Patent Application
20080054867
The present invention relates to voltage regulators for electronic circuits, and more particularly to low dropout voltage regulators for circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiment and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein.
The present invention is mainly described in terms of particular circuits provided in particular implementations. However, one of ordinary skill in the art will readily recognize that this circuit will operate effectively in other implementations.
To more particularly describe the features of the present invention, please refer to
The voltage reference 12 supplies a reference voltage VREF for the regulator circuit 10. The reference voltage VREF line is connected to the negative input terminal of error amplifier 14, which has an output connected to the gate of regulator transistor device or primary pass device 16. Transistor 16 is shown in the embodiment of
A resistance divider (resistor feedback network) is connected to the drain of the transistor 16. The resistance divider includes three resistors R21, R20, and R1, connected in series from the drain of the transistor 16 to ground. A voltage feedback signal VFB is connected between the second and third resistors, R20 and R1, and is fed back to the positive input terminal of the error amplifier 14. A voltage output signal for the regulator 10 is connected to the drain of the transistor 16. An output load capacitor 18 is connected between the output voltage signal VOUT and ground.
The voltage regulator components described above function as a standard LDO voltage regulator, where VFB operates as a first threshold. The error amplifier 14 compares the feedback voltage VFB, which is a percentage of the output voltage VOUT as determined by the ratio of resistors (R20+R21) and R1, to the voltage VREF from the voltage reference 12. The LDO regulator thus delivers current to the output VOUT via the primary pass device 16 and which is fed back to the error amplifier 14 though the feedback network (R1/(R1+R20+R21)) ((R21+R20)/(R1+R20+R21)). Thus the error amplifier's positive input is connected via the feedback network to a voltage of VFB=(R1/(R1+R20+R21))*VOUT. If VFB drops, the error amplifier compensates by increasing drive to the transistor 16, thus increasing the output voltage VOUT. If VFB rises, then the error amplifier decreases the drive to the transistor device 16, thereby decreasing the output voltage VOUT. The error amplifier output is connected to the gate terminal of transistor device 16 so as to ensure that VOUT is equal to ((R1+R20+R21)/R1)*VREF during normal operation. Thus, the error amplifier output seeks to equalize the voltages at the inputs to the amplifier, to provide a regulated output voltage VOUT that is independent of variations in the supply voltage VIN or load current variations.
The output load capacitor 18 is provided for stability, e.g., to buffer oscillation which may occur in VOUT depending on provided currents. Capacitor 18, however, may be required to be kept to a smaller capacitance value than is desired to compensate for output voltage drops due to switched load changes of the regulator. This may be due to limited available space on an integrated circuit chip, for example, when the capacitor is to be included on the chip itself. Thus, higher output current peaks provided by the regulator may not be sustained with the smaller size capacitor 18.
The regulator circuit 10 of the present invention therefore also includes a switching output current boost circuit 20. Boost circuit 20 allows the deliverance of an additional current to the output during falling output voltage due to high switching output current peaks, and includes a transistor device 22 and a comparator 24. Transistor device (or secondary pass device) 22 is connected to the input voltage VIN at its source and is connected to VOUT and the resistor feedback network at its drain. Transistor 22 is shown as a PMOS device in the embodiment of
In operation, the comparator is used to provide a current boost to the output in the event that VOUT goes below a predetermined value, e.g., when an output drop occurs during a switched current peak. For the embodiment of
Thus, if during a switching current peak the voltage drops while the voltage regulator is still bringing up its normal voltage regulation, then the boost circuit 20 allows more current to be provided to the output. The lower feedback voltage level of VFB2, acting as a second threshold, is less than the feedback voltage level VFB (first threshold), allowing the boost circuit 20 to pass additional current at a lower voltage level than the normal regulated output voltage level. Thus the resistor values of resistors R21 and R20 are determined based on the desired lower feedback voltage level, the point at which it is desired for the additional current through transistor 22 to be provided.
The present invention thus allows the regulator 10 to sustain a higher level of output current during switched current peaks, without having to increase the size and capacitance of the load capacitor 18. This allows the regulator 10 to be implemented more easily on the limited area of an integrated circuit chip. In addition, the boost circuit 20 of the present invention includes a small number of components including transistor 22 and a simple comparator 24, and the invention includes no changes to the primary LDO voltage regulator; thus the circuit is quite inexpensive to implement. Furthermore, the additional current consumption of the single comparator 24 is minimal, and so any significant increase in current consumption of the circuit is avoided. This makes the regulator 10 very suitable for portable and power-limited applications, such as battery powered devices.
In an alternate embodiment, other types of transistors for transistors 16 and 22 can be used. For example, other p-channel transistors can be used, such as PNP (in which the collectors would be connected to VOUT, and the emitters connected to VIN). In other embodiments, n-channel transistors can be used, such as NMOS (source connected to VOUT, drain connected to VIN) or NPN (emitter connected to VOUT, collector connected to VIN). If an n-channel transistor is used for primary transistor 16, then the error amplifier 14 should be inverted so that VREF is connected to the positive input and VFB is connected to the negative input of the amplifier. Likewise, if an n-channel resistor is used for secondary transistor 22, the comparator 24 should be inverted such that VREF is connected to the positive input, and VFB2 is connected to the negative input of the comparator.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
