Patent Application
20210376827
The present invention relates in general to electronic switching, and more particularly to a low emission electronic switch for switching binary signals having relatively long transition times.
Conventional switching techniques are known for making voltage transitions with low electro-magnetic emissions (EME) for meeting electromagnetic compatibility (EMC) standards. The conventional techniques may be sufficient for certain applications, but they present disadvantages for applications in which electromagnetic immunity (EMI) is important and longer transition times are required. The main disadvantages of those techniques are two-fold. A first disadvantage is that they use feedback control. A driver with feedback implies that the circuit is susceptible to disturbances during the transition time. Another disadvantage of feedback control is that the feedback circuit requires a control loop which adds complexity to the design and consumes valuable circuit area.
A second disadvantage of conventional techniques is that they use digitally-driven switches partitioned into many smaller switches in which each switch introduces a small and gradual change in resistance. The conventional technique may be applied to signals or communication buses working on the megahertz (MHz) range because the transitions are relatively fast and hence the number of switch partitions may be manageable. A typical case could be 32 partitions for switching frequency in the MHz range. However, with buses or signals having switching frequency in the kilohertz (kHz) range, the number of partitions required to ensure that each partition contributes very little to the emission is excessive, such as on the order of thousands. In that case, the conventional technique becomes prohibitive in terms of area and circuit complexity.
Embodiments of the present invention are illustrated by way of example and are not limited by the accompanying figures. Similar references in the figures may indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
There is a need for switching binary signals with low electromagnetic emissions (EME) for meeting electromagnetic compatibility (EMC) standards having long transition times without using feedback and without having to use an excessive number of switch partitions. A low emission electronic switch as described herein is able to switch signals having long transition times without using an excessive number of switches or switch partitions. The switch apparatus includes multiple current branches and slope circuitry, in which each current branch has a control input. Each of the current branches develops a corresponding current based on a drive signal applied to the control input, in which it combines with the current of any other activated current branches. The slope circuitry is responsive to an input signal and has multiple drive outputs each coupled to a control terminal of a corresponding one of the current branches. The slope circuitry sequentially activates or deactivates the current branches one at a time in response to transition of the input signal while applying a slope function to each current branch so that the output node follows the predetermined voltage-current function. Each current branch may be implemented using a MOS transistor or the like. Each current branch may include a resistor in series with a corresponding MOS transistor.
In one embodiment, N current branches are sequentially activated or deactivated by N slope control circuits of the slope circuitry. Sequential activation may be achieved using delay circuitry that provides one or more delay signals. In one embodiment, the delay circuitry provides N sequential delay signals responsive to the input signal, in which each delay signal is provided to an input of a corresponding one of the N slope control circuits. The first delay may be zero (i.e., the input signal is provided directly to a first slope control circuit for controlling a first current branch. In another embodiment, the input signal is provided, either directly or through the delay circuitry, to an input of a first control circuit, in which the N slope control circuits are daisy-chained together for sequential operation. In the daisy-chained configuration, the output of the first slope control circuit is coupled to the input of the second slope control circuit, having its output coupled to the input of a third slope control circuit, and so on up to the next-to-last last slope control circuit having its output coupled to the input of a last slope control circuit, which provides an Nth drive output to the Nth electronic switch.
The slope function of each of the slope control circuits provides a corresponding transition delay and is other than a step function. The shape of one or more of the slope functions of each of the slope control circuits may be linear or non-linear. Embodiments described herein illustrate a linear function in which a capacitor is charged or discharged with a relatively constant current level. A constant current may be achieved using a current-starved invertor or the like. Examples of non-linear slope functions include exponential slopes (of any suitable degree) or sinusoidal slopes or the like.
In the illustrated embodiment, the slope circuitry 104 includes a series of N slope control circuits individually labeled slope control 1, slope control 2, . . . , slope control N (or slope control circuits 1-N), each having an input receiving a corresponding one of the delay signals D1-DN, respectively, and each providing a corresponding one of the drive signals GD1-GDN. The switch circuitry 106 includes N electronic switches Q1, Q2, . . . , QN (Q1-QN) forming N switch branches, each having a control input receiving a corresponding one of the drive signals GD1-GDN, and each having current terminals coupled between the output node 108 and GND. The electronic switches Q1-QN are shown as N-type or N-channel devices, more specifically an N-channel MOS (NMOS) transistors, each having a gate terminal as a control input and drain and source terminals as the current terminals coupled between the output node 108 and GND. In other embodiments, the switch circuitry 106 may be configured as alternative polarity devices, such as P-type or P-channel MOS (PMOS) transistors, or as alternative device types, such as N-type or P-type bipolar junction transistors (BJTs) or the like (e.g., NPN or PNP transistors).
In operation, DIN and DOUT transition to opposite binary states with respect to each other. In an initial condition, D1-DN and GD1-GDN each have the same binary state as DIN, in which each of these signals ultimately switch between first and second binary states. In response to DIN transitioning from the first binary state to the second binary state, D1 transitions from the first binary state to the second binary state after a first delay, then D2 transitions from the first binary state to the second binary state after a second delay, and so on up to that last delay signal DN, which transitions after N delays. Each of the N delays may have substantially the same period or may have different periods. Each of the drive signals GD1-GDN begin transitioning in response to a transition of the corresponding one of the delay signals D1-DN. The transition of each of the drive signals GD1-GDN, however, follows a corresponding slope function defined by the corresponding one of the slope control circuits 1-N. Thus, in response to the D1 transition, GD1 transitions following a slope function defined by the slope control circuit 1, in response to the D2 transition, GD2 transitions following a slope function defined by the slope control circuit 2, and so on up to transition of DN, in which GDN transitions following a slope function defined by the slope control circuit N.
The delay circuitry 102 may be implemented in any suitable manner. In one embodiment, for example, the delay circuitry 102 may be implemented as a delay pipeline of delay buffers (not shown) including any combination of non-inverting or inverting delay buffers or the like. In another embodiment, the delay circuitry 102 may be implemented as a pipeline of daisy-chained flip-flops (not shown) driven by a digital clock (not shown) having a suitable frequency for controlling the delay periods. In one embodiment, each of the delays 1-N are substantially the same. In another embodiment, one or more of the delays may be different up to all delays being different from each other. For example, the delay periods may increase or decrease from one to the next.
In an alternative embodiment, the first delay period from DIN to D1 may be bypassed as indicated by connection line 112. In this case, DIN may be provided directly to the input of the first slope control circuit 1. Alternatively, the delay from DIN to D1 may be minimal or zero. The remaining delay signals D2-DN are sequentially delayed in the same manner as previously described yet relative to DIN. Operation is substantially similar although the level of emissions may be changed.
In one embodiment, each of the slope control circuits 1-N may be configured in substantially the same manner with the same slope function for each. In another embodiment, one or more of the slope control circuits 1-N may be configured differently for different slope functions. The shape of one or more slope functions may be linear or non-linear. Examples of non-linear slope functions include exponential slopes (of any suitable degree) or sinusoidal slopes or the like. It is noted that each slope function is other than a simple step function so that none of the switches Q1-QN are digitally-controlled. Each slope function transitions between first and second voltage levels (e.g., between VDD and GND) with a configured or an inherent delay to minimize switching emissions from one switch to the next.
Each of the switches Q1-QN turn on or off in response to transitioning of a corresponding one of the gate drive signals GD1-GDN. If each of the switches Q1-QN are initially off and GD1-GD2 transition from low (e.g., at or near ground) to high (up to VDD), then each of the switches Q1-QN are turned on so that DOUT transitions from high to low. If each of the switches Q1-QN are initially on and GD1-GD2 transition from high to low, then each of the switches Q1-QN are turned off so that DOUT starts low and is pulled high via the pull-up resistor R.
As further described herein, each of the switches Q1-QN may be sized to achieve a corresponding current during the switching process. Although each switch may have a particular on-resistance when in its corresponding triode region, one or more of the switches Q1-QN may also be in, or may pass through, its corresponding saturation region of operation during the switching process. This means that each switch develops a corresponding current when acting as a current source or as a resistor during each switching transition. Roughly speaking, during switching, when the drain voltage is larger than the gate voltage, then the transistor is in its saturation region, and when the drain voltage is at or near the gate voltage, then the transistor is in its triode region. The amount of time that the switches Q1-QN are in triode or saturation depends on the particular implementation, the voltages driving the switches, and the voltage level of VDD.
VDD and the output node 208, in which the output node 208 develops the output signal DOUT in similar manner as the switch circuit 100.
The input signal DIN is provided to the delay circuitry 202, which outputs a single delay signal D1 to an input of a first slope control circuit 1 of the slope circuitry 204. The slope circuitry 204 provides the drive signals GD1-GDN to the control inputs of the switches Q1-QN, respectively, in similar fashion as the switch circuit 100. In this case, however, rather than receiving separate delay signals from a delay circuit, the slope circuitry 204 includes N slope control circuits 1-N coupled in a daisy-chained configuration. In particular, the first drive signal GD1 output from the first slope control circuit 1 is provided to an input of the second slope control circuit 2, having an output providing the drive signal GD2 to an input of the third second slope control circuit 3 (not shown), and so on up to the last slope control circuit N, having an input receiving a gate drive output from a next-to-last slope control circuit N-1, and having an output providing GDN to the control input of the last switch QN.
Operation of the switch circuit 200 is substantially similar to the switch circuit 100, except that rather than propagating delay via the delay circuitry 202, delay is iteratively propagated via the delayed gate drive signals GDx in which x is an index from 1 to N-1. Thus, after DIN transitions, D1 transitions after the delay through the delay circuitry 202. GD1 begins transitioning according to the slope function of the slope control circuit 1 after D1 transitions. GD2-GDN each begin transitioning according to the slope functions of the slope control circuit 2-N, respectively, one at a time in iterative fashion.
In an alternative embodiment, the delay circuitry 202 may be eliminated (or otherwise bypassed) as indicated by connection line 212. In this case, DIN is provided directly to the input of the first slope control circuit 1. Operation is substantially similar although the level of emissions may be modified somewhat.
Each of the slope control circuits 1-N of the switch circuit 200 may be configured in substantially similar manner as described for the switch circuit 200, in which each slope function may be the same or different and may be linear or non-linear depending upon the configuration. Again, each slope function transitions between first and second voltage levels with a configured or an inherent delay to minimize switching emissions from one switch to the next. As previously described, each of the switches Q1-QN is sized to achieve a corresponding amount of current during the switching process. The amount of time that the switches Q1-QN are in triode or saturation depends on the particular implementation, the voltages driving the switches, and the voltage level of VDD.
The slope circuitry 304 of the switch circuit 300 is daisy-chained in similar manner as the slope circuitry 204 of the switch circuit 200, except that the delay circuitry 302 is interposed between the slope circuitry 304 and the switch circuitry 306. The slope circuitry 304 includes N slope control circuits 1-N and the delay circuitry 302 includes N delay circuits D1, D2, . . . , DN (D1-DN). The input signal DIN is provided to the input of the first slope control circuit 1, having its output coupled to the input of a first delay circuit D1, having an output providing the first drive signal GD1. GD1 is provided to the input of the second slope control circuit 2, having its output coupled to the input of a second delay circuit D2, having an output providing the first drive signal GD2. GD2 is provided to the input of the next slope control circuit having its output provided to the input of the next delay circuit proving the next drive signal and so on up to the last slope control circuit N, which receives the drive signal GDN-1 and has an output provided to the input of the last delay circuit DN providing the last drive signal GDN.
Each delay circuit D1-DN of the delay circuitry 302 is illustrated as a buffer or the like which may be implemented as any number of delay buffers providing a corresponding amount of delay. Operation of the switch circuit 300 is substantially similar to the switch circuit 200 in which the output of each of the slope control circuits 1-N is delayed and the delay circuitry outputs providing the delayed gate drive signals GDx are iteratively coupled to the next slope and delay circuit from first to last. In an alternative embodiment, the first delay circuit D1 may be eliminated (or otherwise bypassed) as indicated by connection line 312. In this case, the output of the first slope control circuit 1 is provided as GD1. Operation is substantially similar.
Each of the slope control circuits 1-N of the switch circuit 300 may be configured in substantially similar manner as described for the switch circuits 100 or 200, in which each slope function may be the same or different and may be linear or non-linear depending upon the configuration. Again, each slope function transitions between first and second voltage levels with a configured or an inherent delay to minimize switching emissions from one switch to the next. As previously described, each of the switches Q1-QN is sized to achieve a corresponding amount of current during the switching process. The amount of time that the switches Q1-QN are in triode or saturation depends on the particular implementation, the voltages driving the switches, and the voltage level of VDD.
In the illustrated embodiment of
Operation is similar for sequentially turning off the switches Q1-Q6. Just before a sequential time t11, the input signal D1 transitions from a low to high. After the first delay, D1 transitions from low to high at time t11 with negligible switching delay, and GD1 begins increasing from low to high with a substantially linear slope turning Q1 back on. As Q1 turns on, DOUT begins to fall. After the second delay, D2 transitions from low to high at time t12 with negligible switching delay, and GD2 begins sloping up from low to high with a substantially linear slope turning on Q2. At time t12, GD1 is still rising and has only reached about half its value when GD2 begins increasing. As Q2 turns on, DOUT continues to fall at an increased rate. Operation repeats in this manner for subsequent delays 3-6 for times t13 to t16, in which signals D3-D6 sequentially transition from high to low, GD3-GD6 begin sequentially sloping up from low to high, and switches Q3-Q6 are sequentially turned on. As the switches Q1-Q6 are sequentially turned on in this manner, DOUT decreases towards its low voltage level. At subsequent time t17, the signals GD1-GD6 have all reached their high levels and DOUT is pulled low.
It is noted that if the slope circuitry 104 were eliminated or otherwise replaced by digital drivers such that the switches Q1-Q6 were digitally driven, DOUT would transition in stair-step fashion generating a significant amount of emissions. Instead, the slope functions of the slope circuitry 104 smooths out the transitions substantially reducing the amount of emissions. Although only 6 switches are shown, the number of switches may be adjusted to ensure that the corresponding amount of emissions meet the applicable EMC standards under all circuitry and ambient operating conditions (e.g., given applicable variations and ranges of voltages, circuitry, currents, temperature, etc.).
Operation of the switch circuits 200 and 300 are substantially similar to that of the switch circuit 100 for the same number of switches. In any given configuration, the corresponding emissions may be calculated or empirically determined, in which N, the slope functions and the switch sizes may be adjusted to reduce emissions to an allowable or acceptable level.
Given the load resistance (e.g., pull-up resistance R of resistor 110), the desired voltage VLIN and the desired current Ids, an on-resistance value for each switch may be determined according to Ohm's law. Given the total resistance value at each time, the on-resistance value for each individual switch can be determined using simple algebra. The on-resistance R(Q1) of the first switch Q1 is the same as the total resistance value, or R(Q1)=R(t)=26,267 Ω. The on-resistance R(Q2) of the second switch Q2 is calculated based on R(Q1)=26,267Ω and R(t)=12,700Ω for a parallel combination in which R(t)=R(Q1)∥R(Q2)=R(Q1∥Q2)=R(Q1)*R(Q2)/[R(Q1)+R(Q2)]=12,700Ω. Solving for R(Q2), R(Q2)=R(t)/[1-R(t)/R(Q1)]=26,267/[1-12,700/26,267]=24,589Ω. The on-resistance of the third switch R(Q3) is calculated based on R(Q1∥Q2) and R(t)=6,133Ω, so that R(Q3)=R(t)/[1-R(t)/R(Q1∥Q2)]=6,133/[1-6,133/12,700]=11,861Ω. The on-resistances of the remaining switches Q4 to Q31 may be determined in the same manner to achieve the corresponding value of R(t) according to the chart 402.
It is noted that the size of each of the switches Q1-Q31 may be selected and adjusted to achieve a target on-resistance. Also, if a switch needs to have an on-resistance that is higher than the minimum size switch for a given configuration, a resistor in series with the current terminals of the switching resistor can be added to implement the desired on-resistance. It is also noted that in this configuration, the on-resistances may be selected and used to provide an initial configuration. As previously described, however, each of the switches Q1-QN in a given configuration may be sized to target a corresponding current level during the switching process, and that each switch may transition between its off, triode, and saturation regions during the switching process. The switch sizes may be adjusted accordingly.
The current mirror circuitry 802 includes a PMOS transistor PA, a current source 808, and an NMOS transistor NA coupled between VDD and GND and developing a current I. The source of PA is coupled to VDD, and its gate and drain terminals are coupled to an upper node 810 further coupled to an input of the current source 808. An output of the current source 808 is coupled to a lower node 812, which is further coupled to the drain and gate terminals of NA having its source terminal coupled to GND. Although the current mirror circuitry 802 is shown as a single current source driving each of the slope control circuits SC1-SCN, in an alternative embodiment separate current mirrors with corresponding current sources may be provided for each slope control circuit.
The slope control circuit SC1 has an input node 820 receiving the delay signal D1 (which is the first delay signal of the switch circuit 100 or the only delay signal for the switch circuit 200), or receiving the input signal DIN (for the switch circuit 300). Node 820 is internally coupled to the gate terminal of a PMOS transistor P1 and to the gate terminal of an NMOS transistor N1. P1 has its source terminal coupled to VDD and its drain terminal coupled to an intermediate node 822. N1 has its source terminal coupled to GND and its drain terminal coupled to node 822. Node 822 is further coupled to the gate terminal of another PMOS transistor P2 and to the gate terminal of another NMOS transistor N2. The drain terminals of P2 and N2 are coupled together at an output node 824 developing the first drive signal GD1. Another PMOS transistor P3 has a source terminal coupled to VDD, a gate terminal coupled to the upper node 810, and a drain terminal coupled to the source terminal of P2. Another NMOS transistor N3 has a source terminal coupled to GND, a gate terminal coupled to the lower node 812, and a drain terminal coupled to the source terminal of N2. A capacitor C1 is coupled between the output node 824 and GND. As noted above, each of the remaining slope control circuits SC2-SCN) may be configured in substantially the same manner. The last slope control circuit SCN has an input receiving either delay signal DN (for the switch circuit 100) or a drive signal GDN-1 (for the switch circuit 200), and has an output providing the drive signal GDN.
P1 and N1 form a first inverter for switching the intermediate node 822 between VDD and GND depending upon the state of the input signal D1. P2, P3, N2 and N3 form a “current-starved” inverter that drives current I to either charge (CHG) or discharge (DCHG) the capacitor C1 depending upon the state of the intermediate node 820. P3 is coupled in a current mirror configuration with PA and N3 is coupled in a current mirror configuration with NA so that the drain-source current through each of P3, P2, N2, and N3 is I as controlled by the current source 808 of the current mirror circuitry 802. When D1 is asserted high, intermediate node 822 is asserted low turning P2 on and N2 off, so that a charge (CHG) current I flows through P3 and P2 to charge the capacitor C1. When D1 is asserted low, intermediate node 822 is asserted high turning N2 on and P2 off, so that a discharge (DCHG) current I flows through N3 and N2 to discharge the capacitor C1. In this manner, the capacitor C1 is effectively charged or discharged with a constant current I to create a linear slope voltage function at the drive signal GD1 such as shown in
In one embodiment, I is a constant current value. It is noted, however, that the current source 808 does not need to be a constant function. Other functions are contemplated, such as a sinusoidal function (e.g., half-sine wave) or an exponential function or the like. The illustrated embodiment uses constant current through a gate capacitor as the slope function. Alternative slope functions may be implemented. In another embodiment, low pass filters using resistors and capacitors may be used. In yet another embodiment, split-switches may be used. In any event, at least one up to all of the slope functions are other than a non-delayed step function.
It is noted that each of the switches Q1-QN of the switch circuitry, when used alone (as shown for the switch circuitry 106, 206, or 306) or in combination with a corresponding one of the N resistors R1-RN (as shown for the switch circuitry 908), forms a corresponding one of N current branches coupled between an output node (e.g., 108, 208, 308, 708) and a reference node (e.g., GND). Each current branch develops a corresponding current as it is being activated or deactivated by the corresponding slope function such that, when combined with other current branches during the switching process, causes the output node providing the DOUT voltage to follow the target voltage-current function with minimal or reduced EME.
Although there is no theoretical limit to the number N, such that N may be in the hundreds or even thousands, an excessive number of switching branches becomes prohibitive in terms of area and circuit complexity. In a conventional configuration using digitally-driven switches, each switch can advance the signal only so much without generating significant emissions. In this manner, an excessive number of switches (e.g., thousands) would be required using digitally-driven switches for a signal having a relatively low switching frequency and a corresponding long transition time to meet the applicable EMC standards. Instead, a low emission electronic switch implemented according to embodiments described herein reduces EME per switch so that N may be substantially reduced as compared to the conventional configuration while still meeting the applicable EMC standards. Thus, N can be limited to a more practicable number, such as a hundred or less (e.g., 32 in some embodiments) rather than thousands. In any given configuration, mathematical or empirical methods or the like may be used to determine a minimum number of switches, the switch sizes, series resistor values (if used), and the corresponding delays that perform switching while ensuring that the EMC standards are met.
Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the scope of the invention as defined by the appended claims. For example, variations of positive logic or negative logic may be used in various embodiments in which the present invention is not limited to specific logic polarities, device types or voltage levels or the like. For example, logic states, such as logic low and logic high may be reversed depending upon whether the pin or signal is implemented in positive or negative logic or the like. In some cases, the logic state may be programmable in which the logic state may be reversed for a given logic function.
The terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
