Patent Application
20250103082
The present disclosure generally relates to differential voltage reference generator circuits and, in particular, to a differential voltage reference generator with low flicker noise.
Reference is made to
The current mirroring circuit 12 is formed by p-channel metal oxide semiconductor field effect transistor (MOSFET) devices M1, M2 and M3. The source terminals of transistors M1, M2 and M3 are coupled, preferably connected, to the supply node Vdd. The gate terminals of transistors M1, M2 and M3 are coupled, preferably connected, to each other and biased by a voltage Vout to generate mirrored currents. The drain terminal of transistor M1 outputs a first mirrored current, the drain terminal of transistor M2 outputs a second mirrored current, and the drain terminal of transistor M3 outputs a third mirrored current. The third mirrored current output from the drain terminal of transistor M3 is applied across resistor R3 to generate the bandgap reference voltage Vbg at an output node of the circuit 10. Resistor R3 has a first terminal coupled, preferably connected, to the drain of transistor M3 at the output node and a second terminal coupled, preferably connected, to the ground node Gnd.
The bandgap core circuit 14 includes a differential amplifier circuit 16, for example comprising an operational amplifier (OP-AMP), configured in a current control feedback loop that generates the bias voltage Vout which controls generation of the mirrored currents by the transistors M1, M2 and M3. The non-inverting (+) input of the differential amplifier circuit 16 receives a voltage V+ at the drain of the transistor M1 and the inverting (−) input of the differential amplifier circuit 16 receives a voltage V− at the drain of the transistor M2. The bandgap core circuit 14 further includes PNP bipolar transistors Q1 and Q2. The collector terminals of transistors Q1 and Q2 are coupled, preferably connected, to the ground node Gnd. The base terminals of transistors Q1 and Q2 are coupled, preferably connected, to each other and to the ground node Gnd. The transistors Q1 and Q2 of the bandgap core circuit 14 are thus each connected in diode-configuration. The emitter terminal of transistor Q1 is coupled, preferably connected, to an intermediate node 18. The emitter terminal of transistor Q2 is coupled, preferably connected, to the drain of transistor M2 at the inverting (−) input of the differential amplifier circuit 16. A resistor R1 has a first terminal coupled, preferably connected, to the intermediate node 18 and a second terminal coupled, preferably connected, to the drain of transistor M1 at the non-inverting (+) input of the differential amplifier circuit 16. A first resistor R2 has a first terminal coupled, preferably connected, to the drain of transistor M1 at the non-inverting (+) input of the differential amplifier circuit 16 and a second terminal coupled, preferably connected, to the ground node Gnd. A second resistor R2 has a first terminal coupled, preferably connected, to the emitter of transistor Q2 at the inverting (−) input of the differential amplifier circuit 16 and a second terminal coupled, preferably connected, to the ground node Gnd.
As an example, the differential amplifier circuit 16 includes a differential pair 20 of input transistors M5, M6 coupled to a current mirror load circuit 22 formed by transistors M7, M8. The input transistors M5, M6 are n-channel MOSFETs. The load transistors M7, M8 are p-channel MOSFETs. The common source terminals of the transistors M5 and M6 are coupled, preferably connected, to a tail current source 20 connected to the ground node Gnd. The gate terminal of input transistor M5 (at the non-inverting (+) input) receives the voltage V+ at the drain of the transistor M1 and the gate terminal of the input transistor M6 (at the inverting (−) input) receives the voltage V− at the drain of the transistor M2. The drain terminal of input transistor M5 is coupled, preferably connected, to the drain and gate terminals of the load transistor M7. The drain terminal of input transistor M6 is coupled, preferably connected, to the drain terminal of the load transistor M8 at the output of the amplifier. The gate terminals of the transistors M7, M8 are coupled, preferably connected, to each other. The transistor M7 is connected in diode-configuration. The output voltage Vout of the differential amplifier circuit 16 is generated at the common drain terminals of transistors M6, M8 and is a function of the difference between the voltages V+ and V−, and the magnitudes of the first, second and third mirrored currents at the drains of transistors M1, M2 and M3 is a function of the voltage Vout.
The principle of operation of the circuit 10 is to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage, and then add those voltages in a scaled proportion to achieve a cancelation of the positive and negative temperature coefficients.
The generating of the PTAT component uses the difference in base to emitter voltages (VBE) between two forward bias voltages having different current densities (m) using transistors Q1 and Q2. The voltage across resistor R1 is then PTAT in nature:
The current flowing through the resistor R2 is CTAT:
The output bandgap voltage Vbg can be expressed as follows:
The operating point of the circuit 10 can accordingly be scaled by setting of the resistances for resistors R2 and R3, and the temperature coefficient can be adjusted by setting of the resistances for resistors R1 and R2.
There is a recognized problem with the circuit 10. The MOSFETs M5, M6, M7 and M8 introduce flicker (1/f) noise which can perturb the output voltage Vbg. This is a concern when the output voltage Vbg provides a reference voltage for a noise sensitive circuit (like an analog-to-digital converter (ADC)).
To address the issue of flicker noise, there is a teaching in the art to use a chopper technique. See, for example, U.S. Patent Application Publication No. 2010/0295529 and U.S. Pat. No. 10,983,547 (both incorporated herein by reference). However, there are a number of drawbacks associated with the use of the chopper technique including the need for more complicated circuitry and a stable (for example, external) clock source to control the switching operations.
In an embodiment, a circuit comprises: a bandgap voltage generator circuit formed using only bipolar transistors and including a transconductance amplifier circuit in a current control feedback loop having a differential input which receives a bipolar transistor base current, wherein the bandgap voltage generator circuit includes a first output node generating a first current comprising a bandgap reference current plus the bipolar transistor base current and a second output node generating a second current comprising the bandgap reference current minus the bipolar transistor base current; and a transresistance amplifier circuit comprising: a differential amplification circuit having a non-inverting input configured to receive the first current, an inverting input configured to receive the second current, a non-inverting output and an inverting output; a first feedback resistor coupled between the non-inverting input and the inverting output; a second feedback resistor coupled between the inverting input and the non-inverting output; and a compensation current sink circuit configured to sink a first compensation current from the non-inverting input corresponding to the base current and configured to sink a second compensation current from the inverting input corresponding to the base current.
In an embodiment, a circuit comprises: a first current mirroring circuit including a first bipolar transistor, a second bipolar transistor, a third bipolar transistor and a fourth bipolar transistor, wherein a first current is output by the third bipolar transistor and a second current is output by the fourth bipolar transistor; a second current mirroring circuit configured to mirror the second current and generate a third current; a bandgap core circuit including: a fifth bipolar transistor and sixth bipolar transistor coupled, respectively, to the first and second bipolar transistors and configured to use a difference in base to emitter voltages of the fifth and sixth bipolar transistors to generate a complementary to absolute temperature (CTAT) voltage and a proportional to absolute temperature (PTAT) voltage from currents output by the first and second bipolar transistors; and a transconductance amplification circuit having a differential input comprising seventh and eighth bipolar transistors coupled, respectively, to the first and second bipolar transistors, the seventh bipolar transistor having a base configured to receive a first base current and the eighth bipolar transistor having a base configured to receive a second base current, and an output coupled to apply a bias current to base terminals of the first, second, third and fourth bipolar transistors; and a differential amplification circuit having a non-inverting input configured to receive the first current, an inverting input configured to receive the third current, a ninth bipolar transistor having a base coupled to the non-inverting input and configured to sink a first compensation current corresponding to the first base current and a tenth bipolar transistor having a base coupled to the inverting input and configured to sink a second compensation current corresponding to the second base current.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose identical structural, dimensional and material properties.
Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements coupled together, this signifies that these two elements can be connected or they can be coupled via one or more other elements.
In the following description, when reference is made to terms qualifying absolute positions, such as terms “front”, “rear”, “top”, “bottom”, “left”, “right”, etc., or relative positions, such as terms “above”, “under”, “upper”, “lower”, etc., or to terms qualifying directions, such as terms “horizontal”, “vertical”, etc., unless specified otherwise, it is referred to the orientation of the drawings.
Reference is now made to
The current mirror circuit 112 is formed by PNP bipolar transistors QA, QB and QC. The emitter terminals of transistors QA, QB and QC are coupled, preferably connected, to the supply node Vdd. The base terminals of transistors QA, QB and QC are coupled, preferably connected, to each other and biased by a bias current Ibias to generate mirrored currents. The collector terminal of transistor QA outputs a first mirrored current, the collector terminal of transistor QB outputs a second mirrored current, and the collector terminal of transistor QC outputs a third mirrored current. The third mirrored current output from the collector terminal of transistor QC is applied across resistor R3 to generate the bandgap reference voltage Vbg at an output node 134 of the circuit 110. Resistor R3 has a first terminal coupled, preferably connected, to the collector of transistor QC at the output node 134 and a second terminal coupled, preferably connected, to the ground node Gnd.
The bandgap core circuit 114 includes a differential operational transconductance amplifier (OTA) circuit 116 configured in a current control feedback loop that generates an output current Iout which controls generation of the mirrored currents by the transistors QA, QB and QC. The non-inverting (+) input of the differential OTA circuit 116 receives a voltage V+ at the collector of the transistor QA and the inverting (−) input of the differential OTA circuit 116 receives a voltage V− at the collector of the transistor QB. The bandgap core circuit 114 further includes PNP bipolar transistors Q1 and Q2. The collector terminals of transistors Q1 and Q2 are coupled, preferably connected, to a virtual ground node 150. The base terminals of transistors Q1 and Q2 are coupled, preferably connected, to each other and to the virtual ground node 150. The transistors Q1 and Q2 of the bandgap core circuit 114 are thus each connected in diode-configuration. The emitter terminal of transistor Q1 is coupled, preferably connected, to an intermediate node 118. The emitter terminal of transistor Q2 is coupled, preferably connected, to the collector of transistor QB at the inverting (−) input of the differential OTA circuit 116. A resistor R1 has a first terminal coupled, preferably connected, to the intermediate node 18 and a second terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 116. A first resistor R2 has a first terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 116 and a second terminal coupled, preferably connected, to the virtual ground node 150. A second resistor R2 has a first terminal coupled, preferably connected, to the emitter of transistor Q2 at the inverting (−) input of the differential OTA circuit 116 and a second terminal coupled, preferably connected, to the virtual ground node 150.
A resistor Rshift has a first terminal coupled, preferably connected, to the virtual ground node 150 and a second terminal coupled, preferably connected, to a circuit ground node Gnd. It will be noted that in an alternative implementation, the resistor Rshift may be omitted and the virtual ground node 150 and ground node Gnd would then be the same node. This alternative implementation is indicated in
The differential OTA circuit 116 includes a differential pair 120 of input transistors Q5, Q6 coupled to a current mirror load circuit 122 formed by transistors Q7, Q8. The input transistors Q5, Q6 are NPN bipolar transistors. The load transistors Q7, Q8 are PNP bipolar transistors. The common emitter terminals of the transistors Q5 and Q6 are coupled, preferably connected, to a tail current source 124 connected to the ground node Gnd. The base terminal of input transistor Q5 (at the non-inverting (+) input) receives the voltage V+ at collector of the transistor QA (as well as a base current Ib) and the base terminal of the input transistor Q6 (at the inverting (−) input) receives the voltage V− at collector of the transistor QB (as well as a base current Ib). The collector terminal of input transistor Q5 is coupled, preferably connected, to the collector and base terminals of the load transistor Q7. The collector terminal of input transistor Q6 is coupled, preferably connected, to the collector terminal of the load transistor Q8 at the output of the amplifier. The base terminals of the transistors Q7, Q8 are coupled, preferably connected, to each other. The transistor Q7 is connected in diode-configuration. The output current Iout of the differential OTA circuit 116 generated at the common collector terminals of transistors Q6 and Q8 is a function of the difference between the voltages V+ and V−. A stabilization capacitor Cs has a first terminal coupled, preferably connected, to the common collector terminals of transistors Q6 and Q8 and a second terminal coupled, preferably connected, to the ground node Gnd.
The use of an OTA amplifier 116 formed by bipolar transistor devices, as opposed to the differential amplifier 16 formed by MOSFET devices in
The current sink circuit 115 replicates one-half of the differential OTA circuit 116 with a bipolar PNP transistor QD (matching the transistor Q7), an NPN transistor QE (matching the transistor Q5), and a current source 140 (corresponding to the tail current source 124 but with a different current magnitude). The emitter terminal of transistor QD is coupled, preferably connected, to the supply node Vdd. The collector and base terminals of transistor QD are coupled, preferably connected, to each other at intermediate node 142. The transistor QD is connected in diode-configuration. The collector terminal of transistor QE is coupled, preferably connected, to intermediate node 142. The base terminal of transistor QE is coupled, preferably connected, to the output node 134 and is biased by the compensation current Ib′ corresponding to the base current Ib at the pair of transistors 120 in amplifier 116. The emitter terminal of transistor QE is coupled, preferably connected, to current source 140 connected to the ground node Gnd. Because the current sink circuit 115 replicates only one-half of the differential OTA circuit 116, the current source 140 sinks a current Is with a magnitude that is one-half the magnitude of the current 2Is sunk by the current source 124.
Since the amplifier 116 is of the OTA-type, it cannot effectively drive a resistive load (i.e., it cannot sink with current Iout a current with a magnitude of 31b from the connected bases of the transistors QA, QB and QC) without introducing a significant offset to the amplifier input. To address this issue, the bandgap core circuit 114 further includes a current buffer circuit 130. The output current Iout is buffered by the current buffer circuit 130 to generate the bias current Ibias. The magnitude of the first, second and third mirrored currents at the collectors of transistors QA, QB and QC is a function of the bias current Ibias.
The current buffer circuit 130 comprises a first follower circuit formed by a first transistor T1 having a control terminal coupled, preferably connected, to receive the amplifier output current Iout, a reference terminal coupled, preferably connected, to the ground node Gnd and a follower terminal coupled, preferably connected, to receive a first source current Isrc generated by a first current source 150 coupled to the supply node Vdd. The current buffer circuit 130 further comprises a second follower circuit formed by a second transistor T2 having a control terminal coupled, preferably connected, to the follower terminal of the transistor T1, a reference terminal coupled, preferably connected, to the supply node Vdd and a follower terminal coupled, preferably connected, to receive a sink current Isnk generated by a second current source 152 coupled to the ground node Gnd. The bias current Ibias is generated at the follower terminal of the transistor T2.
In a preferred implementation as shown in
The use of first and second follower circuits in the current buffer circuit 130 makes it possible to maintain approximately the same voltage at the collector terminals of transistors Q7, Q8 in order to guarantee the linear operation of transistor Q8 in generating the current Iout and thus avoid any early differential effect.
In the implementation which uses the resistor Rshift, the resistance of the resistor Rshift is selected as a function of the mirrored first and second currents (in transistors QA and QB) and the base current Ib so that the voltage drop across the resistor is equal or substantially equal (within design tolerances) to the voltage drop across the current source 124 in the amplifier 116.
Reference is now made to
The current mirror circuit 212 is formed by PNP bipolar transistors QA, QB, QC and QD as well as NPN bipolar transistors QE and QF. The emitter terminals of transistors QA, QB, QC and QD are coupled, preferably connected, to the supply node Vdd. The base terminals of transistors QA, QB, QC and QD are coupled, preferably connected, to each other and biased by a bias current Ibias to generate mirrored currents. The collector terminal of transistor QA outputs a first mirrored current, the collector terminal of transistor QB outputs a second mirrored current, the collector terminal of transistor QC outputs a third mirrored current and the collector terminal of transistor QD outputs a fourth mirrored current. The third mirrored current output from the collector terminal of transistor QC is applied (perhaps through a series-connected input resistor—not explicitly shown) to the non-inverting (+) input of a fully differential amplifier 217 of the transresistance amplifier circuit 215. The fourth mirrored current output from the collector terminal of transistor QD is mirrored by transistors QE and QF of circuit 219 and applied (perhaps through a series-connected input resistor—not explicitly shown) to the inverting (−) input of the fully differential amplifier 217.
The transresistance amplifier circuit 215 further includes a first feedback resistor R3 having a first terminal coupled, preferably connected, to the non-inverting input of the fully differential amplifier 217 and a second terminal coupled, preferably connected, to the inverting output of the fully differential amplifier 217. A second feedback resistor R3 has a first terminal coupled, preferably connected, to the inverting input of the fully differential amplifier 217 and a second terminal coupled, preferably connected, to the non-inverting output of the fully differential amplifier 217.
The emitter terminals of transistors QE and QF of mirror circuit 219 are coupled, preferably connected, to a reference voltage (for example, ground) node 250, and the collector terminal of transistor QE is coupled, preferably connected, to the collector terminal of transistor QD, the collector terminal of transistor QF is coupled, preferably connected, to the inverting input of fully differential amplifier 217, and the base terminals of transistors QE and QF are coupled, preferably connected, to each other and to the collector of transistor QE.
The bandgap core circuit 214 includes a differential operational transconductance amplifier (OTA) circuit 216 configured in a current control feedback loop that generates an output current Iout which controls generation of the mirrored currents by the transistors QA, QB, QC and QD. The non-inverting (+) input of the differential OTA circuit 216 receives a voltage V+ at the collector of the transistor QA and the inverting (−) input of the differential OTA circuit 216 receives a voltage V− at the collector of the transistor QB. The bandgap core circuit 214 further includes PNP bipolar transistors Q1 and Q2. The collector terminals of transistors Q1 and Q2 are coupled, preferably connected, to the reference voltage (ground) node 250. The base terminals of transistors Q1 and Q2 are coupled, preferably connected, to each other and to the ground node 250. The transistors Q1 and Q2 of the bandgap core circuit 214 are thus each connected in diode-configuration. The emitter terminal of transistor Q1 is coupled, preferably connected, to an intermediate node 218. The emitter terminal of transistor Q2 is coupled, preferably connected, to the collector of transistor QB at the inverting (−) input of the differential OTA circuit 216. A resistor R1 has a first terminal coupled, preferably connected, to the intermediate node 218 and a second terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 216. A first resistor R2 has a first terminal coupled, preferably connected, to the collector of transistor QA at the non-inverting (+) input of the differential OTA circuit 216 and a second terminal coupled, preferably connected, to the ground node 250. A second resistor R2 has a first terminal coupled, preferably connected, to the emitter of transistor Q2 at the inverting (−) input of the differential OTA circuit 216 and a second terminal coupled, preferably connected, to the ground node 250.
The differential OTA circuit 216 includes a differential pair 220 of input transistors Q5, Q6 coupled to a current mirror load circuit 222 formed by transistors Q7, Q8. The input transistors Q5, Q6 are NPN bipolar transistors. The load transistors Q7, Q8 are PNP bipolar transistors. The common emitter terminals of the transistors Q5 and Q6 are coupled, preferably connected, to a tail current source 224 connected to the ground node Gnd. The base terminal of input transistor Q5 (at the non-inverting (+) input) receives the voltage V+ at collector of the transistor QA (as well as a base current Ib) and the base terminal of the input transistor Q6 (at the inverting (−) input) receives the voltage V− at collector of the transistor QB (as well as a base current Ib). The collector terminal of input transistor Q5 is coupled, preferably connected, to the collector and base terminals of the load transistor Q7. The collector terminal of input transistor Q6 is coupled, preferably connected, to the collector terminal of the load transistor Q8 at the output of the amplifier. The base terminals of the transistors Q7, Q8 are coupled, preferably connected, to each other. The transistor Q7 is connected in diode-configuration. The output current Iout of the differential OTA circuit 216 generated at the common collector terminals of transistors Q6 and Q8 is a function of the difference between the voltages V+ and V−. A stabilization capacitor Cs has a first terminal coupled, preferably connected, to the common collector terminals of transistors Q6 and Q8 and a second terminal coupled, preferably connected, to the ground node Gnd.
The bandgap core circuit 214 further includes a current buffer circuit 230. The output current Iout is buffered by the current buffer circuit 230 to generate the bias current Ibias. The magnitude of the first, second, third and fourth mirrored currents at the collectors of transistors QA, QB, QC and QD is a function of the bias current Ibias.
The current buffer circuit 230 comprises a first follower circuit formed by a first transistor T1 having a control terminal coupled, preferably connected, to receive the amplifier output current Iout, a reference terminal coupled, preferably connected, to the ground node Gnd and a follower terminal coupled, preferably connected, to receive a first source current Isrc generated by a first current source 250 coupled to the supply node Vdd. The current buffer circuit 230 further comprises a second follower circuit formed by a second transistor T2 having a control terminal coupled, preferably connected, to the follower terminal of the transistor T1, a reference terminal coupled, preferably connected, to the supply node Vdd and a follower terminal coupled, preferably connected, to receive a sink current Isnk generated by a second current source 252 coupled to the ground node Gnd. The bias current Ibias is generated at the follower terminal of the transistor T2.
In a preferred implementation as shown in
The use of first and second follower circuits in the current buffer circuit 230 makes it possible to maintain approximately the same voltage at the collector terminals of transistors Q7, Q8 in order to guarantee the linear operation of transistor Q8 in generating the current Iout and thus avoid any early differential effect.
The fully differential amplifier circuit 217 includes an input stage formed by a differential pair 260 of input transistors Q9, Q10 coupled to a current mirror load circuit 262 formed by transistors Q11, Q12. The input transistors Q9, Q10 are NPN bipolar transistors. The load transistors Q11, Q12 are PNP bipolar transistors. The common emitter terminals of the transistors Q9 and Q10 are coupled, preferably connected, to a tail current source 264 connected to the ground node Gnd. The transistors Q9, Q10 and tail current source 264 are configured to respectively match the transistors Q5, Q6 and tail current source 224 (i.e., replica transistor devices and same current magnitudes for the current sources).
The base terminal of input transistor Q9 (at the non-inverting (+) input) receives the voltage Vin+ at the collector of the transistor QC (as well as a base current Ib′) and the base terminal of the input transistor Q9 (at the inverting (−) input) receives the voltage Vin− at the collector of the transistor QE (as well as a base current Ib′). The collector terminal of input transistor Q9 is coupled, preferably connected, to the collector and base terminals of the load transistor Q11. The collector terminal of input transistor Q10 is coupled, preferably connected, to the collector terminal of the load transistor Q12 at the output of the amplifier. The base terminals of the transistors Q11, Q12 are coupled, preferably connected, to each other and receive a bias control voltage VC.
The positive output voltage Vout+ generated at the common collector terminals of transistors Q10 and Q12 is a function of the difference between the voltages V+ and V− and is applied to an input of an output stage including a first flip voltage follower circuit 270. The first flip voltage follower circuit 270 includes a transistor T3 coupled, preferably connected, in series with a transistor T4. Transistors T3 and T4 are both p-channel MOSFET devices. The positive output voltage Vout+, stabilized by a capacitor Cs, is applied to the gate terminal of transistor T3. The source of transistor T4 is coupled, preferably connected, to the supply node Vdd. The drain of transistor T4 is coupled, preferably connected, to the source of transistor T3 at the non-inverting output of amplifier 217 where the positive differential output reference voltage REFP is generated. The gate of transistor T4 is coupled, preferably connected, to the drain of transistor T3. The drain of transistor T3 is further connected to a current source 252 configured to generate a bias current sunk from transistor T3 to the ground node.
The negative output voltage Vout-generated at the common collector terminals of transistors Q9 and Q11 is a function of the difference between the voltages V+ and V− and is applied to an input of the output stage including a second flip voltage follower circuit 272. The second flip voltage follower circuit 272 includes a transistor T5 coupled, preferably connected, in series with a transistor T6. Transistors T5 and T6 are both n-channel MOSFET devices. The negative output voltage Vout-, stabilized by a capacitor Cs, is applied to the gate terminal of transistor T5. The source of transistor T6 is coupled, preferably connected, to the ground node. The drain of transistor T6 is coupled, preferably connected, to the source of transistor T5 at the inverting output of amplifier 217 where the negative differential output reference voltage REFN is generated. The gate of transistor T6 is coupled, preferably connected, to the drain of transistor T5. The drain of transistor T5 is further connected to a current source 254 configured to generate a bias current sourced to transistor T5 from the supply node Vdd.
The transistors T3 and T5 of the circuits 270 and 272 are operating in source follower configuration.
Discharged capacitors are applied at each clock cycle on the REFP node (often close to the supply voltage). When REFP drops, the gate to source voltage (Vgs) of transistor T3 is reduced accordingly. The current flowing in the source-drain path of transistor T3 is then less than the current Iref (sunk by current source 252). Therefore, the gate voltage of transistor T4 rapidly decreases, resulting in a high current through this transistor, recharging the capacitors connected to the REFP node.
Charged capacitors are applied at each clock cycle to the REFN node (often close to ground). When the REFN suddenly increases, the Vgs voltage of transistor T5 is reduced accordingly. The current flowing in the source-drain path of transistor T5 is then less than the current Iref (sourced by current source 254). Therefore, the gate voltage of transistor T6 increases rapidly, resulting in a high current through this transistor, discharging the capacitors connected to the REFN node.
An advantage of using the circuits 270 and 272 in the output stage of the amplifier 217 is to lower the output impedance of the amplifier circuit 217. The use of flip voltage follower circuits 270 and 272 in the output stage is also superior to the use of a conventional MS transistor-based voltage follower circuit because the sourcing and sinking current at the output nodes is not limited by the current sources.
The bias control voltage VC applied at the connected base terminals of transistors Q11 and Q12 is output from a differential amplifier 280, for example comprising an operational amplifier (OP-AMP). A first input of the differential amplifier 280 receives a common mode reference voltage VCM. This voltage VCM may be generated by a suitable generator circuit at a voltage level half-way between Vdd and ground. A second input of the differential amplifier 280 receives a feedback voltage VFB generated by a resistive divider circuit 282 formed by a first feedback resistor RFBN and second feedback resistor RFBP connected in series with each other at a tap node. The first feedback resistor RFBN is coupled, preferably connected, between the inverting output of amplifier 217 (where the negative differential output reference voltage REFN is generated) and the tap node. The second feedback resistor RFBP is coupled, preferably connected, between the non-inverting output of amplifier 217 (where the positive differential output reference voltage REFP is generated) and the tap node. The bias control voltage VC is generated at a level which causes the output voltages Vout+ and Vout− as applied to the output stage flip voltage follower circuits 270, 272 to generate the differential output voltages REFP and REFN at levels where their median voltage equals the common mode voltage level.
The main drawback of using bipolar transistors for the differential pair 220 of input transistors Q5, Q6 in circuit 220 is their base current Ib. It will be noted that the mirrored current flowing through each of the transistors QA, QB, QC and QD has three components: the PTAT current Iptat across R1, the CTAT current Ictat across R2 (wherein IREF=Iptat+Ictat), and the base current Ib flowing into the bases of the pair of transistors 220. The base current Ib is unwanted and must be addressed by compensation. The effect of this base current Ib is compensated at the differential input of the amplifier 217 by sinking, at each input, a compensation current Ib′ from the applied input currents IREF+Ib and IREF-Ib, wherein the compensation current Ib′ corresponds to (i.e., is equal or substantially equal within the limits of circuit tolerances to) the base current Ib.
The third mirrored current output from the collector terminal of transistor QC is composed of the constant (across process, voltage and temperature (PVT)) current IREF and an undesired current Ib corresponding to the base current Ib of the differential input transistors Q5 and Q6. The current IREF+Ib is applied to (i.e., sourced to) the non-inverting (+) input of the fully differential amplifier 217 where the input transistor Q9 (matching transistor Q5) sinks a base current Ib′ for compensation. The current flowing through the first feedback resistor R3 (coupled, preferably connected, between the non-inverting input of the fully differential amplifier 217 and the inverting output of the fully differential amplifier 217) is the current IREF=(IREF+Ib)−Ib′, where Ib′ is equal or substantially equal to Ib.
Likewise, the fourth mirrored current output from the collector terminal of transistor QD is composed of the constant (across process, voltage and temperature (PVT)) current IREF and an undesired current Ib corresponding to the base current Ib of the differential input transistors Q5 and Q6. The current IREF+Ib is mirrored by the mirror 216 to generate the current IREF-Ib which is applied to (i.e., sunk from) the inverting (−) input of the fully differential amplifier 217 where the input transistor Q10 (matching transistor Q6) sinks a base current Ib′ for compensation. The current flowing through the second feedback resistor R3 (coupled, preferably connected, between the inverting input of the fully differential amplifier 217 and the non-inverting output of the fully differential amplifier 217) is the current IREF=(IREF−Ib)+Ib′, where Ib′ is equal or substantially equal to Ib. Note here that because mirror circuit 219 uses bipolar transistors QE and QF, a base current Ib is sunk by each transistor QE and QF so that the output current of the mirror is (IREF+Ib)−(2*Ib)=IREF-Ib. In this configuration, the bipolar transistors QE and QF of the mirror circuit 219 are designed to match differential input transistors Q5 and Q6 and differential input transistors Q9 and Q10.
Although
While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.
This application is a Continuation-In-Part (CIP) of U.S. patent application Ser. No. 18/373,520, filed Sep. 27, 2023, the disclosure of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18373520 | Sep 2023 | US |
| Child | 18897333 | US |
