BRIEF DESCRIPTION OF DRAWINGS
These and other objects, features and advantages of the present invention will become apparent to those skilled in the art upon consideration of the following description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a waveform diagram to show the output signals of a conventional voltage regulator in a load transient;
FIG. 2 is a waveform diagram to show the output signals of a conventional voltage regulator when an AVP control is applied thereof;
FIG. 3 shows a conventional current-mode voltage regulator;
FIG. 4 shows the current sense signal VCS and error signal COMP of a current-mode voltage regulator in a PWM on-time period when the error amplifier of the voltage regulator has a small gain;
FIG. 5 shows a low-gain current-mode voltage regulator according to the present invention;
FIG. 6 is a waveform diagram to show various signals in the voltage regulator of FIG. 5;
FIGS. 7-10 show four current sense circuits to sense the inductor current IL of a voltage regulator;
FIG. 11 shows a modification of the voltage regulator of FIG. 5.
DETAIL DESCRIPTION OF THE INVENTION
FIG. 5 shows an embodiment of the present invention, and FIG. 6 is a waveform diagram to show various signals thereof. In a low-gain current-mode voltage regulator 200, a high-side switching signal U and a low-side switching signal L switch a high-side transistor 216 and a low-side transistor 218 serially connected between an input voltage Vin and ground GND with two drivers 212 and 214, respectively, to produce an inductor current IL to charge an output capacitor C to produce an output voltage Vout, an error amplifier 202 has a gain Av to amplify the difference between the output voltage Vout and a reference voltage Vref to produce an error signal COMP, a voltage amplifier 208 has a gain Ai to amplify the voltage drop across a current sense resistor Rs serially connected to the inductor L to produce a current sense signal VCS, a combiner 220 combines the error signal COMP and an offset signal LO provided by an offset cancellation circuit 204 to produce a modified error signal
COMP′=COMP+LO [EQ-4]
a PWM comparator 206 produces a PWM signal by comparing the current sense signal VCS and modified error signal COMP′, and an SR flip-flop 210 produces the switching signals U and L in response to the PWM signal and a clock CLK. By illustrating by FIG. 4 and the equation EQ-2, the offset Voffset of the output voltage Vout is equal to 1/Av times of the difference between the DC levels of the current sense signal VCS and error signal COMP. Therefore, the offset cancellation circuit 204 injects the offset signal LO into the error signal COMP to cancel the offset caused by the ripple effect of the current sense signal VCS and error signal COMP. The offset cancellation circuit 204 uses a combiner 224 to obtain the subtraction in the inputs of the PWM comparator 206, i.e., LI=COMP′-VCS. The subtraction signal LI indicates the offset source of the voltage regulator 200. However, the subtraction signal LI includes ripple item, and thus a low-pass filter 222 is used to filter out the ripple of the subtraction signal LI to obtain the DC level thereof, i.e., the offset signal LO. Namely, the low-pass filter 222 averages the subtraction of the modified error signal COMP′ and current sense signal VCS to remove the AC signal component thereof.
In FIG. 6, waveform 226 represents the modified error signal COMP′, waveform 228 represents the current sense signal VCS, waveform 230 represents the error signal COMP, waveform 232 represents the clock CLK, waveform 234 represents the high-side switching signal U, waveform 236 represents the subtraction signal LI, and waveform 238 represents the offset signal LO. As shown in FIG. 6, the offset signal LO is almost a DC signal, and by injecting it into the error signal COMP, the DC levels of the error signal COMP and current sense signal VCS are equal to each other. In response to the modified error signal COMP′ and current sense signal VCS, only when the modified error signal COMP′ is crossing with the current sense signal VCS, the PWM comparator 206 will send low level signal to the SR flip-flop 210 to turn off the high-side transistor 216. Offset still occurs in the inputs of the PWM comparator 206, but the injection of the offset signal LO into the error signal COMP cancels the output offset of the voltage regulator 200. That is, precise output voltage Vout is obtained.
From another point of view, if LPF is the transfer function of the low-pass filter 222, the error amplifier 202 and offset cancellation circuit 204 can be considered as a modified error amplifier having the gain
Av′=Av+Av′×LPF [EQ-5]
The transfer function of the low-pass filter 222 is
where ωp is the corner frequency of the low-pass filter 222, and s is the frequency of the subtraction signal LI. Substituting the equation EQ-6 into the equation EQ-5 will obtain the gain
When the pole is the original point, i.e., s=0, it will obtain an infinite DC gain, and thus the low-gain current-mode voltage regulator 200 may be referred as a high gain system at DC level. As a result, it can be obtained the precise output voltage Vout.
In the voltage regulator 200, the offset signal LO is injected into the error signal COMP, while in other embodiments, it may be alternatively injected into the current sense signal VCS at opposite polarity, since in the PWM comparator 206 the inverting input and non-inverting input thereof will be compared with each other.
To sense the inductor current IL, the current sense resistor Rs may be the parasitic resistor in the inductor L, or an additional one inserted in the system. In the above embodiment, the current sense signal VCS is produced by the voltage amplifier 208 by sensing the voltage drop across the current sense resistor Rs serially connected to the inductor L, while in other embodiments, various alternative schemes can be used instead. FIGS. 7-10 show some typical current sense circuits, which sense either the ramp-up or ramp-down portion of the inductor current IL, and the combination properly selected therefrom or the combination of either one of them with any other not shown hereof may be used to sense the inductor current IL. In FIG. 7, the current sense resistor Rs is connected between the input voltage Vin and high-side switch 216 for the voltage amplifier 208 to sense the voltage drop thereacross to produce the current sense signal VCS. In FIG. 8, the voltage amplifier 208 directly senses the voltage drop across the high-side switch 216 to produce the current sense signal VCS. In FIG. 9, the current sense resistor Rs is connected between the low-side switch 218 and ground GND for the voltage amplifier 208 to sense the voltage drop thereacross to produce the current sense signal VCS. In FIG. 10, the voltage amplifier 208 directly senses the voltage drop across the low-side switch 218 to produce the current sense signal VCS.
To enhance the stability of the voltage regulator 200, it usually introduces a slope compensation mechanism as shown in FIG. 11, in which a slope compensation signal SC is provided to the non-inverting input of the PWM comparator 206 to combine with the current sense signal VCS. While in other embodiments, the slope compensation signal SC may be alternatively provided to the inverting input of the PWM comparator 206 to combine with the modified error signal COMP′.
As illustrated by the above embodiments, the present invention provides a simple, precise and global control to improve the offset issue in a low-gain current-mode voltage regulator.
While the present invention has been described in conjunction with preferred embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and scope thereof as set forth in the appended claims.
Patent Application
20080024100
