Patent Application
20120182001
1. Field of the Invention
The present invention relates to a boost-type power converter and a controller thereof, and more particularly to a low input voltage boost-type power converter operable at low temperatures and a boost controller thereof.
2. Description of the Related Art
Please refer to
The boost converter 100, including a boost controller 110 and an NMOS transistor 120, is a three-pin integrated chip, of which the package is compatible with that of a MOSFET—popular and available, for minimizing the package size and packaging cost. The boost controller 110 therefore has to be powered by a DC supply voltage derived from VX—the voltage at the anode of the Shottky diode 140, or from an output voltage VO—the voltage across the resistor 160, wherein, if the DC supply voltage is powered by VX, which has a repeated voltage notch caused by the switching of the NMOS transistor 120, a rectification circuit including a diode is needed in the boost controller 110 to build up the DC supply voltage. When in operation, the boost controller 110 will send a switching signal VSW, of which the amplitude is determined by the DC supply voltage, to switch the NMOS transistor 120 to repeatedly transfer an energy from an input voltage YIN at a lower level to the output voltage VO at a higher level, by repeatedly storing the energy into the inductor 130 and then releasing it through the Shottky diode 140 to the capacitor 150 and the resistor 160. The process of storing the energy into the inductor 130 is illustrated in
However, when the input voltage YIN is a low voltage source, for example a 0.9V voltage source, and the environmental temperature is at low temperatures, for example below −20° C., the prior art boost converter circuit may fail to function. The reasons are elaborated as follows:
1. The threshold voltage of the NMOS transistor 120 has a negative temperature coefficient of around −2 mV/° C. Therefore, if the threshold voltage is 0.6V at 25° C., then it will become 0.69V when the environmental temperature is at −20° C.
2. If the input voltage YIN is at 0.9V, the environmental temperature is at −20° C., and the DC supply voltage of the boost controller 110 is derived by a half-wave rectification of VX to be equal to (VX—the forward voltage drop of a rectification diode), then the high level of the switching signal VSW (around 0.9V-0.7V=0.2V) will be much lower than the threshold voltage of the NMOS transistor 120 (0.69V as mentioned above), causing failure of the switching of the NMOS transistor 120, and thereby failure of the boost converter circuit.
3. On the other hand, if the DC supply voltage of the boost controller 110 is derived from the output voltage VO with the input voltage VIN being at 0.9V and the environmental temperature at −20° C., then the output voltage VO will be at about 0.685V—equal to (the input voltage VIN—the voltage drop of the inductor 130—the voltage drop of the Shottky diode 140) during the startup period, and the high level of the switching signal VSW will be lower than the threshold voltage of the NMOS transistor 120 (0.69V as mentioned above), causing failure of the switching of the NMOS transistor 120, and thereby failure of the boost converter circuit.
To tackle the issues mentioned above, adopting a process having a lower threshold voltage seems to be a solution. However, a lower threshold voltage means a larger leakage current, and a larger leakage current can deteriorate the performance of power saving of the boost converter, especially when the boost converter is in standby mode.
In view of these problems, the present invention proposes a boost converter utilizing a novel boost controller, to overcome the effects of low input voltage and low environmental temperatures.
One objective of the present invention is to propose a low input voltage boost converter operable at low temperatures.
Another objective of the present invention is to propose a boost controller for a low input voltage boost converter circuit operable at low temperatures.
To achieve the foregoing objectives of the present invention, a low input voltage boost converter operable at low temperatures is proposed, the boost converter including a boost controller and an NMOS transistor, wherein the boost controller has a first input end coupled to the anode of a Shottky diode, a second input end coupled to an output voltage, a switching signal output end for providing a switching signal, and a common end for connecting to a ground; and the boost controller includes a driver unit, a first inverter circuit, a second inverter circuit, and a comparator circuit.
The driver unit, powered by the output voltage, is used to generate a first switching signal.
The first inverter circuit, powered by the voltage at the anode of the Shottky diode, has an input end coupled to the first switching signal, a control end coupled to a control signal, and an output end coupled to the switching signal output end, wherein the first inverter circuit is active when the control signal is inactive, and disabled when the control signal is active.
The second inverter circuit, powered by the output voltage, has an input end coupled to the first switching signal, and an output end coupled to the switching signal output end.
The comparator circuit is used to generate the control signal by comparing the output voltage with a reference voltage.
The NMOS transistor has a gate terminal coupled to the switching signal output end, a drain terminal coupled to the anode of the Shottky diode, and a source terminal coupled to the ground.
To make it easier for our examiner to understand the objective of the invention, its structure, innovative features, and performance, we use preferred embodiments together with the accompanying drawings for the detailed description of the invention.
a illustrates the circuit diagram of a prior art boost converter circuit.
b illustrates the process of storing the energy into the inductor.
c illustrates the process of releasing the energy from the inductor to the capacitor and the resistor.
The present invention will be described in more detail hereinafter with reference to the accompanying drawings that show the preferred embodiment of the invention.
Please refer to
The boost converter 200 including a boost controller 210 and an NMOS transistor 220, wherein the boost controller 210 has a first input end coupled to the anode of the Shottky diode 240, a second input end coupled to an output voltage VO, a switching signal output end for providing a switching signal VSW, and a common end for connecting to a ground VSS; and the boost controller 210 includes a driver unit 211, a first inverter circuit 212, a second inverter circuit 213, and a comparator circuit 214.
The driver unit 211, powered by the output voltage VO, is used to generate a first switching signal VSW1, of which the duty is determined by an error signal derived from the difference of the output voltage VO and a first reference voltage.
The first inverter circuit 212, powered by VX—the voltage at the anode of the Shottky diode 240, has an input end coupled to the first switching signal VSW1, a control end coupled to a control signal SOFF, and an output end coupled to the switching signal output end, wherein the first inverter circuit 212 is active if the control signal SOFF is inactive, and disabled if the control signal SOFF is active.
The second inverter circuit 213, powered by the output voltage VO, has an input end coupled to the first switching signal VSW1, and an output end coupled to the switching signal output end.
The comparator circuit 214 is used to generate the control signal SOFF by comparing the output voltage VO with a second reference voltage.
The NMOS transistor 220 has a gate terminal coupled to the switching signal output end, a drain terminal coupled to the anode of the Shottky diode 240, and a source terminal coupled to the ground.
During a startup period, the high level of the switching signal VSW will be enhanced by the first inverter circuit 212 due to the fact that VX is higher than the output voltage VO. With the NMOS transistor 220 being effectively turned on, the output voltage VO will build up cycle by cycle. When VO reaches the second reference voltage, the control signal SOFF will be active to disable the first inverter circuit 212, and the switching signal VSW will then be solely provided by the second inverter circuit 213.
In a scenario of having an input voltage VIN at 0.9V, and the environmental temperature at −20° C., the high level of the switching signal VSW enhanced by the first inverter circuit 212 during a startup period will still be high enough for turning on the NMOS transistor 220—the threshold voltage of the NMOS transistor 220 is 0.69V, while VX is around 0.9V. The waveform diagram of major signals VO, VSW, VX, ID, and IL of the boost converter circuit in
According to the principles mentioned above, the present invention proposes a preferred embodiment of the boost controller 210 as illustrated in
The driver unit 211, powered by VO, is used to generate a first switching signal VSW1, of which the duty is determined by an error signal derived from the difference of VO and a first reference voltage.
The first inverter circuit 212 includes a PMOS transistor 2121 and a PMOS transistor 2122, wherein the PMOS transistor 2121 has a source terminal coupled to VX, a gate terminal coupled to a control signal SOFF, and a drain terminal coupled to a source terminal of the PMOS transistor 2122; while the PMOS transistor 2122 has a gate terminal coupled to the first switching signal VSW1, and a drain terminal coupled to the switching signal output end. When the control signal SOFF is inactive (at a low level), the PMOS transistor 2121 will be turned on, and the PMOS transistor 2122 will act as an inverter. When the control signal SOFF is active (at a high level), the PMOS transistor 2121 will be turned off, and the inverter function of the PMOS transistor 2122 will be disabled.
The second inverter circuit 213 includes a PMOS transistor 2131 and an NMOS transistor 2132, wherein the PMOS transistor 2131 has a source terminal coupled to VO, a gate terminal coupled to the first switching signal VSW1, and a drain terminal coupled to a drain terminal of the NMOS transistor 2132; while the NMOS transistor 2132 has the drain terminal coupled to the switching signal output end, a gate terminal coupled to the first switching signal VSW1, and a source terminal coupled to the ground. When SOFF is inactive (at a low level) and VSW1 is at a low level, VSW will exhibit a high level, which is a superposition of VX and VO, higher than VO but lower than VX. When SOFF is active (at a high level) and VSW1 is at a low level, VSW will exhibit a high level, which is solely supplied by VO.
The comparator circuit 214 includes a reference voltage generator 2141, a voltage divider 2142, and a comparator 2143, wherein the reference voltage generator 2141, powered by VO, is used to generate a reference voltage VREF; the voltage divider 2142 is used to generate VOD—a divided voltage of VO; and the comparator 2143 is used to generate the control signal SOFF by comparing VOD with VREF, wherein SOFF is at a low level when VOD is lower than VREF, and turns to be at a high level when VOD is higher than VREF.
According to the principles mentioned above, the boost controller 210 of the present invention can have other embodiments. Please refer to
As the operation principles of the driver unit 211, the second inverter circuit 213, and the comparator circuit 214 are elaborated above, they will not be readdressed here.
The first inverter circuit 212 includes a NOR gate 2123, an inverter 2124, and a PMOS transistor 2125, wherein the NOR gate 2123, powered by VO, has a first input end coupled to SOFF, a second input end coupled to VSW1, and an output end coupled to the inverter 2124; the inverter 2124, powered by VO, has an input end coupled to the output end of the NOR gate 2123, and an output end coupled to the PMOS transistor 2125; the PMOS transistor 2125 has a source terminal coupled to VX, a gate terminal coupled to the output end of the inverter 2124, and a drain terminal coupled to the switching signal output end for enhancing the high level of VSW.
When the control signal SOFF is inactive (at a low level), the NOR gate 2123 will function as an inverter, and the combination of the NOR gate 2123, the inverter 2124, and the PMOS transistor 2125 will serve as an inverter. When the control signal SOFF is active (at a high level), the output end of the NOR gate 2123 will exhibit a low level, the output end of the inverter 2124 will exhibit a high level, the PMOS transistor 2125 will be turned off, and the switching signal VSW will be solely provided by the second inverter circuit 213.
As can be seen from the specification above, by using the boost controller of the present invention capable of enhancing the high level of the switching signal during a startup period, a boost converter circuit can operate at low environmental temperatures to boost a low input voltage to a higher output voltage, so the present invention does improve the prior art boost converters and boost controllers and is worthy of being granted a patent.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.
In summation of the above description, the present invention herein enhances the performance than the conventional structure and further complies with the patent application requirements and is submitted to the Patent and Trademark Office for review and granting of the commensurate patent rights.
