Low-jitter phase-locked loop

Abstract

A phase-locked loop (PLL) with a decreased frequency tuning gain KVCO and a loop filter using capacitor multiplication technique to get high chip area efficiency. To get decreased frequency tuning gain, KVCO, a voltage to current converter in a voltage-controlled oscillator (VCO) in the PLL may comprise a first voltage to current converter and a second voltage to current converter. The trans-conductance of the first voltage to current converter is 1/β of that of the second voltage to current converter, wherein β>1. The first voltage to current converter is controlled by an output voltage of a loop filter in the PLL, and the second voltage to current converter is controlled by a relative DC voltage, which may be the junction node between R1 and C1 in a loop filer of the PLL. Capacitor multiplication technique may use an auxiliary charge pump to charge or discharge the junction node between R1 and C1 inversely to the main charge pump. When the charge or discharge current unit of the auxiliary charge pump is α times of the main charge pump, the capacitance of C1 may be reduced to just (1−α) times of what it needed in a conventional loop stability compensation method, wherein α<1.

Description

BACKGROUND

1. Field of the Invention

The present invention relates generally to phase-locked loops (PLLs).

2. Description of Related Art

Phase-locked loops are widely used in electronic devices, such as computers, telecommunications equipment and radio. However, known PLLs have been insufficiently noise insensitive.

FIG. 1 illustrates a known PLL 100, which is used to maintain an output frequency ω_out to be a multiple times of a reference frequency ω_ref. The PLL 100 has a phase and frequency detector (PFD) 101, a charge pump 102, a loop filter 103, a voltage-controlled oscillator (VCO) 104 and a divider 105. The VCO 104 has a voltage supply 1041 which as shown may be, e.g., a high power supply rejection (PSR) regulator, a voltage to current converter 1042 and a current-controlled oscillator (ICO) 1043. The ICO 1043 may be, e.g., a ring based oscillator. The voltage to current converter 1042, having a voltage to current converting rate gm=I_C/V_ctrl, may generate a control current I_C in proportion with a control voltage V_ctrl from the loop filter 103. The ICO 1043, having a frequency tuning gain K_ICO=ω_out/I_c, may output a frequency ω_out based on the control current I_C. The divider 105 is on the feedback route from the output of the ICO 1043 to the input of the PFD 101, and may divide the output frequency ω_out by an integer N and send a feedback frequency, ω_fb=ω_out/N, to the input of the PFD 101.

The PFD 101 may compare the feedback frequency ω_fb with the reference frequency ω_ref. When ω_fb is lower than the reference frequency ω_ref, the PFD 101 may output switching signals PU and PD to the charge pump 102, closing a switch 1021 and keeping a switch 1022 open, so as to charge a charge storage device C1 in the loop filter 103. Consequently, the control voltage V_ctrl at the output of the loop filter 103 is up, the control current I_C supplied to the ICO 1043 is up, and the output frequency ω_out is up until it equals N ω_ref.

When ω is higher than the reference frequency ω_ref, the PFD 101 may generate switching signals PU and PD to open the switch 1021 and close the switch 1022, so that the charge storage device C1 in the loop filter 103 may discharge via the switch 1022. Consequently, the control voltage V_ctrl at the output of the loop filter 103 is down, the control current I_C is down, and the output frequency ω_out is down, until ω_out=N ω_ref.

When ω_fb equals ω_ref, the PFD 101 may keep both switches 1021 and 1022 closed to maintain the relationship.

The pole position and zero position of the PLL 100 are:

$\begin{array}{cc}{\omega }_z=\frac{1}{R_1{C}_1}& \left(1\right)\\ {\omega }_p=\frac{1}{R_1{C}_2}\left(1+\frac{C_2}{C_1}\right)\approx \frac{1}{R_1{C}_2}& \left(2\right)\end{array}$

So the ratio between the pole and zero position is:

$\begin{array}{cc}\frac{{\omega }_p}{{\omega }_z}=\frac{C_1+C_2}{C_2}& \left(3\right)\end{array}$

The gain bandwidth of the PLL 100 is:

$\begin{array}{cc}{\omega }_c\approx \frac{I_{\mathrm{cp}}}{2*\pi }*R_1*g_m*K_{\mathrm{ICO}}*\frac{1}{N}& \left(4\right)\end{array}$

For the PLL 100, the output phase noise at the output frequency ω_out contributed by R1 is:

$\begin{array}{cc}{\varphi }_n^2=4*K*T*R_1*{\left(g_m*\frac{K_{\mathrm{ICO}}}{s}\right)}^2& \left(5\right)\end{array}$

wherein K is the Boltzmann constant, T is a temperature value, and s=jω, which is a variable in frequency domain.

One limitation of the known PLL 100 is its high frequency tuning gain (K_VCO), which is the frequency/voltage gain of the VCO. The high frequency tuning gain, together with a wide loop bandwidth used to suppress phase noise, may make the PLL more sensitive to the noise from the PFD, the charge pump and the loop filter. Therefore, it may be desirable to provide a PLL which may have a decreased frequency tuning gain K_VCO and the wide loop bandwidth.

Another limitation of the known PLL 100 is that the loop filter 103 may occupy a large chip area when being integrated on a chip. One known solution uses an active loop filter, but the active device may bring additional noise. Another known solution uses a passive feed forward loop filter with noiseless resistor multiplication, but it may increase sensitivity to switching glitches of the charge pump. Therefore, it may be desirable to provide a PLL with a loop filter which has high chip area efficiency but low noise and switching glitch sensitivity.

SUMMARY

A voltage-controlled oscillator (VCO), comprising: a voltage supply; a voltage to current converter for converting a voltage signal from the voltage supply into a control current, the voltage to current converter comprising a first voltage to current converter and a second voltage to current converter coupled in parallel to produce the control current; and a current-controlled oscillator (ICO), generating an output frequency in response to the control current.

A phase-locked loop (PLL), comprising: a phase and frequency detector (PFD) for comparing a feedback frequency and a reference frequency and generating a first switching signal and a second switching signal; a first charge pump, comprising a first current source coupled in series with a first switch, a second switch and a second current source, wherein the first switch is controlled by the first switching signal, the second switch is controlled by the second switching signal and the first current source provides a current I_CP; a loop filter, comprising a first branch and a second branch coupled in parallel, wherein the first branch comprises a resistance device coupled in series with a first charge storage device, and the second branch comprises a second charge storage device; and a voltage controlled oscillator (VCO) providing an output frequency, wherein the output frequency is sent to the PFD as the feedback frequency. The VCO comprise: a voltage supply; a voltage to current converter for converting a voltage signal from the voltage supply into a control current, the voltage to current converter comprising a first voltage to current converter and a second voltage to current converter coupled in parallel to produce the control current; and a current-controlled oscillator (ICO), generating the output frequency in response to the control current.

A capacitor multiplication structure may be used in the PLL to increase the capacitance of the first charge storage device without increasing its size. The PLL may further comprise a second charge pump coupled in parallel with the first charge pump, wherein the second charge pump comprises a third current source, a third switch, a fourth switch and a fourth current source coupled in series, to charge or discharge the junction of the resistance device and the first charge storage device. The third current source provides a current α*I_CP to decrease voltage variations over the first charge storage device, and wherein α<1. The third switch is turned on and off approximately simultaneously with the first switch, but in the opposite direction. The fourth switch is turned on and off approximately simultaneously with the second switch, but in the opposite direction.

A method for controlling a voltage-controlled oscillator (VCO), comprising: converting a voltage signal into a first control current with a first voltage to current converter; converting a voltage signal from the voltage supply into a second control current with a second voltage to current converter; combining the first control current and the second control current into a control current; and generating an output frequency in response to the control current with a current-controlled oscillator (ICO).

BRIEF DESCRIPTION OF THE DRAWING FIGURES

Embodiments are described herein with reference to the accompanying drawings, similar reference numbers being used to indicate functionally similar elements.

FIG. 1 illustrates a known PLL.

FIG. 2 is a circuit schematic depicting a VCO with a low frequency tuning gain according to one embodiment.

FIG. 3 is a circuit schematic depicting a PLL having a VCO with a low frequency tuning gain according to one embodiment.

FIG. 4 illustrates an exemplary circuit implementation of the PLL in FIG. 3.

FIG. 5 illustrates an example of the PSR performance (power supply noise rejection from V_DD—VCO to V_C) of the PLL in FIG. 4.

FIG. 6 illustrates an exemplary circuit implementation of the PLL in FIG. 3.

FIG. 7 illustrates an exemplary circuit implementation of the PLL in FIG. 3.

FIG. 8 illustrates a transient simulation result for control voltages V_ctrl—A and V_ctrl—B in FIG. 3 when the PLL 300 is acquiring lock.

FIGS. 9A, 9B, 9C and 9D illustrate exemplary relationships between K_VCO′ and V_ctrl—B in the PLL of FIG. 3.

FIG. 10 is a circuit schematic depicting a PLL with the VCO in FIG. 2 and a passive loop filter with capacitor multiplication according to one embodiment.

DETAILED DESCRIPTION

The following discussion describes a PLL with an oscillator structure having a low frequency tuning gain K_VCO and a passive loop filter structure with noiseless capacitor multiplication.

FIG. 2 is a circuit schematic depicting a VCO with a low frequency tuning gain according to one embodiment.

A VCO 204 may include a voltage supply such as a high PSR regulator 2041, a voltage to current converter 2042 and an ICO 2043. The voltage to current converter 2042 may include two voltage to current converters, 2042A and 2042B, coupled in parallel between the voltage supply 2041 and the ICO 2043. The converter 2042A may be controlled by a control voltage V_ctrl—A from a voltage source A, which may be, e.g., the output of a loop filter in a PLL. The converter 2042B may be controlled by a control voltage V_ctrl—B from a voltage source B, which may be, e.g., a relative DC voltage. The converter 2042A may have a voltage to current converting rate, or trans-conductance, g_m—A, and generate a control current I_A based on the control voltage V_ctrl—A. The converter 2042B may have a trans-conductance g_m—B, and generate a control current I_B based on the control voltage V_ctrl—B. Control currents I_A and I_B may be added at C and a combined control current I_C may be provided to the ICO 2043.

In one embodiment, g_m—A:g_m—B=1: β, and β>1. Thus, in the voltage to current converter 2042:g_m=g_m—A+g_m—B=g_m—A(1+β)=g_m—B(1/β+1);   (6)g_m—A=g_m/(1+β);   (7)g_m—B=β*g_m/(β+1);   (8)

According to equation (7), when β is considerably greater than 1, the trans-conductance g_m—A of the converter 2042A may be only a small part of the trans-conductance g_m of the voltage to current converter 2042.

When V_ctrl—B is stable, I_B may be stable, and l_C may only change with V_ctrl—A. In a small signal model, the equivalent resistor of the ICO 2043 may be much larger than 1/g_m—A, andV_C=V_ctrl—A(g_m—A/(g_m—A+g_m—B)=V_ctrl—A/(1+β)   (9)

Assuming that K_VCO′ is the tuning gain from V_ctrl—A to the output frequency, and K_VCO is the tuning gain from V_c to the output frequency, then:

$\begin{array}{cc}\begin{array}{c}{K}_{\mathrm{VCO}}^{\prime }={\omega }_{\mathrm{out}}/V_{\mathrm{ctrl\_A}}\\ ={\omega }_{\mathrm{out}}/\left(V_c*\left(1+\beta \right)\right)\\ =K_{\mathrm{VCO}}/\left(1+\beta \right)\end{array}& \left(10\right)\end{array}$

When the trans-conductance of the VCO 204 is similar to the trans-conductance of the VCO 104 in the known PLL 100, by using two converters 2042A and 2042B and controlling the converter 2042B, whose trans-conductance is β times the trans-conductance of 2042A, with the control voltage V_ctrl—B which is relatively stable and is separated from the control voltage V_ctrl—A for the converter 2042A, the tuning gain of the VCO 204 may be reduced to about 1/(1+β) of the tuning gain of the VCO 104 in the known PLL 100. When β=4, for example, the tuning gain of the VCO 204 may be only about ⅕ of that of the VCO 104. By adjusting the value of β, the tuning gain of the VCO 204 may be further decreased. The decrease may only need minimal circuit changes, but may make the VCO 204 significantly less sensitive to the noise from other parts in a PLL.

FIG. 3 is a circuit schematic depicting a PLL with the VCO in FIG. 2 according to one embodiment. A PLL 300 may have a PFD 301, a charge pump 302, a loop filter 303, and a VCO 304 (corresponding to the VCO 204 in FIG. 2).

The charge pump 302 may have a current source 3021, switches 3022 and 3023, and a current source 3024 coupled in series between a fixed voltage AVDD and a fixed voltage P. Switches 3022 and 3023 may be turned on and off by switching signals PU and PD from the PFD 301 respectively, and may be, e.g., transistors. The current sources 3021 and 3024 may provide a current I_CP.

In the loop filter 303, a charge storage device C1 and a resistance device R1 may be coupled in series between the output of the charge pump 302 and the fixed voltage P, and a charge storage device C2 may be coupled between the output of the charge pump 302 and the fixed voltage P as well, in parallel with the circuit branch including the charge storage device C1 and the resistance device R1. The charge storage devices C1 and C2 may be, e.g., capacitors, and the resistance device R1 may be, e.g., a resistor. A voltage to current converter 3042A may take its control voltage V_ctrl—A from the junction of R1 and C2, and a voltage to current converter 3042B may take its control voltage V_ctrl—B from the junction of R1 and C1.

The current source 3021 may charge the charge storage device C1 via the switch 3022 and the resistance device R1 to raise the control voltages V_ctrl—A and V_ctrl—B when the switch 3022 is closed and the switch 3023 is open. Or the charge storage device C1 may discharge via the resistance device R1 and the switch 3023 to lower the control voltages V_ctrl—A and V_ctrl—B when the switch 3022 is open and the switch 3023 is closed.

As discussed above with reference to FIG. 2, the tuning gain of the VCO 304 may be about 1/(1+β) of that of the known VCO 104. The decrease in tuning gain may make the PLL 300 less sensitive to switching glitches from the charge pump 302, and the noise from the PFD 301, the charge pump 302, and the loop filter 303.

FIGS. 4, 6 and 7 illustrate exemplary circuit implementations of the PLL in FIG. 3.

In the circuit shown in FIG. 4, N-type field effect transistors (FETs) MNA and MNB may be used as the voltage to current converters 3042A and 3042B in FIG. 3, and the fixed voltage P may be ground. The trans-conductance of MNA is g_m—A, the trans-conductance of MNB is g_m—B, andg_m—A:g_m—B=1:β, and β>1

In particular, the gate of MNA may receive the control voltage V_ctrl—A, and the gate of MNB may receive the control voltage V_ctrl—B. The drains of MNA and MNB may be coupled to a voltage supply such as a high PSR regulator 4041, and the sources of MNA and MNB may be coupled to an ICO 4043. The control voltage V_ctrl—A may control the current I_A flowing through MNA, and the control voltage V_ctrl—B may control the current I_B flowing through MNB. A control current l_C, which is the sum of I_A and I_B, may control the ICO 4043. In one embodiment, MNA and MNB may be native devices, and an output noise of about −25 dB PSR from V_DD—VCO at the output of the voltage supply to V_C at the input of the ICO 4043 may be achieved, as shown in FIG. 5.

In the circuit shown in FIG. 6, P-type FETs MPA and MPB may be used as the voltage to current converters 3042A and 3042B in FIG. 3, and the fixed voltage P may be V_DD—VCO at the output of a voltage supply such as a high PSR regulator 6041. The trans-conductance of MPA is g_m—A, the trans-conductance of MPB is g_m—B, andg_m—A:g_m—B=1:β, and β>1

In particular, the gate of MPA may receive the control voltage V_ctrl—A from the junction of C2 and R1, and the gate of MPB may receive the control voltage V_ctrl—B from the junction of C1 and R1. The source of MPA may be coupled to the voltage supply 6041 via a resistor R_a, and the source of MPB may be coupled to the voltage supply 6041 via a resistor R_b. In one embodiment, R_b=R_a/β. The drains of MPA and MPB may be coupled to an ICO 6043. Thus, the control voltage V_ctrl—A may control the current I_A flowing through MPA, and the control voltage V_ctrl—B may control the current I_B flowing through MPB. A control current I_C, which is the sum of I_A and I_B, may control the ICO 6043.

In the circuit of FIG. 7, N-type FETs MNA and MNB may be used as the voltage to current converters 3042A and 3042B in FIG. 3, and the fixed voltage P may be the ground. The trans-conductance of MNA is g_m—A, the trans-conductance of MNB is g_m—B, and

$g_{\mathrm{m\_A}}:g_{\mathrm{m\_B}}=\frac{g_m}{\beta +1}\text{:}\frac{g_m*\beta }{\beta +1}$ $\beta >1$

In particular, the gate of MNA may receive the control voltage V_ctrl—A, and the gate of MNB may receive the control voltage V_ctrl—B. The source of MNA may be grounded via a resistor R_a, and the source of MNB may be grounded via a resistor R_b. In one embodiment, R_b=R_a/β. The drains of MNA and MNB may be coupled to a voltage supply such as a high PSR regulator 7041 via a current mirror 7044.

The current mirror 7044 may have P-type FETs MPP1 and MPP2. The junction of the gates of MPP1 and MPP2 and the drain of MPP1 may be coupled to the junction of the drains of MNA and MNB. The source of MPP1 may be coupled to the voltage supply 7041 via a resistor R_c, and the source of MPP2 may be coupled to the voltage supply 7041 via a resistor R_d. In one embodiment, R_d=R_c/m. The drain of MPP2 may be coupled to an ICO 7043.

The control voltage V_ctrl—A may control the current I_A flowing through MNA, and the control voltage V_ctrl—B may control the current I_B flowing through MNB. The reference current of the current mirror 7044 is I_C, which is the sum of I_A and I_B. The output current I_C′ of the current mirror 7044 may be provided to the ICO 7043 as its control current, wherein I_C′=I_C*m=(I_A+I_B)*m.

FIG. 8 illustrates a transient simulation result for V_ctrl—A and V_ctrl—B in FIG. 3 when the PLL 300 is acquiring a lock. As shown, instead of a DC voltage in FIG. 2, the control voltage V_ctrl—B in the PLL 300 in FIG. 3 may change with the control voltage V_ctrl—A slowly, and it may take a few microseconds for V_ctrl—B to catch up with the control voltage V_ctrl—A. Taking the variation of V_ctrl—B into consideration, the frequency tuning gain of the PLL shown in FIG. 3 may be:

$\begin{array}{cc}{K}_{{\mathrm{VCO}}^{\prime }}=\underset{\Delta V\to 0}{\lim }\frac{f\left(V_{\mathrm{ctrl\_A}}=V_{\mathrm{ctrl\_B}}+\Delta V\right)-f\left(V_{\mathrm{ctrl\_A}}=V_{\mathrm{ctrl\_B}}-\Delta V\right)}{2\Delta V}& \left(11\right)\end{array}$

FIGS. 9A, 9B, 9C and 9D illustrate exemplary relationships between K_VCO′ and the difference between V_ctrl—A and V_ctrl—B, V_ctrl—A−V_ctrl—B, in the PLL 300 of FIG. 3. As shown, if V_ctrl—B is set to a absolutely DC value and the output frequency is scanned by increasing V_ctrl—A only, K_VCO′ may vary significantly with (V_ctrl—A−V_ctrl—B), changing from 220 MHz/V to 450 MHz/V. This may make the bandwidth of the PLL loop vary and deteriorate the loop stability. However, it is found that, when V_ctrl—A−V_ctrl—B=0, Kvco′ almost does not vary with the absolute value of V_ctrl—B. Thus, in one embodiment, V_ctrl—B may be biased with a relative DC voltage, which may follow V_ctrl—A in a long period of time. One way to implement this is shown in FIG. 3, in which V_ctrl—B is taken from the junction of R1 and C1. Since C1>>C2, the difference between V_ctrl—A, and V_ctrl—B may be a DC bias point. Furthermore, since V_ctrl—B is connected to V_ctrl—A via R1, V_ctrl—B may follow V_ctrl—A at last.

Some properties of the PLL 300 are as follows:

$\begin{array}{cc}{V}_{\mathrm{ctrl\_B}}=I_{\mathrm{CP}}*\left(\frac{1}{{\mathrm{sC}}_2}//\left(R_1+\frac{1}{{\mathrm{sC}}_1}\right)\right)& \left(12\right)\end{array}$

wherein “∥” is a functor which means:

$A//B=\frac{A*B}{A+B}.$

$\begin{array}{cc}{V}_{\mathrm{ctrl\_B}}=I_{\mathrm{CP}}*\left(\frac{1}{{\mathrm{sC}}_2}//\left(R_1+\frac{1}{{\mathrm{sC}}_1}\right)\right)\frac{\frac{1}{{\mathrm{sC}}_1}}{R_1+\frac{1}{{\mathrm{sC}}_1}}& \left(13\right)\end{array}$

When I_A=V_ctrl—A*g_m—A, I_B=V_ctrl—B*g_m—B, and

$g_{\mathrm{m\_A}}=\frac{g_m}{\beta +1},g_{\mathrm{m\_B}}=\frac{g_m*\beta }{\beta +1}\text{:}$

$\begin{array}{cc}\begin{array}{c}{I}_C=I_A+I_B=V_{\mathrm{ctrol\_A}}*g_{\mathrm{m\_A}}+V_{\mathrm{ctrl\_B}}*g_{\mathrm{m\_B}}\\ =I_{\mathrm{CP}}*\left(\frac{1}{{\mathrm{sC}}_2}//\left(R_1+\frac{1}{{\mathrm{sC}}_1}\right)\right)*\\ \left(\frac{1}{\beta +1}+\frac{\beta }{\beta +1}*\frac{\frac{1}{{\mathrm{sC}}_1}}{R_1+\frac{1}{{\mathrm{sC}}_1}}\right)*g_m\end{array}& \left(14\right)\end{array}$

So the open loop transfer function may be:

$\begin{array}{cc}{H}_0\left(s\right)=\frac{I_{\mathrm{CP}}}{2*\pi }*\left(\frac{1}{{\mathrm{sC}}_2}//\left(R_1+\frac{1}{{\mathrm{sC}}_1}\right)\right)*\left(\frac{1}{\beta +1}+\frac{\beta }{\beta +1}*\frac{\frac{1}{{\mathrm{sC}}_1}}{R_1+\frac{1}{{\mathrm{sC}}_1}}\right)*g_m*\frac{K_{\mathrm{ICO}}}{s}*\frac{1}{N}& \left(15\right)\end{array}$

From equation (15), the pole and zero position may be:

$\begin{array}{cc}{\omega }_z=\frac{\left(1+\beta \right)}{R_1{C}_1}& \left(16\right)\\ {\omega }_p=\frac{1}{R_1{C}_2}\left(1+\frac{C_2}{C_1}\right)& \left(17\right)\\ \frac{{\omega }_p}{{\omega }_z}=\frac{1}{\left(1+\beta \right)}\frac{C_1+C_2}{C_2}& \left(18\right)\end{array}$

The gain bandwidth may be:

$\begin{array}{cc}{\omega }_c\approx \frac{I_{\mathrm{cp}}}{2*\pi }*R_1*\frac{g_m}{1+\beta }*K_{\mathrm{ICO}}*\frac{1}{N}& \left(19\right)\end{array}$

As the impedance of C1 is far smaller than that of C2, the thermal noise contributed by R1 at the junction between R1 and C1 is negligible compared to that at the junction R1 and C2. As a result, the output phase noise contributed by R1 at the output frequency ω_out of the PLL 300 may be:

$\begin{array}{cc}\begin{array}{c}{\phi }_n^2=4*K*T*R_1*{\left(g_{\mathrm{m\_A}}*\frac{K_{\mathrm{ICO}}}{s}\right)}^2\\ =4*K*T*R_1*{\left(\frac{g_m}{1+\beta }*\frac{K_{\mathrm{ICO}}}{s}\right)}^2={\left(\frac{1}{1+\beta }\right)}^2*{\varphi }_n^2\end{array}& \left(20\right)\end{array}$

where φ_n² is the output phase noise contributed by R1 at the output frequency ω_out of the PLL 100.

Compared to equation (3), equation (18) indicates that the pole over zero ratio of the PLL 300 is 1/(1+β) times of that of the known PLL 100. This will make the PLL loop unstable. In addition, equation 20 indicates that, due to the frequency tuning gain K_VCO is reduced to 1/(1+β) times, the phase noise contribute by R1 is reduced to 1/(1+β)² times.

One way to improve the loop stability of the PLL 300 may be to increase the value of C1 to its (1+β) times. However, this may make the die size consumption unacceptable, since C1 is a big capacitor.

Another way to improve the loop stability of the PLL 300 may be to decrease the value of C2 to its 1/(1+β) and increase the value of R1 to its (1+β) times. Since the resistor may become R1*(1+β), which will contribute 4*K*T*R1*(1+β) to the noise, the noise reduction benefit depicted by equation 20 may be substituted with equation 23. Equation 23 also indicates that, in the PLL 300, the phase noise contributed by the filter resistor R1 may be improved to 1/(1+β) times of that in the PLL 100. Properties of such a PLL may be:

$\begin{array}{cc}{\omega }_Z^{\prime }=\frac{\left(1+\beta \right)}{R_1^{\prime }{C}_1}=\frac{\left(1+\beta \right)}{\left(\left(1+\beta \right)*R_1\right)*C_1}=\frac{1}{R_1{C}_1}& \left(21\right)\\ \begin{array}{c}{\omega }_p^{\prime }=\frac{1}{R_1^{\prime }{C}_2^{\prime }}*\left(1+\frac{C_2^{\prime }}{C_1}\right)=\frac{1}{\left(1+\beta \right)*R_1*\frac{1}{1+\beta }*C_2}*\\ \left(1+\frac{\frac{1}{1+\beta }*C_2}{C_1}\right)\approx \frac{1}{R_1{C}_2}\end{array}& \left(22\right)\\ \begin{array}{c}{\phi }_n^2=4*K*T*R_1*{\left(g_{\mathrm{m\_A}}*\frac{K_{\mathrm{ICO}}}{s}\right)}^2\\ =4*K*T*\left(1+\beta \right)*R_1*{\left(\frac{g_m}{1+\beta }*\frac{K_{\mathrm{ICO}}}{s}\right)}^2=\frac{1}{1+\beta }*{\varphi }_n^2\end{array}& \left(23\right)\end{array}$

One way to both improve the loop stability and further reduce the output phase noise of the PLL 300 is to use capacitor multiplication. FIG. 10 is a circuit schematic depicting a PLL corresponding to the PLL 300 of FIG. 3, with the VCO 304 corresponding to VCO 204 in FIG. 2, but with a passive loop filter with capacitor multiplication according to one embodiment. A replica charge pump 1002 may be added to construct an equivalent capacitor multiplication for C1. The replica charge pump 1002 may have a current source 10021, switches 10022 and 10023, and a current source 10024 coupled in series between the fixed voltage AVDD and the fixed voltage P, in parallel with the charge pump 302. The switch 10022 may be controlled by the switching signal PD from the PFD 301, and be turned on and off approximately simultaneously with the switch 3022, but in the opposite direction. The switch 10023 may be controlled by the switching signal PU from the PFD 301, and be turned on and off approximately simultaneously with the switch 3023, but in the opposite direction. The junction of R1 and C1 in the loop filter 303, from where the control voltage V_ctrl—B of the voltage to current converter 3042B is taken, may be coupled to the junction of switches 10022 and 10023. The current provided by the current source 10021 may be a times the current provided by the current source 3021 in the charge pump 302, wherein α<1.

When ω_fb is lower than the reference frequency ω_ref, the PFD 301 may output switching signals PU and PD to the charge pump 302 and the replica charge pump 1002, closing switches 3022 and 10023 and keeping switches 3023 and 10022 open. When f<1/(C1R1), since 1/(sC2)>>(R1+1/(sC1), most of the current I_CP coming from the current source 3021 in the charge pump 302 may go through C1. At the same time, since 1/(sC1)<<(R1+1/sC2)), most of the current from the current source 10024 in the replica charge pump 1002, which is in the opposite direction of the current I_CP coming from the current source 3021 and is αI_CP, may go through C1 as well. Thus, the actual current going through C1 is I_CP*(1−α), and the actual voltage drop over C1 is about I_CP*(1−α)/(s*C1), which means that the equivalent value of C1 may be amplified by 1/(1−α).

When α=⅞, for example, for each charge unit charged to C1 from the current source 3021 via the switch 3022 and R1, ⅞ of the charge unit may be drawn from C1 by the current source 10024 via R1 and the switch 10023. Thus, the value of C1 may be amplified by 8 times, without changing the size of C1 and reducing chip area efficiency, and the variation of V_ctrl—B in the PLL 1000 may reduce ⅞.

When ω_fb is higher than the reference frequency ω_ref, the PFD 301 may send switching signals PU and PD to the charge pump 302 and 1002, keeping switches 3022 and 10023 open while closing switches 3023 and 10022. Consequently, C1 may discharge via R1 and the switch 3023 and the discharge current is I_CP. At the same time, the current source 10022 may charge C1 via the switch 10022 and R1, and the charging current may be α*I_CP.

When ω_fb equals ω_ref, the PFD 301 may keep the switches 3022 and 3023 in the charge pump 302 and switches 10022 and 10023 in the replica charge pump closed to maintain the relationship.

The frequency tuning gain of the PLL 1000 may be similar to that of PLL 300. However, since the variation of V_ctrl—B is significantly reduced, the loop stability of PLL 1000 may be much better than that of PLL 300.

Properties of the PLL 1000 may be:

$\begin{array}{cc}{V}_{\mathrm{ctrl\_A}}=I_{\mathrm{CP}}\left(\frac{1}{{\mathrm{sC}}_2}//\left(R_1+\frac{1}{{\mathrm{sC}}_1}\right)\right)-I_{\mathrm{CP}}\alpha \left(\frac{1}{{\mathrm{sC}}_1}//\left(R_1+\frac{1}{{\mathrm{sC}}_2}\right)\right)\frac{\frac{1}{{\mathrm{sC}}_2}}{R_1+\frac{1}{{\mathrm{sC}}_2}}& \left(24\right)\\ V_{\mathrm{ctrl\_B}}=I_{\mathrm{CP}}\left(\frac{1}{{\mathrm{sC}}_2}//\left(R_1+\frac{1}{{\mathrm{sC}}_1}\right)\right)\frac{\frac{1}{{\mathrm{sC}}_1}}{R_1+\frac{1}{{\mathrm{sC}}_1}}-I_{\mathrm{CP}}\alpha \left(\frac{1}{{\mathrm{sC}}_1}//\left(R_1+\frac{1}{{\mathrm{sC}}_2}\right)\right)& \left(25\right)\end{array}$

When I_A=V_ctrl—A*g_m—A, I_B=V_ctrl—B*g_m—B, and

$g_{\mathrm{m\_A}}=\frac{g_m}{\beta +1},g_{\mathrm{m\_B}}=\frac{g_m*\beta }{\beta +1},$ then:

$\begin{array}{cc}{I}_C=I_A+I_B=V_{\mathrm{ctrl\_A}}*g_{\mathrm{m\_A}}+V_{\mathrm{ctrl\_B}}*g_{\mathrm{m\_B}}=\frac{1}{1+\beta }*I_{\mathrm{cp}}*\frac{s*\left(R_1*C_1-R_1*C_2*\beta *\alpha \right)+\left(1+\beta \right)*\left(1-\alpha \right)}{s*\left(s*R_1*C_1*C_2+C_1+C_2\right)}*g_m& \left(26\right)\end{array}$

The open loop transfer function may be:

$\begin{array}{cc}{H}_o\left(s\right)=\frac{I_{\mathrm{cp}}}{2*\pi }*\frac{1}{1+\beta }*\frac{s*\left(R_1*C_1-R_1*C_2*\beta *\alpha \right)+\left(1+\beta \right)*\left(1-\alpha \right)}{s*\left(s*R_1*C_1*C_2+C_1+C_2\right)}*g_m*\frac{K_{\mathrm{ICO}}}{s}*\frac{1}{N}& \left(27\right)\end{array}$

From equation (27), especially when α=β/(β+1), the pole and zero position may be:

$\begin{array}{cc}{\omega }_z=\frac{\left(1+\beta \right)*\left(1-\alpha \right)}{R_1^{*}\left(C_1-C_2*a\right)}=\frac{1}{R_1*\left(C_1-C_2*\alpha \right)}\approx \frac{1}{R_1*C_1}& \left(28\right)\\ {\omega }_p=\frac{1}{R_1{C}_2}\left(1+\frac{C_2}{C_1}\right)& \left(29\right)\\ \frac{{\omega }_p}{{\omega }_z}=\frac{C_1-C_2*\alpha }{\left(1+\beta \right)*\left(1-\alpha \right)}*\frac{C_1+C_2}{C_1*C_2}\approx \frac{C_1+C_2}{C_2}& \left(30\right)\end{array}$

The output phase noise contributed by R1 may be:

$\begin{array}{cc}\begin{array}{c}{\phi }_n^2=4*K*T*R_1*{\left(g_{\mathrm{m\_A}}*\frac{K_{\mathrm{ICO}}}{s}\right)}^2\\ =4*K*T*R_1*{\left(\frac{g_m}{1+\beta }*\frac{K_{\mathrm{ICO}}}{s}\right)}^2={\left(\frac{1}{1+\beta }\right)}^2*{\varphi }_n^2\end{array}& \left(31\right)\end{array}$

Equation (30) may indicate that the ratio of pole and zero position of the PLL 1000 in FIG. 10 is better than that of PLL 300 in FIG. 3 (expressed by equation (17)), and is similar to that of PLL 100 in FIG. 1 (expressed by equation (3)).

Equation (31) may indicate that the output phase noise contributed by R1 in the PLL 1000 may be 1/(1+β) times of that in the PLL 300 (expressed by equation (19)), and 1/(1+β)² times of that in the PLL 100.

In sum, PLL 1000 and PLL 300 may reduce the frequency tuning gain to about 1/(1+β) of that of the known PLL 100. PLL 1000 may reduce the output noise contributed by R1 to 1/(1+β) times of that in the PLL 300, and 1/(1+β)² times of that in the PLL 100. In addition, with the capacitor multiplication provided by the replica charge pump, the PLL 1000 may achieve similar loop stability of that of PLL 100 without increasing the size of C1, C2 or R1. Table 1 is an exemplary performance comparison between a known PLL 100 and a PLL 1000 according to one embodiment.

		Conventional Structure	This Work
	Kvco	1.5	GHz/V	0.3	GHz/V
	fo	1.3	GHz	1.3	GHz
	fref	26	MHz	26	MHz
	N	50		50
	α	No data	7/8
	β	No data	4
	Icp	270	uA	340	uA
	R1	2	kΩ	8	kΩ
	C1	120	PF	30	PF
	C2	8	PF	2	PF
	fc	2.6	MHz	2.6	MHz
	fz	0.65	MHz	0.575	MHz
	fp	10.35	MHz	11.04	MHz
	Phase Margin	60	Degree Celsius	63	Degree Celsius
	Phase Noise	−106.3 dBc @ 1.5 MHz	−118 dBc @ 1.5 MHz
	contribute by
	R1 at the out-
	put frequency

Several features and aspects have been illustrated and described in detail with reference to particular embodiments by way of example only, and not by way of limitation. Alternative implementations and various modifications to the disclosed embodiments are within the scope and contemplation of the present disclosure. For example, bipolar junction transistors (BJTs) or junction gate field-effect transistors (JFETs) may be used to replace the FETs in the embodiments. Therefore, it is intended that the invention be considered as limited only by the scope of the appended claims.

Claims

1. A voltage-controlled oscillator (VCO), comprising: a voltage supply;a voltage to current converter for converting a voltage signal from the voltage supply into a control current, the voltage to current converter comprising a first voltage to current converter responsive to a first control voltage and a second voltage to current converter responsive to a second control voltage and coupled in parallel to said first voltage to current converter to produce the control current; anda current-controlled oscillator (ICO), generating an output frequency in response to the control current.

2. The VCO of claim 1, wherein the trans-conductance of the first voltage to current converter is 1/β of that of the second voltage to current converter, and wherein β>.

3. The VCO of claim 2, wherein the first voltage to current converter is controlled by a first control voltage, which is an output voltage of a loop filter in a phase-locked loop (PLL).

4. The VCO of claim 1, wherein the first voltage to current converter and the second voltage to current converter comprise transistors.

5. The VCO of claim 1, wherein the first voltage to current converter and the second voltage to current converter comprise field effect transistors (FETs).

6. The VCO of claim 4, wherein the current to voltage converter further comprises a current mirror coupled between a joint output of the first and second voltage to current converter and the ICO.

7. The VCO of claim 2, wherein the second voltage to current converter is controlled by a second control voltage, which is a relative DC voltage.

8. A phase-locked loop (PLL), comprising: a phase and frequency detector (PFD) for comparing a feedback frequency and a reference frequency and generating a first switching signal and a second switching signal;a first charge pump, comprising a first current source coupled in series with a first switch, a second switch and a second current source, wherein the first switch is controlled by the first switching signal, the second switch is controlled by the second switching signal and the first current source provides a current ICP;a loop filter, comprising a first branch and a second branch coupled in parallel, wherein the first branch comprises a resistance device coupled in series with a first charge storage device, and the second branch comprises a second charge storage device, said loop filter producing first and second control voltages; anda voltage controlled oscillator (VCO) providing an output frequency and comprising: a voltage supply;a voltage to current converter for converting a voltage signal from the voltage supply into a control current, the voltage to current converter comprising a first voltage to current converter responsive to the first control voltage and a second voltage to current converter responsive to the second control voltage and coupled in parallel to the first voltage to current converter to produce the control current; anda current-controlled oscillator (ICO), generating the output frequency in response to the control current,wherein the output frequency is sent to the PFD as the feedback frequency.

9. The PLL of claim 8, wherein the first control voltage is taken from a junction of the resistance device and the second charge storage device, and the second control voltage is taken from a junction of the first charge storage device and the resistance device.

10. The PLL of claim 8, wherein the first switch is closed to charge the first charge storage device to raise the first control voltage.

11. The PLL of claim 8, wherein the second switch is closed to discharge the first charge storage device to decrease the first control voltage.

12. The PLL of claim 8, further comprising a second charge pump coupled in parallel with the first charge pump, wherein the second charge pump comprises a third current source, a third switch, a fourth switch and a fourth current source coupled in series, to charge or discharge the junction of the resistance device and the first charge storage device.

13. The PLL of claim 12, wherein the third current source provides a current α*ICP to decrease voltage variations over the first charge storage device, and wherein α<1.

14. The PLL of claim 12, wherein the third switch is turned on and off approximately simultaneously with the first switch, but in the opposite direction.

15. The PLL of claim 12, wherein the fourth switch is turned on and off approximately simultaneously with the second switch, but in the opposite direction.

16. A method for controlling a voltage-controlled oscillator (VCO), comprising: converting a voltage signal into a first control current with a first voltage to current converter responsive to a first control voltage and a second control current with a second voltage to current converter responsive to a second control voltage;combining the first control current and the second control current into a control current; andgenerating an output frequency in response to the control current with a current-controlled oscillator (ICO).

17. The method of claim 16, wherein the trans-conductance of the first voltage to current converter is 1/β of that of the second voltage to current converter, and wherein β>1.

18. The method of claim 16, further comprising: controlling a value of the first control current with a first control voltage, which is an output voltage of a loop filter in a phase-locked loop (PLL).

19. The method of claim 16, further comprising: controlling a value of the second control current with a second control voltage, which is a relative DC voltage.

20. The method of claim 16, further comprising: amplifying the control current with a current mirror.