Patent Application
20230208408
The technology of the disclosure relates generally to voltage conversion, and particularly to a circuit for converting a signal at a first voltage to a signal at a second voltage.
Significant technological advancements have been made in wireless communication systems to achieve high data throughput, improved coverage range, enhanced signaling efficiency, and reduced latency compared to previous communication systems. Mobile communication devices have become increasingly common in current society for providing wireless communication services. The popularity of mobile communication devices is further driven by evolution from purely communication devices to sophisticated mobile multimedia centers that enable enhanced user experiences. A wide variety of user applications are made possible by combining the advanced communication capabilities of wireless communication systems with high-performance processing in mobile devices. Thus, in addition to analog radio frequency (RF) circuits for wireless communication, mobile communication devices include digital processing circuits for controlling the analog RF circuits, executing application software, and managing data.
With the increased circuitry provided in mobile devices that all consume battery power, advances have been made in digital circuit technology to reduce power consumption to extend battery life. Such advances include reducing the power supply voltage used to power transistors in digital circuits. However, there is still a need for high power circuits, such as power amplifiers for wireless transmission and reception. Higher powered RF circuits can operate at voltage levels that are significantly higher than and may be multiples of the power supply voltage of the digital circuits. Since data received by the analog RF circuits is processed in the digital processing circuits and the processed data is then transmitted back out by the analog RF circuits, there are many points of interaction between digital circuits and analog circuits in a mobile device. Signals generated in the digital circuits at the lower power supply voltage may be too low in voltage for use in the analog RF circuits. Therefore, level shifter circuits are used at interfaces between a first circuit, such as a digital circuit operating at a lower voltage, and a second circuit, such as an analog RF circuit operating at a higher voltage, to convert signals generated in the lower voltage range to the higher voltage range for use in the second circuit. Given the number of level shifter circuits that may be used in a mobile device, it is important to minimize the power consumption of each level shifter circuit.
Aspects disclosed in the detailed description include a low leakage level shifter circuit. An integrated circuit (IC) including a first circuit, a second circuit, and a level shifter circuit is also disclosed. A level shifter circuit converts a lower voltage signal to a higher voltage signal. The level shifter includes a half-latch with an output node that is toggled between the higher voltage and a reference voltage (e.g., ground) based on an input signal being toggled between the lower voltage and the reference voltage. Cross-coupled transistors of the half-latch keep one of the output node and a complement node charged to the higher voltage while the other node is at the reference voltage. The charged node is discharged by a discharge transistor, and the previously discharged node is allowed to charge through a charge transistor to toggle the half-latch. The discharge transistor needs to discharge the charged node at a rate faster than a charge transistor can provide charge. In this regard, a higher current through the discharge transistor is needed. However, the input signal provided to the gate of the discharge transistors only partially turns on the discharge transistor because the input signal is at the lower voltage. Thus, the discharge transistor conducts only a fraction of its maximum current capacity. To provide the higher current, the discharge transistor can be sized large enough that the fractional current of the discharge transistor, when it is partially turned-on, is able to discharge the charged node, but the leakage current through the discharge transistor increases as it increases in size. In an exemplary aspect, a first resistor and a second resistor are coupled between the charge transistors and a voltage source, providing the higher voltage to the half-latch. The first and second resistors reduce current through the respective charge transistors. In this regard, a smaller current is needed to discharge a node, so discharge transistors of a smaller size can be employed to avoid a large leakage current.
In one exemplary aspect, a level shifter circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor is disclosed. The first resistor is coupled between a supply node and a first terminal of the first transistor, and the second resistor is coupled between the supply node and a first terminal of the second transistor. A gate of the first transistor is coupled to a first terminal of the fourth transistor and a second terminal of the second transistor to provide an output node, and a gate of the second transistor is coupled to a first terminal of the third transistor and a second terminal of the first transistor to provide a first node. The output node transitions between a supply voltage provided at the supply node and a reference voltage based on input signals provided to the gate of the third transistor and the gate of the fourth transistor. As the output node transitions from the supply voltage to the reference voltage, the second resistor limits current flow through the second transistor to less than current flow through the fourth transistor to discharge the output node, and as the output node transitions from the reference voltage to the supply voltage, the first resistor limits current flow through the first transistor to less than current flow through the third transistor to discharge the first node.
In another exemplary aspect, an integrated circuit is disclosed. The integrated circuit comprises a first circuit configured to generate a first signal at a first supply voltage, a second circuit configured to receive a second signal at a second supply voltage, and a level shifter circuit configured to convert signals from the first supply voltage to the second supply voltage. A level shifter circuit comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor is disclosed. The first resistor is coupled between a supply node and a first terminal of the first transistor, and the second resistor is coupled between the supply node and a first terminal of the second transistor. A gate of the first transistor is coupled to a first terminal of the fourth transistor and a second terminal of the second transistor to provide an output node, and a gate of the second transistor is coupled to a first terminal of the third transistor and a second terminal of the first transistor to provide a first node. The output node transitions between a supply voltage provided at the supply node and a reference voltage based on input signals provided to the gate of the third transistor and the gate of the fourth transistor. As the output node transitions from the supply voltage to the reference voltage, the second resistor limits current flow through the second transistor to less than current flow through the fourth transistor to discharge the output node, and as the output node transitions from the reference voltage to the supply voltage, the first resistor limits current flow through the first transistor to less than current flow through the third transistor to discharge the first node.
In a further exemplary aspect, a level shifter circuit comprising a half-latch is disclosed. The half-latch comprises an output node coupled to a gate of a first charge transistor and an output terminal of a second charge transistor and a complement node coupled to a gate of the second charge transistor, and an output terminal of the first charge transistor. The level shifter circuit further comprises a first discharge transistor coupled to the complement node to discharge the complement node and a second discharge transistor coupled to the output node to discharge the output node. The level shifter circuit comprises a first resistor coupled between an input terminal of the first charge transistor and a supply node to limit current for charging the complement node, and a second resistor coupled between an input terminal of the second charge transistor and the supply node to limit current for charging the output node.
Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings.
The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.
It will be understood that, although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Aspects disclosed in the detailed description include a low leakage level shifter circuit. An integrated circuit including a first circuit, a second circuit, and a level shifter circuit is also disclosed. A level shifter circuit converts a lower voltage signal to a higher voltage signal. The level shifter includes a half-latch with an output node that is toggled between the higher voltage and a reference voltage (e.g., ground) based on an input signal being toggled between the lower voltage and the reference voltage. Cross-coupled transistors of the half-latch keep one of the output node and a complement node charged to the higher voltage while the other node is at the reference voltage. The charged node is discharged by a discharge transistor, and the previously discharged node is allowed to charge through a charge transistor to toggle the half-latch. The discharge transistor needs to discharge the charged node at a rate faster than a charge transistor can provide charge. In this regard, a higher current through the discharge transistor is needed. However, the input signal provided to the gate of the discharge transistors only partially turns on the discharge transistor because the input signal is at the lower voltage. Thus, the discharge transistor conducts only a fraction of its maximum current capacity.
To provide the higher current, the discharge transistor can be sized large enough that the fractional current of the discharge transistor, when it is partially turned-on, is able to discharge the charged node, but the leakage current through the discharge transistor increases as it increases in size. In an exemplary aspect, a first resistor and a second resistor are coupled between the charge transistors and a voltage source, providing the higher voltage to the half-latch. The first and second resistors reduce current through the respective charge transistors. In this regard, a smaller current is needed to discharge a node, so discharge transistors of a smaller size can be employed to avoid a large leakage current.
Before discussing an exemplary level shifter circuit illustrated in
The half-latch 106 includes cross-coupled charge transistors 112A and 112B. A gate 114A of the charge transistor 112A is coupled to the complement node 110, which is further coupled to a second terminal 116B of the charge transistor 112B. A gate 114B of the charge transistor 112B is coupled to the output node 104, which is further coupled to a second terminal 116A of the charge transistor 112A. The charge transistor 112A includes a first terminal 118A coupled to a supply node 120 and selectively provides the higher voltage VHIGH from the supply node 120 to the output node 104 based on the complement voltage VCOMP on the complement node 110. The charge transistor 112B includes a first terminal 118B coupled to the supply node 120 and selectively provides the higher voltage VHIGH to the complement node 110 based on the output voltage VOUT on the output node 104.
The discharge transistor 108A is coupled between the output node 104 and a reference node 122 (e.g., ground) at the reference voltage VGND (e.g., 0 V) and discharges the output node 104 to the reference voltage VGND based on an input signal 102A received on a gate 124A of the discharge transistor 108A. A discharge transistor 108B is coupled between the complement node 110 and the reference node 122 and discharges the complement node 110 down to the reference voltage VGND based on an input signal 102B received on a gate 124B of the discharge transistor 108B. The input signals 102A and 102B are complementary to each other. If the input signal 102A is at the lower voltage VLOW, the input signal 102B is at the reference voltage VGND, and if the input signal 102A is at the reference voltage VGND, the input signal 102B is at the lower voltage VLOW. Thus, only one of the discharge transistors 108A and 108B is turned on at a time.
In the above configuration, if the input signal 102B is at the lower voltage VLOW and the input signal 102A is at the reference voltage VGND, the discharge transistor 108B is turned on to discharge the complement node 110, and the discharge transistor 108A is turned off. In this state, the discharged complement node 110 is coupled to the reference node 122, bringing the complement voltage VCOMP to the reference voltage VGND, which turns on the charge transistor 112A and causes the output node 104 to be at the higher voltage VHIGH. The higher voltage VHIGH on the output node 104 causes the charge transistor 112B to be turned off, maintaining the complement node 110 in a stable state at the reference voltage VGND.
To toggle the output voltage VOUT on the output node 104 from the high voltage VHIGH to the reference voltage VGND, the input signals 102A and 102B are flipped in polarity. With the input signal 102B at the reference voltage VGND and the input signal 102A at the lower voltage VLOW, the discharge transistor 108A is turned on to discharge the output node 104 while the discharge transistor 108B is turned off. In this state, the output node 104 becomes coupled to the reference node 122 while the output node 104 is still coupled to the supply node 120 by the charge transistor 112A. The cross-coupled charge transistors 112A and 112B of the half-latch 106 tend to hold the output voltage VOUT stable. Therefore, immediately after the input signals 102A and 102B switch and the output node 104 is coupled to the reference node 122, the output voltage VOUT is still at the higher voltage VHIGH, and the complement voltage VCOMP is at the reference voltage VGND. In this condition, the discharge transistor 108A discharges the output node 104 as the charge transistor 112A continues to charge the output node 104 from the supply node 120.
If the rate at which the discharge transistor 108A discharges the output node 104 is higher than the rate at which the charge transistor 112A charges the output node 104, the output voltage VOUT will begin to decrease. In other words, if the current through the discharge transistor 108A is greater than current through the charge transistor 112A, the output node 104 will discharge. As the output voltage VOUT on the output node 104 decreases, the charge transistor 112B begins to turn on, which begins to charge the complement node 110. In turn, as the complement node 110 begins to charge, the charge transistor 112A begins to turn off, which decreases the current flowing through the charge from the supply node 120 to the output node 104. As this continues, the charge transistor 112B becomes fully turned on, and the complement node 110 is fully charged to the higher voltage VHIGH. Since the input signal 102B is at the reference voltage VGND, the discharge transistor 108B does not discharge the complement node 110. In turn, the charge transistor 112A is fully turned off, and the discharge transistor 108A discharges the output node 104 down to the reference voltage VGND.
The current needed in the discharge transistor 108A in the above scenario to discharge the output node 104 to toggle the output node 104 must be greater than a current through the charge transistor 112A. Otherwise, the output node 104 would not become discharged and would not toggle. If the discharge transistor 108A was fully turned on by the input signal 102A, and the maximum current capacity of the discharge transistor 108A is large enough for the needed discharge current, the output node 104 will toggle. However, the discharge transistor 108A needs to be configured with a higher breakdown voltage in order to operate without failure when the higher voltage VHIGH is provided at the first terminal 118A, the reference voltage VGND is provided at the second terminal 116A, and either the lower voltage VLOW or the reference voltage VGND is provided at the gate 114A. The breakdown voltage may be increased by increasing the thickness of a gate oxide.
A consequence of increasing gate oxide thickness is an increase in the voltage needed to fully turn on the transistor. Therefore, the discharge transistors 108A configured to handle the higher voltage VHIGH are not fully turned on by the low voltage VLOW on input signal 102A. To ensure that the discharge transistor 108A conducts sufficient discharge current to toggle the output node 104 when only partially turned on by the lower voltage VLOW on the input signals 102A, 102B, the size of the discharge transistor 108A is increased. However, a consequence of using a larger size discharge transistor is a correspondingly larger leakage current.
For example, the lower voltage VLOW may be a percentage (e.g., 15%-20%) of the higher voltage VHIGH. The level shifter circuit 200 includes a half-latch 206 coupled to the output node 202, which is toggled between the higher voltage VHIGH and a reference voltage VGND (e.g., 0 V) based on the input signal 204B being toggled between the lower voltage VLOW and the reference voltage VGND. Cross-coupled charge transistors 208A, 208B of the half-latch 206 keep one of the output node 202 and a complement node 210 charged to the higher voltage VHIGH while the other node is at the reference voltage VGND. Toggling the half-latch 206 includes discharging the charged node by one of discharge transistor 212A and discharge transistor 212B and allowing the previously discharged node to charge through one of the charge transistors 208A, 208B.
The terms “charge transistor” and “discharge transistor” as used herein are only intended to be indicative of a function performed by a transistor in the level shifter circuit 200 and not intended to limit physical aspects of the transistors so described. The discharge transistors 212A, 212B need to pass a sufficient current to discharge the charged node at a rate faster than a charge transistor 208A, 208B can provide charge.
The input signals 204A, 204B provided to gates 214A, 214B of the discharge transistors 212A, 212B, which are configured for handling the higher voltage VHIGH do not fully turn on the discharge transistors 212A, 212B. Because the discharge transistors 212A, 212B are only partially turned on by the lower voltage VLOW of the input signals 204A, 204B, the discharge transistors 212A, 212B are sized to have a maximum current capacity much larger than the discharge current.
In an exemplary aspect, the first resistor R0 and the second resistor R1 are coupled between the charge transistors 208A, 208B, and a supply node 216 providing the higher voltage VHIGH. The supply node 216 may be a supply voltage rail. The first and second resistors R0, R1 reduce current through the respective charge transistors 208A, 208B. Consequently, the current needed to discharge a node to toggle the output node 202 of the half-latch 206 is reduced. In this regard, discharge transistors 212A, 212B employed to toggle the output node 202 based on the input signals 204A, 204B can be much smaller in size. Consequently, the leakage current ILEAK through the discharge transistors 212A, 212B is reduced compared to existing level shifter circuits.
To further clarify the structural aspects described above, the level shifter circuit 200 comprises the charge transistor 208A, the charge transistor 208B, the discharge transistor 212A, the discharge transistor 212B, the first resistor R0, and the second resistor R1. The first resistor R0 is coupled between the supply node 216 and a first terminal 218A of the charge transistor 208A. The second resistor R1 is coupled between the supply node 216 and a first terminal 218B of the charge transistor 208B. A gate 220B of the charge transistor 208B is coupled to the output node 202, which is further coupled to a first terminal 222A of the discharge transistor 212A and a second terminal 224A of the charge transistor 208A. A gate 220A of the charge transistor 208A is coupled to the complement node 210, which is further coupled to a first terminal 222B of the discharge transistor 212B and a second terminal 224B of the charge transistor 208B. The output voltage VOUT on the output node 202 transitions (“toggles”) between the higher voltage VHIGH provided at the supply node 216 and the reference voltage VGND based on input signals 204A, 204B provided to the gate 214B of the discharge transistor 212B and the gate 214A of the discharge transistor 212A.
As the output voltage VOUT on the output node 202 transitions from the higher voltage VHIGH to the reference voltage VGND, the first resistor R0 limits current flow through the charge transistor 208A to be less than current flow through the discharge transistor 212A to discharge the output node 202. Alternatively, as the output voltage VOUT on the output node 202 transitions from the reference voltage VGND to the supply voltage VHIGH, the second resistor R1 limits current flow through the charge transistor 208B to be less than current flow through the discharge transistor 212B, allowing the discharge transistor 212B to discharge the complement node 210 to a reference node 225.
In the level shifter circuit 200, the output node 202 transitions from the higher voltage VHIGH to the reference voltage VGND in response to the input signal 204a provided to the gate 214A of the discharge transistor 212A transitioning from the reference voltage VGND to the low supply voltage VLOW, which is lower than the higher voltage VHIGH and the input signal 102B provided to the gate 214B of the discharge transistor 212B transitioning from the low voltage VLOW to the reference voltage VGND. The output node 202 transitions in the other direction, from the reference voltage VGND to the higher voltage VHIGH in response to the input signal 204A provided to the gate 214A of the discharge transistor 212A transitioning from the low supply voltage VLOW to the reference voltage VGND and the input signal 204B provided to the gate 214B of the discharge transistor 212B transitioning from the reference voltage VGND to the low voltage VLOW.
The input signals 204A and 204B are binary complements of each other, such that when one is at the lower voltage VLOW, the other is at the reference voltage VGND. An asserted state may correspond to either the low voltage VLOW or the reference voltage VGND. To provide the input signal 204A complementary to the input signal 204B, the input signal 204B is provided to an input 226 of an inverter circuit 228, shown in
With further reference to
In some examples, the effect of the resistor R0 is to limit current through the charge transistor 208A when the output node 202 is discharging to less than or equal to twenty percent (20%) of a maximum current capacity of the charge transistor 208A. Similarly, the effect of the resistor R1 is to limit current through the charge transistor 208B, when the complement node 210 is discharging, to less than or equal to twenty percent (20%) of a maximum current capacity of the charge transistor 208A. In some examples, the resistances of resistors R0 and R1 are set to limit current through the charge transistor 208B to less than or equal to ten percent (10%) of the maximum current capacity of the charge transistors 208A, 208B.
Increasing the resistances of the resistors R0 and R1 reduces the current through the charge transistors 208A, 208B to have the effect of reducing the sizes of the discharge transistors 212A, 212B to reduce leakage current. However, reducing current through the charge transistors 208A, 208B increases the time required to charge the output node 202 or the complement node 210, which increases the time for toggling the half-latch 206. In this regard, an increase in the resistances of the resistors R0 and R1 can limit the bandwidth of the level shifter circuit 200. Thus, in some examples, the resistances of the resistors R0 and R1 may be in a range from twenty (20) kilohms to forty (40) kilohms and may preferably be in a range from twenty-five (25) kilohms to thirty-five (35) kilohms. To avoid a difference in timing between toggling from the high voltage VHIGH to the reference voltage VGND and from the reference voltage VGND to the high voltage VHIGH, the resistances of the resistors R0 and R1 are the same, or the resistance of the first resistor R0 is within five percent (5%) of the resistance of the second resistor R1.
In some examples, the charge transistors 208A, 208B are P-type metal-oxide-semiconductor (MOS) (PMOS) field-effect transistors (FETS) (MOSFETS), where a semiconductor of a P-type MOSFET is doped with trivalent atoms. In some examples, the discharge transistors 212A, 212B are N-type MOSFETs, where a semiconductor of an N-type MOSFET is doped with pentavalent atoms.
The level shifter circuit 200 may also be described as the half-latch 206, including the output node 202 coupled to the gate 220B of the charge transistor 208B and a second terminal 224B of the charge transistor 208A. The half-latch 206 also includes the complement node 210 coupled to the gate 220A of the charge transistor 208A and the second terminal 224B of the charge transistor 208B. The level shifter circuit 200 also includes the discharge transistor 212B coupled to the complement node 210 to discharge the complement node 210 and the discharge transistor 212A coupled to the output node 202 to discharge the output node 202. The level shifter circuit 200 also includes the resistor R1 coupled between a first terminal 218B of the charge transistor 208B and the supply node 216 to limit current for charging the complement node 210, and the resistor R0 coupled between the first terminal 218B of the charge transistor 208A and the supply node to limit current for charging the output node.
An integrated circuit (IC) 300, as illustrated in
The IC 300 also includes a second circuit 306 that is powered by a second voltage source 308 at a higher voltage VHIGH and is configured to receive a second signal 310 at the higher voltage VHIGH. The level shifter circuit 200 is configured to convert the first input signal 204B at the lower voltage VLOW to the second signal 310 at the higher voltage VHIGH on the output node 202. The second signal 310 may also be provided on the output node 202 at the reference voltage VGND in response to the first input signal 204B being at the reference voltage VGND.
Discharging the output node 202 includes providing the input signal 204A at the lower voltage VLOW to the gate 406A of the discharge transistor 402A and to the gate 214A of the discharge transistor 212A. Discharging the complement node 210 includes providing the input signal 204B at the lower voltage VLOW to the gate 406B of the discharge transistor 402B and to the gate 214B of the discharge transistor 212B.
In contrast to the discharge transistor 212A in
Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.
