Patent Grant
10198014
This disclosure is related to the field of low dropout regulators, and more particularly, to a low dropout regulator that utilizes a low voltage ballast transistor for high bandwidth and power supply rejection, and that protects the low voltage ballast transistor from electrical overstresses.
Handheld battery powered electronic devices such as tablets and smartphones have been in wide use in recent years, with usage rates that are ever increasing, and with additional functionality being added on a regular basis.
A common type of voltage regulator used in such electronic devices is known as a low dropout (LDO) regulator, which can operate with a small input to output voltage difference, and which provides a high degree of efficiency and heat dissipation. A typical LDO regulator includes an error amplifier that controls a field effect transistor (FET) or bipolar junction transistor (BJT) to cause that transistor to sink or source current from or to an output node. One input of the error amplifier receives a feedback signal, while the other receives a reference voltage. The error amplifier controls the power FET or BJT so as to maintain a constant output voltage.
The power FET or BJT is typically tolerant of 5V, meaning that the FET or BJT therefore has a large area and a low transconductance, however to source or sink a high current, a large transconductance would be required, leading to a very large sized transistor. This in turn leads to high leakage current when the LDO is powered down. In addition, the bandwidth of the LDO is limited by a high input gate or base capacitance to the power FET or BJT. Another drawback of this design is that the power FET or BJT has a large gate to drain or base to emitter capacitance and total gate or drain capacitance due to its size, which results in degradation in high frequency power source noise rejection.
In an attempt to address these drawbacks, additional designs have been devised. For example, a LDO 100 is shown in
The transistors T1 and T2 are low voltage devices, and are to be protected from electrical overstresses. When the LDO 100 is operating in a normal power on mode, T2 is biased by amplifier 104 such that it acts as a switch. When the LDO 100 is powered down, node N1 is biased such that neither T1 nor T2 experiences overstresses. However, during the transition between the powered on mode and the powered down mode, or between the powered down mode and the powered on mode, node N1 can intermittently go to supply or ground at a different time constant than node N3, which can also go to ground. Transistor T1 can be stressed because it has no protections against such overstresses, and transistor T2 can be stressed because it is within the feedback loop.
Further development of LDO regulators is necessary to address the aforementioned drawbacks.
This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.
Disclosed herein is an electronic device including a low dropout regulator producing an output at an intermediate node and a resistive divider coupled between the intermediate node and ground, with the low dropout regulator receiving a feedback signal from a tap node of the resistive divider. A transistor has a first conduction terminal coupled to the intermediate node, a second conduction terminal coupled to an output node, and a control terminal. A first impedance is coupled to the output node, and a first switch is configured to selectively couple the first impedance to a supply node. A second impedance coupled to the output node, and a second switch is configured to selectively couple the second impedance to a ground node.
Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry is configured to switch the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.
The control circuitry is configured to switch the electronic device to a power on mode by turning on the low dropout regulator, opening the first and second switches, and turning on the transistor.
The low dropout regulator includes an amplifier receiving a reference signal and the feedback signal as input, and generating an output based on a difference between the reference signal and the feedback signal. A fourth switch is coupled between an output terminal of the amplifier and the supply node. A transistor has a first conduction terminal coupled to the supply node, a second conduction terminal coupled to the intermediate node, and a control terminal biased by the output of the amplifier. A third switch is coupled between the supply node and the second conduction terminal of the transistor of the low dropout regulator.
The control circuitry turns off the low dropout regulator by closing the third and fourth switches and turning off the amplifier. The control circuitry switches the electronic device to a power on mode by opening the third and fourth switches, turning on the low dropout regulator, opening the first and second switches, and turning on the transistor.
One or more embodiments of the present disclosure will be described below. These described embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description, some features of an actual implementation may not be described in the specification. When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements.
With reference to
The low dropout regulator 60 itself is comprised of an error amplifier 52 receiving the reference signal at a first input (non-inverting terminal), and a feedback signal Vfb at a second input (inverting terminal), and providing an output to node N4. The error amplifier 52 is powered between a supply voltage Vdd and ground. The supply voltage Vdd may be 5 V, 2.5 V, 1.8 V, 1V a voltage between 1 V and 5 V, or another suitable voltage.
The low dropout regulator 60 includes a low voltage p-channel transistor M1, which may be a PMOS transistor in some cases, and in some cases, may be a low voltage thin gate oxid transistor. The low-voltage p-channel transistor M1 serves as the ballast for the low dropout regulator 60. The p-channel transistor M1 has its source coupled to the supply voltage Vdd, its drain coupled to intermediate node N3, and its gate coupled to node N4 at the output of the error amplifier 52. A switch SW4 selectively couples node N4 (and thus the gate of the p-channel transistor M1) to the supply voltage Vdd. A switch SW3 selectively couples intermediate node N3 (and thus the drain of the p-channel transistor M1) to the supply voltage Vdd.
A first resistance R1 is coupled between the intermediate node N3 and node N2, while a second resistance R2 is coupled between the node N2 and switch SW6. Switch SW6 is coupled between resistance R2 and ground. The first resistance R1 and second resistance R2 may have the same resistance values or may have different resistance values, and in some cases one or both of these resistances R1, R2 may be programmable. R1 and R2 form a resistive voltage divider receiving the voltage at node N3 and outputting a feedback voltage Vfb.
Another low-voltage p-channel transistor M2 has its source coupled the intermediate node N3, its drain coupled to the output node N1, and its gate selectively coupled to either the supply voltage Vdd or ground by the switch SW5. This p-channel transistor M2 may also be a PMOS transistor in some cases.
A first impedance ZB1 is coupled to the output node N1, and is selectively coupled to the supply voltage Vdd by switch SW1. A second impedance ZB2 is also coupled to the output node N1, and is selectively coupled to ground by switch SW2. The first impedance ZB1 and second impedance ZB2 may have a same impedance value, or may have different impedance values.
The switches SW1, SW2, SW3, SW4, SW5, and SW6 are coupled to control circuitry 62, which serves to control actuation and deactuation of those switches via the generation of appropriate control signals.
The circuit 50 may operate in a powered down mode or a powered on mode. To switch into the powered on mode from a power off condition, the control circuitry 62 first turns on the error amplifier 52, and then opens switches SW6, SW4, and SW3. This serves to activate the low dropout regulator 60.
Then, the control circuitry 62 opens switches SW2 and SW1, removing any DC bias present at the drain of the p-channel transistor M2 at node N1. Thereafter, the control circuitry 62 sets the switch SW5 to couple the gate of transistor M2 to ground, turning the transistor M2 on.
In some cases when switching into the powered on mode, the control circuitry 62 may open switches SW2 and SW1, as well as set the switch SW5 to couple the gate of transistor M2 to ground, substantially simultaneously. In others, the control circuitry 62 may set the switch SW5 to couple the gate of transistor M2 to ground before opening the switches SW2 and SW1.
To switch into the powered down mode, the control circuitry 62 first sets the switch SW5 to couple the gate of the p-channel transistor M2 to the supply voltage Vdd to thereby turn off the p-channel transistor M2. Then, the control circuitry 62 closes the switches SW2 and SW1, forming a DC bias at the drain of the p-channel transistor M2. Thereafter, the control circuitry 62 closes switches SW6, SW4, and SW3, coupling the drain and gate of the p-channel transistor M1 to the supply voltage Vdd, thereby turning the p-channel transistor M1 off. Lastly, the error amplifier 52 is turned off.
In powered down mode, the closing of switches SW6, SW4, and SW3 protects the p-channel transistor M1, as its source, drain, and gate are all coupled to the same supply voltage Vdd. Similarly, the DC bias formed at the drain of the p-channel transistor M2 by the impedances ZB1 and ZB2 helps serve to protect the p-channel transistor M2.
In some cases when switching into the powered down mode, the control circuitry 62 may close switches SW2 and SW1, as well as set the switch SW5 to couple the gate of transistor M2 to the power supply node Vdd, substantially simultaneously. In others, the control circuitry 62 may set the switch SW5 to couple the gate of transistor M2 to the power supply node Vdd before closing the switches SW2 and SW1.
The voltage drop across p-channel transistor M2 is minimal, and neither of the p-channel transistors M1 or M2 are overstressed. However, the p-channel transistor M1 has a higher transconductance than the ballast transistor in prior art designs, and the size of the p-channel transistor M1 can be smaller than in prior art designs. Due to the smaller size of the p-channel transistor M1, the gate to drain capacitance is less than in prior designs. As a result, the p-channel transistor M1 can be fabricated such that the bandwidth of the circuit 50 can be high, and the power supply rejection can be high. Alternatively, the p-channel transistor M1 can be fabricated such that the quiescent current therethrough is substantially lowered, but with the bandwidth and power supply rejection of the circuit 50 remaining the same as prior art devices.
With additional reference to
While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be envisioned that do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the disclosure shall be limited only by the attached claims.
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|---|---|---|---|
| 9285821 | Maeda | Mar 2016 | B2 |
| 20030218476 | Lindsay | Nov 2003 | A1 |
| 20060284658 | Wright | Dec 2006 | A1 |
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| Number | Date | Country | |
|---|---|---|---|
| 20180284822 A1 | Oct 2018 | US |
