Patent Application
20240077903
Voltage reference circuits are used to generate a stable direct current (DC) reference voltages, which are minimally affected by process variation, voltage fluctuation, or temperature drift (PVT). Voltage reference circuits may be used as building blocks for integrated circuit (IC) design, such as analog, digital and mixed-signal circuits where precision voltage or current is needed. Because of their critical role in microelectronics, different techniques, technologies and circuit configurations have been applied to achieve such precision voltage.
The present disclosure, in accordance with one or more various embodiments, is described in detail with reference to the following figures. The figures are provided for purposes of illustration only and merely depict typical or example embodiments.
The figures are not exhaustive and do not limit the present disclosure to the precise form disclosed.
Reference voltage generator circuits are widely used in IC design to generate a stable direct current (DC) reference voltages. The increasing development of largescale IC necessitates the need for accurate and stable voltage references. Furthermore, accurate and precise voltage references directly impact computation accuracy of ICs, which may translate to an impact in the performance of the overall system in which an IC is included. For example, in the case of Double Data Rate 5 (DDR5) memory design, an increase in precision and stability of a reference voltage, across ranges of PVT variations, translates to an increase in power savings in the circuitry (e.g., by transmitter and receiver circuitry) because the circuitry need not be overdesigned or redundantly designed to ensure they are able to function in across PVT variation ranges. Thus, it is preferentially to provide high precision references with low sensitivity to PVT variations.
Conventional reference voltage generators, a such as those having the example circuit implementation depicted in
As alluded to above,
The operational amplifier 102 operates to ensure that the voltage at node n2 and node n3 will be the same. Additionally, due to devices M3 and M4, the current at nodes n2 and n3 are the same. The current through device M4, which is drawn to node n3 is determined by the ratio of the area of the emitter of BJT Q2 over the area of the emitter of BJT Q1 and the resistance of resistor RS1 (e.g., rs1). Thus, the difference of the base-to-emitter voltage of Q2 (e.g., VBE2) and the base-to-emitter voltage of Q1 (e.g., VBE1) over rs1 (e.g., (VBE2−VBE1)/rs1)) produces a fixed amount of current in both M3 and M4. For example, for a bipolar transistor, VBE=VTLn(IC/IS) in which VT is thermal voltage, IS the saturation current, and IC is the collector current. By proper design of the circuit, M4 and M3 are set to have similar sizes and operate in the saturation regime and operational amplifier 102 is in a negative feedback loop. This will ensure that their drain currents remain the same and equal to IC. According to Kirchhoff's Voltage Law (KVL), the input terminal of the operational amplifier 102 leads to (VBE1−VBE2)=rs1/C. If Q2 is m times larger than Q1 (e.g., Q1 is 1 transistor and Q2 is m parallel transistors), then (VBE1−VBE2)=VTLn(mIC1IS2/IC2IS1) and since IC1=IC2 and IS1=IS2, this leads to IC1,2=VTLn(m)/R. The current at M3 or M4 is then copied to device M5, which flows through resistor RS2 and BJT Q3. The output voltage at the node n3 is the base-to-emitter voltage of BJT Q3 (e.g., VBE3) plus the resistance of resistor RS2 (e.g., rs2) times the current at node n3 (e.g., I3), or Vref=VBE3+rs2I3.
While the conventional approaches, such as circuit 100, may compensate for temperature and supply voltage and produce a stable DC voltage, the conventional approaches suffers from various technical problems, particularly with respect to sensitivity to process induced variations and requiring larger physical chip real-estate requirements. That is, BJTs are generally large transistors that require physical space on the chip, which translates to larger overall IC size. Furthermore, traditionally BJTs exhibit increased variations in process due to manufacturing tolerances, thereby increasing the sensitivity of conventional circuitry to process induced variations. These increased variations must be compensated for in designing the conventional circuit, which translates to increased circuit complexity and/or reduction in PVT variation ranges for which the conventional circuit is insensitive too. While process induced variations may be addressed by trimming the IC (e.g., calibrating to account for process variations), such operations are an additional step that takes time and resources to perform.
A further technical problem associated with the conventional designs is that they require a high minimum supply voltage to operate the circuit. For example, referring to circuit 100, the minimum supply voltage VDDQ is based on the overhead voltages of device M3 and BJT Q2 to ensure that both devices operate in saturation region and pass current through the circuit 100. Accordingly, the supply voltage VDDQ must be VBE2 plus the overdrive voltage of M3 (e.g., VOV3) at a minimum, otherwise device M3 and/or BJT Q2 may turn off. As an illustrative example, for the circuit 100, VBE2 may be 0.7-0.8 volts and VOV3 may be approximately 200 millivolts. Thus, the minimum supply voltage VDDQ required for circuit 100 is around 0.9 V to 1 V, otherwise the circuit 100 would not function.
Further still, the conventional designs are capable of generating only a single, fixed reference voltage that is stable with respect to designed temperature ranges. That is, the conventional designs can only output one voltage level, and if the voltage level is adjusted the output voltage would no longer be stable with respect to temperature. For example, solving Vref=VBE3+rs2I3 of
Accordingly, embodiments of the disclosed technology relate to an improved reference voltage generator and corresponding circuit implementation and method of operation that achieve improved stability for PVT variations and reduced physical dimensions compared to existing reference voltage designs. More specifically, and as will be described in more detail later in this disclosure, embodiments disclosed herein utilize complementary metal-on-silicon (CMOS) field-effect transistors (FETs) to generate a stable DC reference voltage, which is several orders of magnitude smaller in on chip real estate than BJTs used in the conventional designs. As a result, the embodiments disclosed herein are physically smaller and subject to reduced process induced variation, as MOSFETs are generally easier to produce and can be manufactured to tighter tolerance providing less variation between components. This enables the embodiments disclosed herein to achieve improved stability in terms of PVT variations, thereby providing a technical improvement over the existing design.
Additionally, the embodiments disclosed herein are capable of operation at a minimum supply voltage substantially less than the minimum supply voltage required in the conventional bandgap designs. For example, because the gate-to-source bias voltage (VGS) required for MOSFETs to function is less than the VBE of BJTs, the minimum supply voltage required to turn on the electrical components included in the embodiments disclosed herein is less than that of the conventional designs. This enables the embodiments disclosed herein to consume less power as compared to at least the conventional bandgap designs, thereby providing another technical improvement over the existing designs.
Furthermore, the embodiments disclosed herein are capable of providing an adjustable output reference voltage that is stable with respect to PVT variations. For example, due to the physical properties of MOSFETs and the dynamics of how temperature impacts the operation thereof, as detailed below, the output reference voltage may be provided at multiple different voltage levels by the embodiments disclosed herein while maintaining the stability with respect to PVT variations. This provides yet another technical improvement over existing cross-coupled level shifters.
There are some existing approaches that employ CMOS transistors to generate a stable DC reference voltage. These approaches operate the CMOS transistors in a subthreshold region to save power, which will lead to significant process-induced variations that will necessitate calibration (e.g., trimming of the circuit). Furthermore, the temperature ranges of for which stability could be achieved is limited (e.g., 10° C.-70° C. in some cases). Whereas, the embodiments disclosed herein provide for stable DC reference voltage generation using CMOS transistors that are operated in the saturation region. As will be detailed below, the embodiments disclosed herein achieve improved TC and line regulation, across all process corners without requiring calibration. Calibration is possible for the embodiments disclosed herein which will provide increased improvements in terms of stability across larger temperature ranges and supply voltages.
For example, the range of temperatures may be representative of ambient an environmental temperatures that the reference voltage generator 200 (also referred to herein as a reference voltage generator circuit) is exposed to throughout operation. Over such a range (for example, −40° C. to 140° C.), the reference voltage generator 200 is outputs a voltage Vref that exhibits minimal variations. That is, within the temperature range, the output voltage varies only within an acceptable voltage levels. For example,
Similarly, the reference voltage generator 200 may be exposed to fluctuations in supply voltage. For example, the supply voltage may fluctuation from 106% to 97% of the designed for supply voltage due to circuity external to the reference voltage generator 200 sinking or sourcing current form the supply. As such, the reference voltage generator 200 is configured to generate an output voltage that is relatively insensitive to these fluctuations, for example, as illustratively shown in
Furthermore, process induced variations in the electrical components that make up the reference voltage generator 200 may provide for variations in electrical properties between physical implementations of the reference voltage generator 200. For example, variations in physical properties of electrical components due manufacturing tolerances (e.g., semiconductor doping levels and concentrations, device sizes, etc.) may translate to differences between each real world physical implementation of the reference voltage generator 200. For example, dopant concentration of transistors may fluctuate within manufacturing tolerances that may translate to differences in threshold voltages, which can impact the operation of the reference voltage generator 200. The process induced variations are characterized as a plurality of process corners for each electrical component, for example, a fast (F), slow (S), and typical (T) corner. Each device has its own corners, and when the components are combined into a single circuit the number of corners increases to cover all variations. For example, an n-channel MOSFET (nMOS) transistor may have F, S, and T corners and a p-channel MOSFET (pMOS) may also have a F, S, and T corners. Across both nMOS and pMOS there would be FF, FS, FT, SF, ST, SS, TT, TS, and TF corners. In the embodiments disclosed herein, there may be 15 process induced corners, and the reference voltage generator 200 is configured to generate an output voltage that is relatively stable across all 15 process corners.
The reference voltage generator 200 according to embodiments disclosed herein includes startup device(s) 210, current control devices 220, and reference voltage devices 230. The startup device(s) 210 (also referred to herein as a startup circuit) may include one or more electrical components configured to remove degenerate points within the reference voltage generator 200, as well as reduce startup time by decreasing time period of the reference voltage generator 200 to settle responsive to ramping up a supply voltage VDDQ. For example, the startup device(s) 210 may be coupled to the current control devices 220 and reference voltage generation devices 230 at a node. The startup device(s) 210 is configured to activated responsive to receiving the supply voltage VDDQ and operate to charge the node to a non-zero current (e.g., non-degenerate point). Once charged (e.g., the output voltage Vref stabilizes), the startup device(s) 210 is deactivated and draws minimal to zero current.
Without the startup device(s) 210, there are at least two points that the reference voltage generator 200 may stabilize such that the reference voltage generator 200 will operate as designed. Once such point is where all electrical components of the reference voltage generation devices 230 have a the same current, and the second where there is zero current passing in reference voltage generation devices 230. However, if the reference voltage generation devices 230 have zero current, then the reference voltage generator 200 would not output any voltage. This point of zero current is referred to herein as the degenerate point. Thus, the startup devices 210 function to force the current in the reference voltage generation devices 230 to the optimum point having non-zero current to ensure proper operation after the settling period.
The current control devices 220 (also referred to herein as a current control circuit) may include a plurality of electrical components, which are configured to feed current into the reference voltage generation devices 230. The current control devices 220 are configured to mirror the current at different nodes coupled to reference voltage generation devices 230 so that voltage levels at each node can be properly maintained.
The reference voltage generation devices 230 (also referred to herein as a reference voltage generation circuit) includes a plurality of electrical components configured to generate the stable DC output voltage Vref. For example, as will be described below, the reference voltage generation devices 230 comprises CMOS transistors, with one CMOS on a first branch of the reference voltage generation devices 230 and a second CMOS on a second branch of the reference voltage generation devices 230. The current control devices 220 function to ensure current in each of the first and second branches are approximately equal. The closer to equal, the better in terms of stable voltage generation. Furthermore, the CMOS transistors have dissimilar threshold voltages. For example, one CMOS transistor has a threshold voltage that is higher than the threshold voltage of the complimentary transistor. This dissimilarity in the threshold voltage, along with the mirroring of the current at each branch, causes the CMOS transistors to pass a current to an output node that is dependent on a difference between threshold voltages, which generates output voltage Vref that is dependent on resistance between the CMOS transistors and the output node and the passed current.
Accordingly, the reference voltage generator 200 provides various technical advantages over the conventional bandgap voltage reference circuits. For example, the reference voltage generator 200 does not use any BJTs, using CMOS transistors instead. Accordingly, embodiments disclosed herein are more compact (e.g., require less physical space) than the conventional bandgap voltage reference circuits. Additionally, embodiments disclosed herein exhibit less process induced variation, as MOSFETS are generally easier to produce and can be manufactured to tighter tolerance providing less variation between components. Furthermore, the embodiments disclosed herein operate at a minimum supply voltage that is substantially less than the supply voltage required by conventional bandgap voltage reference circuits. For example, as noted above, circuit 100 requires a minimum supply voltage of around 0.9 V (e.g., VBE2 of 0.7-0.8 V and VOV3 of 0.2 V to remain in the saturation region). Whereas, the embodiments herein require approximately 0.3 V less, because the supply voltage required to maintain saturation of the CMOS transistors may be approximately 0.4 V instead of 0.7-0.8 required by the BJTs.
Further still, the output reference Vref generated by reference voltage generator 200 may be tunable, such that a stable DC output voltage Vref may be generated at multiple different voltage levels that are respect to PVT variations. For example, because the reference voltage generator 200 is implemented using MOSFETs instead of BJTs, the dynamics temperature impacting the operation of the reference voltage generator 200 are based on a different physical properties and operating principles as compared to BJTs. The difference in temperature dynamics is discussed below with reference to Eq. 2-14.
Referring to
The current control devices 320 may be example circuitry for implementing current control devices 220 of
The startup devices 310 may be example circuitry for implementing startup devices 210 of
While the example implementation of the startup devices 310 includes one transistor M6, this is merely an illustrative example and other implementations are possible. For example, startup devices 310 and/or 210 may be implemented as a plurality of electrical devices such as transistors, resistors, capacitors, etc. However, such implementations may increase the size of the circuit thereby requiring increased on chip real-estate.
The reference voltage generation devices 330 may be example circuitry for implementing reference voltage generation devices 230 of
As an illustrative example, the first terminal of first resistor R1 may be directly coupled to node N2 and the second terminal of the first resistor R1 may be directly coupled to the drain terminal and gate terminal of transistor M1. Drain terminal and gate terminal of second transistor M2 may be directly coupled to node N3. Source terminals of transistors M1 and M2 may be directly coupled to each other and coupled to ground GND. The first terminal of second resistor R2 may be directly to the source terminals of transistors M1 and M2. Drain terminal of transistor M5 may be directly coupled to the second terminal of second resistor R2.
As described above with reference to
Referring now to
After the settling period, at block 410, the voltage at the gate terminal of transistor M4 is less than the supply voltage level VDDQ such that VSG of M4 is approximately 150 millivolts above its absolute threshold voltage. The gate terminal of transistor M6 is also brought down, which causes the VGS of transistor M6 to be reduced well below its threshold voltage, thereby turning transistor M6 OFF (e.g., deactivate). As such, after the settling period, negligible current flows through transistor M6 and the circuit 300 operates to generate a PVT insensitive output voltage, for example, as described in connection with
Referring now to
At block 504, the first and second transistors M1 and M2 are turned ON based on voltage levels at node N2 and node N3, respectively. For example, a voltage is applied to the gate terminal of transistor M1 that brings up the gate-to-source bias voltage of transistor M1 (VGS1) above its threshold voltage (Vth1), thereby turning the transistor M1 ON. Similarly, a voltage is applied to the gate terminal of transistor M2 that brings up the gate-to-source bias voltage of transistor M2 (VGS2) above its threshold voltage (Vth2), thereby turning the transistor M2 ON. Accordingly, as alluded to above, the minimum supply voltage VDDQ required for circuit 300 to operate is VGS2 plus VOV3 (e.g., overdrive voltage of transistor M3 to maintain transistors M3-M5 in saturation). VGS2 controls the minimum supply voltage because of the higher Vth2, thus a larger VGS2 (relative to VGS1) is required to ensure both transistors M1 and M2 are activated. Furthermore, while VOV3 is illustrated here, the minimum supply voltage could be based on VOV3, VOV4, or VOV5 because each of M3-M5 may have approximately the same physical properties (e.g., withing manufacturing tolerances), and would therefore have the same VOV. In an illustrative example, VGS2 may be 300 mV and VOV3 may be 200 mV as noted above.
At block 506, current at node N5 (e.g., current I5 at source terminals of transistors M1 and M2) is generated based on transistors M1 and M2 turning ON. The current at node N5 is determined based on VGS2 and VGS1, along with the resistance levels r1 and r2 of resistors R1 and R2, respectively. Furthermore, VGS2 of transistor M2 and VGS1 of transistor M1 are dependent on the current at nodes N3 and N2, respectively. For example, the current passing through transistor M2 in branch 340 from node N3 is applied to the drain and gate terminals of transistor M2. As a result, the voltage at the drain terminal of transistor M2 will be VGS2. Because the current at node N2 and node N3 are the same, the voltage at node N2 will be VGS2 and the voltage at node N3 will be VGS1. Thus, the voltage drop across resistor R1 is the difference between VGS2 and VGS1 and the curren I5 at node N5 will be the ratio of the difference of VGS2 and VGS1 over the resistance ri of resistor R1 (e.g., I5=(VGS2−VGS1/r1).
The current applied to the source terminal of transistor M5 is approximately the same as that at the source terminal of transistors M3 and M4. This condition flows from transistor M5 being substantially the same and having approximately the same physical properties (e.g., size, width, length, and threshold voltage) as transistors M3 and M4. As a result, at block 508, the voltage level generated at node N4 (e.g., at the second terminal of the resistor R2) will be the current I5 times the resistance r2 of resistor R2. Thus, the output voltage Vref is provided as follows:
Due to the threshold voltage of both transistors M1 and M2 having similar temperature dependency and resistors R2 and E1 having similar temperature dependency, the output voltage becomes temperature independent.
To achieve insensitivity to PVT variations, the derivative of the output voltage Vref with respect the temperature (Vref/δT) , which is dependent on VGS1 and VGS2, should be minimized. For example, to minimize the gradients, the partial derivative of Vref with respect to temperature (T) is forced to zero (e.g., δVref/δT=0), which means that the partial derivative of the difference between VGS1 and VGS2 (e.g., ΔVGS2,1) with respect to T is forced to zero (e.g., δΔVGS2,1/OT=0) and that/5 satisfies the following condition:
I
5
=I
0/(1+αRΔT) Eq. 2
Where I0 represents the current at room temperature (e.g., 27° C.), αR represents a temperature coefficient of the resistor R2, and ΔT represents the difference in temperature between the operating temperature of the circuit 300 (T) and room temperature (T0) (e.g., ΔT=T−T0).
Using square law approximation:
ΔVGS2,1=ΔVth2,1+√{square root over (2I5β2)}−√{square root over (2I5β1)}=ΔVth2,1+√{square root over (2I5)}(√{square root over (1/β2)}−√{square root over (1/β1)}) Eq. 3
Where ΔVth2,1 is the difference in threshold voltages of transistor M2 (Vth2) and transistor M1 (Vth1). As noted above, Vth2 is higher than Vth1. The coefficient β for each transistor M1 and M2 (e.g., β1 pond β2, respectively) is provided as:
βeff is a coefficient whose behavior with respect to temperature is shown in
ΔVGS2,1=ΔVth2,1+√{square root over (2I/βeff)}(√{square root over (L2/W2)}−√{square root over (L1/W1)}) Eq. 6
Where L1 and W1 are the length and width of transistor M1 and L2 and W2 are the length and width of transistor M2. By defining a variable N as follows:
N=√{square root over (2)}(√{square root over (L2/W2)}−√{square root over (L1/W1)}) Eq. 7
The difference in the gate-to-source bias voltage between transistor M2 and M1 is:
ΔVGS2,1=ΔVth2,1+N√{square root over (I/μnCox)} Eq. 8
Next temperature equations for MOSFETs can be substituted into Eq. 8 to obtain:
ΔVGS2,1=ΔVth0(1+αΔV
ΔVGS2,1=ΔVth0(1+αΔV
Where a αΔV
Using Taylor expansion series and neglecting the second order terms, the temperature dependent factor in the second term simplifiers to:
Second order terms are neglected in Eq. 11 because they do not impact the analysis in a significant way, and removing them simplifies the analysis.
Eq. 11 is validated by the simulation data graphically shown in
Where ΔVth0 is the difference in threshold voltage between M2 and M1 at room temperature and βeff,0 is the βeff at room temperature. To obtain a zero TC, Eq. 12 is set to 0 as follows:
Furthermore,
I
0=(ΔVth0+N√{square root over (I0/βeff,0))}/r10 Eq. 14
Accordingly, the zero TC condition parameters of circuit 300 can be obtained by solving Eqs. 13 and 14. For example, Eqs. 13 and 14 can be solved for N and r10. A pair of N and r10 that satisfy Eqs. 13 and 14 may lead to zero TC conditions, where an optimum N facilitates selecting sizes of transistors M1 and M2 and r10 sets the resistance value of resistor R1.
ΔVth2,1=ΔVth0(1+αΔV
Where αΔV
βeff=βeff,0(1+αμΔT) Eq. 16
Where Eq. 5 can be modeled as Eq. 15, αμ is 4606×10−61/° C. and βeff,0 is 707 μA/V2.
ρ=√{square root over (1/βeff)}=ρ0(1+αρΔT) Eq. 16
Where αρ is 2106×10−61/° C. and ρ0 is the variable ρ at room temperature and is 109 millivolts.
As shown in
Similarly,
For example,
Thus, as shown in
Table 1 below compares the embodiments of the disclosed technology in column 8 against comparative examples 1-7 of conventional voltage refence generating circuits. Table 1 provides a type of voltage refence generating circuit, which indicates whether the circuit implements BJTs or CMOS. As shown in Table 1, embodiments disclosed herein provide for a larger range of temperature (e.g., −40 to 140° C.) across which output voltage is relatively stable, e.g., TC is a maximum (μ) of 59 ppm/° C. with a standard deviation (δ ) of 7 ppm/° C. These TC results are achieved by the embodiment disclosed herein while also providing an adjustable reference voltage, which none of the conventional circuits provide.
Furthermore, the TC results are achieved without trimming, for example, by calibrating the circuit for process variations. For example, while conventional circuit of example 7 achieves a maximum TC of 4 ppm/° C., example 7 requires trimming of the circuit in order to achieve this result. Additionally, the temperature range over which the TC was achieved by example 7 is smaller than that provided by the embodiments disclosed herein (e.g., −40° C. to 125° C.). While the embodiments herein do not require trimming or calibration to achieve the results shown in Table 1 (or
As alluded to in connection with
Additionally, embodiments disclosed herein are capable of accounting for any lingering process induced variations. For example, with reference to
The first stage reference generator 1202 may be implemented, for example, as the reference voltage generator 200. For example, circuit 300 or circuit 1000 may be example circuit implementations of the first stage reference generator 1202. Thus, for example, the supply voltage VDDQ may be coupled to source terminals M3-M5 of circuit 300 or circuit 1000, and the output voltage from node N4 from circuit 300 or circuit 1000 may be supplied to positive terminal of operational amplifier 1204.
Similarly, the second stage reference generator 1206 may be implemented, for example, as the reference voltage generator 200. That is the second stage reference generator 1206 may be identical to the first stage reference generator 1202. For example, circuit 300 or circuit 1000 may be example circuit implementations of the second stage reference generator 1206. Thus, for example, the output Vx from the operational amplifier 1204 may be coupled to source terminals M3-M5 of circuit 300 or circuit 1000 (e.g., in place of supply voltage VDDQ), and the output voltage from node N4 from circuit 300 or circuit 1000 may be the output voltage Vref.
Accordingly, the first stage reference generator 1202 generates a relatively stable output voltage, as described above, which is supplied to the operational amplifier 1204. The operational amplifier 1204 functions to include the voltage output from the first stage reference generator 1202, and supply the amplified voltage Vx to the second stage reference generator 1206, for example, as the input thereto. The stage reference generator 1206 then generates an output voltage Vref, which increases the stability of the output voltage (e.g., increases the insensitivity to PVT variations). For example, the total sensitivity of circuit 1200 is the sensitivity of the first stage reference generator 1202 (e.g., δVx/δVDDQ) multiplied by the sensitivity of the second stage reference generator 1206 (e.g., δVref/δVx), which results in very low line sensitivity to PVT variations (as shown below in Table 2 and described in connection with
Along with increased reference voltage stability, circuit 1200 provides for additional technical advantages, such as low supply voltage requirements and ease of design. For example, circuit 1200 does not require adding Cascode devices (e.g., placing transistors on top of each other), which cannot operate at low supply voltages. Thus, low supply voltage operation (e.g., minimum supply voltage is VGS2+VOV3) is achieved, in part, by not using Cascode devices. Furthermore, circuit 1200 can be simple to design once one of stages 1202 or 1206 are designed. That is, once one stage is designed, the design can be repeated for the second stage giving two identical stages.
As shown in
Similarly,
Accordingly, the two-stage reference voltage generator of
Table 2 below compares the two-stage reference voltage generator of
In the depicted embodiment, the computing device 1510 includes a processor 1515, a memory 1530, and storage 1540. In various embodiments, a processor 1515 may refer to any electronic element that carries out the arithmetic or logical operations performed by the computing device 1510. For example, in one embodiment, the processor 1515 may be a general-purpose processor that executes stored program code. In another embodiment, a processor 1515 may be a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), or the like, that operates on data stored by the memory 1530 and/or the storage 1540. In a certain embodiment, a processor 1515 may be a controller for a storage device (e.g., on a storage area network), a networking device, or the like.
In the depicted embodiment, the processor 1515 includes a cache 1520. In various embodiments, a cache 1520 may store data for use by the processor 1515. In certain embodiments, a cache 1520 may be smaller and faster than the memory 1530, and may duplicate data in frequently-used locations of the memory 1530, or the like. In certain embodiments, a processor 1515 may include a plurality of caches 1520. In various embodiments, a cache 1520 may include one or more types of memory media for storing data, such as static random access memory (SRAM) 1522, three-dimensional memory 1550, or the like. For example, in one embodiment, a cache 1520 may include SRAM 1522. In another embodiment, a cache 1520 may include three-dimensional memory 1550. In a certain embodiment, a cache 1520 may include a combination of SRAM 1522, three-dimensional memory 1550, and/or other memory media types.
The memory 1530, in one embodiment, is coupled to the processor 1515 by a memory bus 1535. In certain embodiments, the memory 1530 may store data that is directly addressable by the processor 1515. In various embodiments, a memory 1530 may include one or more types of memory media for storing data, such as dynamic random access memory (DRAM) 1532, three-dimensional memory 1550, or the like. For example, in one embodiment, a memory 1530 may include DRAM 1532. In another embodiment, a memory 1530 may include three-dimensional memory 1550. In a certain embodiment, a memory 1530 may include a combination of DRAM 1532, three-dimensional memory 1550, and/or other memory media types.
The storage 1540, in one embodiment, is coupled to the processor 1515 by a storage bus 1545. In certain embodiments, the storage bus 1545 may be a peripheral bus of the computing device 1510, such as a peripheral component interconnect express (PCI Express or PCIe) bus, a serial Advanced Technology Attachment (SATA) bus, a parallel Advanced Technology Attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like. In various embodiments, the storage 1540 may store data that is not directly addressable by the processor 1515, but that may be accessed via one or more storage controllers. In certain embodiments, the storage 1540 may be larger than the memory 1530. In various embodiments, a storage 1540 may include one or more types of storage media for storing data, such as a hard disk drive, NAND flash memory 1542, three-dimensional memory 1550, or the like. For example, in one embodiment, a storage 1540 may include NAND flash memory 1542. In another embodiment, a storage 1540 may include three-dimensional memory 1550. In a certain embodiment, a storage 1540 may include a combination of NAND flash memory 1542, three-dimensional memory 1550, and/or other storage media types.
In various embodiments, three-dimensional memory 1550 may be used to store data in a cache 1520, memory 1530, storage 1540, and/or another component that stores data. For example, in the depicted embodiment, the computing device 1510 includes three-dimensional memory 1550 in the cache 1520, memory 1530, and storage 1540. In another embodiment, a computing device 1510 may use three-dimensional memory 1550 for memory 1530, and may use other types of memory or storage media for cache 1520 or storage 1540. Conversely, in another embodiment, a computing device 1510 may use three-dimensional memory 1550 for storage 1540, and may use other types of memory media for cache 1520 and memory 1530. Additionally, some types of computing device 1510 may include memory 1530 without storage 1540 (e.g., in a microcontroller) if the memory 1530 is non-volatile, may include memory 1530 without a cache 1520 for specialized processors 1515, or the like. Various combinations of cache 1520, memory 1530, and/or storage 1540, and uses of three-dimensional memory 1550 for cache 1520, memory 1530, storage 1540, and/or other applications will be clear in view of this disclosure.
In various embodiments, the three-dimensional memory 1550 may include one or more chips, packages, die, or other integrated circuit devices comprising three-dimensional memory arrays with multiple layers of memory cells, disposed on one or more printed circuit boards, storage housings, and/or other mechanical and/or electrical support structures. For example, one or more dual inline memory modules (DIMMs), one or more expansion cards and/or daughter cards, a solid-state-drive (SSD) or other storage device, and/or another memory and/or storage form factor may comprise the three-dimensional memory 1550. The three-dimensional memory 1550 may be integrated with and/or mounted on a motherboard of the computing device 1510, installed in a port and/or slot of the computing device 1510, installed on a different computing device 1510 and/or a dedicated storage appliance on a network, in communication with a computing device 1510 over an external bus, or the like.
The three-dimensional memory 1550, in various embodiments, may include one or more memory dies. A memory die may include multiple layers of memory cells in a three-dimensional memory array. In various embodiments, three-dimensional memory may include magnetoresistive RAM (MRAM), phase change memory (PCM), resistive RAM (ReRAM), NOR Flash memory, NAND Flash memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory, or the like.
In certain embodiments, the three-dimensional memory 1550 may include a plurality of planar memory cells forming a three-dimensional array, a plurality of word lines extending horizontally across the layers (e.g., in-plane), and a plurality of selector columns or pillars extending vertically through the plurality of layers. In further embodiments, the selector columns or pillars may be coupled to the memory cells, and may include central conductors surrounded by one or more concentric selective layers. In various embodiments, one or more selective layers may permit an electrical current through a cell, between a word line and a central conductor, in response to a voltage satisfying a threshold. In certain embodiments, a selector column or pillar that extends through a plurality of layers of planar memory cells may facilitate reading to or writing from individual memory cells by limiting leakage current through other cells. Additionally, in further embodiments, forming a selector pillar or column that extends through a plurality of layers may simplify manufacturing compared to forming selector devices in individual layers alternating with memory cell layers.
Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, or the like) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module,” “apparatus,” or “system.” Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer readable storage media storing computer readable and/or executable program code.
Many of the functional units described in this specification have been labeled as modules, in order to more particularly emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like.
Modules may also be implemented at least partially in software for execution by various types of processors. An identified module of executable code may, for instance, comprise one or more physical or logical blocks of computer instructions which may, for instance, be organized as an object, procedure, or function. Nevertheless, the executables of an identified module need not be physically located together, but may comprise disparate instructions stored in different locations which, when joined logically together, comprise the module and achieve the stated purpose for the module.
Indeed, a module of executable code may include a single instruction, or many instructions, and may even be distributed over several different code segments, among different programs, across several memory devices, or the like. Where a module or portions of a module are implemented in software, the software portions may be stored on one or more computer readable and/or executable storage media. Any combination of one or more computer readable storage media may be utilized. A computer readable storage medium may include, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing, but would not include propagating signals. In the context of this document, a computer readable and/or executable storage medium may be any tangible and/or non-transitory medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, processor, or device.
Computer program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Python, Java, Smalltalk, C++, C#, Objective C, or the like, conventional procedural programming languages, such as the “C” programming language, scripting programming languages, and/or other similar programming languages. The program code may execute partly or entirely on one or more of a user's computer and/or on a remote computer or server over a data network or the like.
A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as a hardware logic circuit comprising custom VLSI circuits, gate arrays, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain embodiments, may alternatively be embodied by or implemented as a component.
A circuit, as used herein, comprises a set of one or more electrical and/or electronic components providing one or more pathways for electrical current. In certain embodiments, a circuit may include a return pathway for electrical current, so that the circuit is a closed loop. In another embodiment, however, a set of components that does not include a return pathway for electrical current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return pathway for electrical current) or not. In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and/or electrical components with or without integrated circuit devices, or the like. In one embodiment, a circuit may include custom VLSI circuits, gate arrays, logic circuits, or other integrated circuits; off-the-shelf semiconductors such as logic chips, transistors, or other discrete devices; and/or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as field programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, a netlist, or the like). A circuit may comprise one or more silicon integrated circuit devices (e.g., chips, die, die planes, packages) or other discrete electrical devices, in electrical communication with one or more other components through electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein, in certain embodiments, may be embodied by or implemented as a circuit.
Reference throughout this specification to “one embodiment,” “an embodiment,” or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” and similar language throughout this specification may, but do not necessarily, all refer to the same embodiment, but mean “one or more but not all embodiments” unless expressly specified otherwise. The terms “including,” “comprising,” “having,” and variations thereof mean “including but not limited to” unless expressly specified otherwise. An enumerated listing of items does not imply that any or all of the items are mutually exclusive and/or mutually inclusive, unless expressly specified otherwise. The terms “a,” “an,” and “the” also refer to “one or more” unless expressly specified otherwise.
Aspects of the present disclosure are described below with reference to schematic flowchart diagrams and/or schematic block diagrams of methods, apparatuses, systems, and computer program products according to embodiments of the disclosure. It will be understood that each block of the schematic flowchart diagrams and/or schematic block diagrams, and combinations of blocks in the schematic flowchart diagrams and/or schematic block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor or other programmable data processing apparatus, create means for implementing the functions and/or acts specified in the schematic flowchart diagrams and/or schematic block diagrams block or blocks.
It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. Other steps and methods may be conceived that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures. Although various arrow types and line types may be employed in the flowchart and/or block diagrams, they are understood not to limit the scope of the corresponding embodiments. For instance, an arrow may indicate a waiting or monitoring period of unspecified duration between enumerated steps of the depicted embodiment.
In the following detailed description, reference is made to the accompanying drawings, which form a part thereof. The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of proceeding figures. Like numbers may refer to like elements in the figures, including alternate embodiments of like elements.
