Certain example embodiments are described below in conjunction with the appended drawing figures, wherein like reference numerals refer to like elements in the various figures, and wherein:
In one form or another, the various embodiments describe a low-loss optical device structure and method of fabrication. The method includes forming a cladding region that is below an optical device and adjacent to a buried oxide region of an SOI substrate. The described cladding region compensates for a thin BOX layer. Thus, the combination of a BOX layer and the cladding region is a structure that serves as the bottom cladding of an optical device, such as a waveguide, for example.
Overall, the optical device structures described below are implemented in a variety of conventional semiconductor processes and combinations thereof, which include: lithography, etching, thin-film deposition, and anti-reflective coatings.
For simplicity, the description below and related figures describe an optical device structure that includes a silicon-based waveguide that comprises a single crystalline silicon layer. In alternative examples, however, the described cladding region may be used to reduce optical losses in a variety of optical devices and is not limited to one particular type of optical device or optical coupling arrangement. For example, the described cladding region may be used to reduce optical losses in devices such as splitters, mirrors, gratings, resonators and modulators.
It should also be understood that the illustrated optical elements described below may comprise various materials and multiple layers with specific characteristics for each individual layer (i.e., doping, thickness, resistivity, etc.). The thickness of a waveguide, for example, may be tailored to accommodate one or more modes of a propagating light beam. In addition, although the described embodiments below use silicon-based optical elements, other types of high index materials (i.e., gallium arsenide, lithium niobate, indium phosphide, etc.) may replace silicon-based elements. Further, unless stated otherwise, the illustrated elements may take on a variety of shapes and sizes.
Turning now to the figures,
The BOX layer 14 may serve a variety of purposes. For example, The BOX layer 14 provides electrical isolation to microelectronic devices, such as a FET 19. The BOX layer 14 also promotes optical confinement within the waveguide 18.
In addition, the BOX layer 14 may also serve as an evanescent coupling between a top side and a bottom side of the SOI substrate 10. For example, to introduce a light beam into the waveguide 18 or draw light out of the waveguide 18, the BOX layer 14 serves as a spacer. As a spacer, the BOX layer 14 accurately sets a distance between a prism 20 and the waveguide 18 and as a result, enables efficient and repeatable coupling of light into and out of the waveguide 18.
To act as a spacer and also to prevent wafer bowing during fabrication, the BOX layer 14 should be less than about 2500 Angstroms or less in thickness. However, to clad the waveguide 18 and thus efficiently guide the light beam, the waveguide 18 should be surrounded by cladding layers that have a low index and sufficient thickness. To clad the top of the waveguide 18, an oxide layer 26 is grown or thermally deposited above the waveguide 18. In one example, the thickness of the oxide layer 26 should be about 1 um or more.
However, to clad the bottom of the waveguide 18, a BOX layer 14 may not be sufficient in adequately confining a light beam within the waveguide 18. Therefore, a cladding region 24 is formed below the waveguide 18. In general, the cladding region 24 serves to increase the cladding thickness of the BOX layer 14. Preferably the cladding region 24 is an air cavity, which inherently has a low index of refraction. However, the cladding region 24 may also be filled with a dielectric material such as an oxide, nitride, polymer film, or combination thereof. More detail with respect to filling the cladding region will be described with reference to
To prevent losses within the waveguide 42, the cavity 48 serves as a cladding region. Preferably the cavity 48 is an air cavity or is a cavity that is filled or at least partially filled with a dielectric material. The dielectric material should have continuous refractive index that is less than the refractive index of the waveguide 42 and less than or equal to the refractive index of a BOX layer. In addition, to promote optical confinement, it is preferable that the cavity 48 has a width 50 that is greater than a width 52 of the waveguide 42. The cavity 48, for example, may be patterned and etched so that the cavity 48 sufficiently overlaps the waveguide 42 and a portion of the substrate 40.
Alternatively, a groove or a trench may be formed in lieu of a cavity.
Generally speaking, the cladding region 24 may be created in a variety of ways, preferably by a lithography process in combination with an etching step (i.e., a wet or dry etch).
At block 70, an SOI substrate is provided. At block 72, a hard masking layer is deposited on the bulk layer of the bottom side of the SOI substrate. The hard masking layer, for example, may be silicon nitride. At block 74 a photoresist masking layer is deposited over the hard masking layer. At block 76, a mask is aligned to a front side of the SOI substrate and the mask is used to pattern the photoresist masking layer. As described above, a cladding region should be aligned underneath the optical device that is to be cladded. In addition, the cladding region should be aligned so that the cladding region is wider than the device that is to be cladded. For example, the cladding region should be designed to be wider than an optical device region, where the optical device region represents an area where an optical device is or will be located.
To align the cladding region, a mask aligner (e.g. a stepper) may use a camera, for example, to align a mask to features on the top side of the SOI substrate. The cladding region may be aligned with the device itself or various other features on the front side of the SOI substrate. Other methods of alignment, besides a camera, include using an IR source to detect and align front side features with a bottom side mask. In such examples, alignment marks, which can be recognized by the mask aligner, may be patterned into an appropriate layer of the device to enable registration of a backside pattern to a front side (or vice versa).
At block 78, the cavity and/or trench pattern is transferred into the hard masking layer via a wet or dry chemical etch, for example. At block 80, a wet or dry chemical etch process may be used to transfer the cavity and/or trench pattern into the bulk layer. The cavity and/or trench may be etched until the BOX layer is exposed. Alternatively, the etch process may be tailored so that a thin portion of silicon remains between the BOX layer and the cavity and/or trench. This remaining silicon may be subsequently oxidized and thus fill the cavity and/or trench with a thermal oxide (described further with reference to
Because the bulk layer may be substantially thick (i.e., on the order of a hundreds of μm), the hard mask may ensure that the photoresist masking layer does not break down during the pattern transfer into the bulk layer. Thus, the etching processes shown at blocks 78, 80 may be one continuous etch step, or a two-step etch process. It should also be understood that the hardmasking layer may not be necessary. For example, the photoresist may be durable enough to remain intact during pattern transfer into the bulk layer.
The photoresist masking layer may be removed during or after the etch process at block 78, or after the etch process at block 80. The photoresist masking layer may be removed by a plasma ash and/or a wet clean, for example. The hard mask layer may be removed by a chemical HF (hydrofluoric acid) or hot phosphoric etch. The type of hard mask strip may depend on the type of hard mask layer that is used.
As described above, a cladding region may be filled or partially filled with a dielectric material. The dielectric material may be used to tailor the index of refraction of the cladding region to a particular optical device or application.
At block 82, a cavity or trench to be filled is provided. At block 84, the cavity and/or trench is filled with a dielectric material. For example, a chemical vapor deposition (CVD) or a plasma enhanced CVD (PECVD) process may be used to deposit an oxide layer and completely fill or at least partially fill the cavity and/or trench.
It should also be understood that a thermal diffusion process may also be used to grow a dielectric layer within the cavity and/or trench. The dielectric layer may be grown to a preferred thickness that completely fills or at least partially fills the cavity and/or trench. Also, as described above, the cavity and/or trench may include a remaining amount of silicon. This silicon may be oxidized during a wet or dry oxidation, for example. It may be preferable, in some examples, to perform high temperature dielectric deposition steps prior to the formation of microelectronic devices as such temperatures may affect the diffusion profiles of these devices.
As mentioned above, a variety of optical devices may be mounted to the bottom side of an SOI substrate. Thus, a cavity and/or trench may be tailored to accommodate such a mounting.
Generally speaking, the cladding region allows thinner BOX layers to be used in optoelectronic IC processing and design layout. For example, BOX layers having a thickness that is less than 2500 Angstroms may be used for electrical isolation. Nevertheless, the cladding region insures that optoelectronic devices are adequately cladded.
It should be understood, however, that the illustrated examples and related description are examples only and should not be taken as limiting the scope of the present invention. The methods and structures described above are not limited to a particular type of optical device. Other optical devices may be cladded via the method described above. Moreover, although the disclosure uses a silicon based substrates, a variety of other semiconductor substrates and films may be used instead of silicon and silicon dioxide, such as GaAs, GaN, or InP, for example. In addition, the indexes of any of the above films may be tailored. For example, a cavity may be filled with a dielectric material that has a preferred index of refraction. The claims should not be read as limited to the described order or elements unless stated to that effect. Therefore, all embodiments that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.
The present application claims priority to U.S. patent application Ser. No. 11/412,738, entitled “Optical Coupling Structure,” filed Apr. 27, 2006, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | |
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Parent | 11412738 | Apr 2006 | US |
Child | 11557185 | US |