Patent Application
20250167736
The present application is a non-provisional patent application claiming priority to EP 23210737.5, filed on Nov. 17, 2023, the contents of which are hereby incorporated by reference.
The present disclosure generally relates to a low-noise amplifier, LNA, circuitry.
Low-noise amplifier, LNA, circuitries provide amplification while minimising additional noise introduced during amplification. They process noisy signals, often having a low amplitude, with minimal further noise contributions to the signal. Applications comprise amplifying wireless incoming signals captured by a receiver antenna, for example, in radio frequency integrated circuits, RFIC.
Low-noise amplifiers may be implemented in complementary metal oxide semiconductor, CMOS, technology, for achieving a low power consumption. As CMOS evolves to smaller transistor sizes and lower supply voltages, it may become a challenge to provide low-noise amplifiers while maintaining required biasing and linearity of transistors.
It is an object of the disclosure to provide a low-noise amplifier circuitry that alleviates one or more of the abovementioned obstacles.
According to some aspects, there is provided the subject matter of the independent claim. Some further aspects are defined in the dependent claims.
According to a first example aspect, the object of the disclosure is achieved by providing a low-noise amplifier, LNA, circuitry for amplifying an input signal at an input to an output signal at an output. The circuitry comprises a first cascode amplifier and a second complementary cascode amplifier, respectively connected to a first load and a second load. The first load and the second load are coupled and the output signal is an output of the first or second cascode amplifier. The first cascode amplifier comprises a first initial amplification stage and a first transistor. The first initial amplification stage is connected to the input and to a lower power supply node. The first transistor is arranged in a common-gate configuration, in cascode with the first initial amplification stage and connected to the first load. The second cascode amplifier comprises a second initial amplification stage and a second transistor. The second initial amplification stage is connected to the input and to a higher power supply node. The second transistor is arranged in a common-gate configuration, in cascode with the second initial amplification stage and connected to the second load. Further, inputs of the first and second transistors are capacitively coupled such that the first and second transistors are connected at frequencies higher than a frequency characterising the capacitive coupling.
The first cascode amplifier and the second cascode amplifier are arranged as two complementary sub-circuitries that are coupled via their respective end loads in order to provide a single output. The capacitive coupling provides a direct link between internal nodes of the first and second cascode amplifiers. In particular, the capacitive coupling provides a short circuit for alternating current, AC, and an open circuit for direct current, DC, between the inputs of the first transistor and of the second transistor. Thus, the LNA circuitry behaves the same in DC as it would without the capacitive coupling, yet provides an additional interconnection between internal nodes of the first and second cascode amplifiers for AC signals.
The common-gate configuration provides small input impedance, which is desirable for LNA circuitries to achieve wide bandwidth. Furthermore, a complementary set-up is beneficial for reducing distortion, or, in other words, non-linearity due to the symmetry it introduces into the circuitry. By providing complementary paths, higher order harmonics of signals may be cancelled out. On the other hand, stacking transistors requires an increased supply voltage in order to enable biasing of the transistors in the proper operating region. By directing the complementary cascode amplifiers along separate paths, stacking of threshold voltages is avoided thereby keeping the required supply voltage low. To provide a single output, the cascode amplifier branches are combined via an indirect coupling of the first and second loads, while preserving the lower necessary voltage supply. This way, linearity benefits resulting from symmetry still occur, even though the symmetry may no longer be ideally present by separating the cascode amplifier branches. In addition, biasing is an issue due to an evolution of electronics technology towards lower power consumption and therefore lower power supplies. Circuitries may be supplied with increasingly lower DC voltages. By providing the two separate branches without stacking the transistors, the challenge of operating at a low DC voltage may be overcome.
The DC-problem, i.e. the biasing problem, and the AC-problem of non-linearity are two crucial issues for LNA circuitries. By providing the capacitive coupling between the inputs of the first transistor and of the second transistor, both issues are addressed. Since the capacitive coupling functions as an open circuit in DC, the separate cascode amplifier branches remain separate in DC, resulting in a low necessary voltage supply. In AC, the capacitive coupling functions as a short circuit, resulting in a cancelling of distortion components, due to symmetry of the circuit branches in AC, and greatly improving linearity of the LNA circuitry. Thus, introducing the capacitive coupling ensures keeping a low required bias and power supply while removing non-linear effects such as intermodulation distortion or harmonic distortion.
According to an embodiment, the first and second transistors are configured to operate in a strong saturation region.
Transistors may exhibit a different behaviour depending on its biasing, i.e. the DC voltage supplied across the different terminals of the transistor. These different dependencies between transistor parameters are described by defining regions in transistor characteristics curves, such that the behaviour in a region can be captured by a single equation. In the strong saturation region, the current flowing through a transistor is linearly depending on a biasing voltage, e.g. a voltage between the drain terminal and the source terminal of a metal oxide semiconductor field effect transistor, MOSFET. The linear dependence in the strong saturation region has a relatively small slope, i.e. significantly smaller than in the ohmic region, sometimes also referred to as the linear region or triode mode. The strong saturation region may also be referred to as saturation region or active region.
By biasing the first transistor and the second transistor in the strong saturation region, a stable and correct functioning of the LNA circuitry is ensured.
According to further embodiments, the first and second transistors respectively comprise a first gate terminal and a second gate terminal; the first gate terminal is connected to the higher power supply; and the second gate terminal is connected to the lower power supply.
For example, the first transistor may be an N-channel metal oxide semiconductor, NMOS, transistor and the second transistor may be a P-channel metal oxide semiconductor, PMOS, transistor. By connecting the gate terminals to the power supply, the first transistor and the second transistor are arranged in a common-gate configuration.
According to an example embodiment, the first and second initial amplification stages each comprise a transistor, arranged in a common-source configuration.
A transistor arranged in a common-source configuration provides a relatively high gain in comparison to other topologies. As such, the first initial amplification stage and the second initial amplification stage may provide an effective initial amplification of the input signal, before passing the signal to the first transistor and the second transistor respectively. For LNA applications, it may be effective to provide a sufficient amplification of the input signal, as it may have a relatively small amplitude.
According to an embodiment, the LNA circuitry further comprises a first and a second pre-amplifier configured to pre-amplify the input signal and provide the so obtained pre-amplified input signal to the inputs of the first and second transistors respectively.
By providing pre-amplification of the input signal before passing through the first and second initial amplification stages, a further amplification may be achieved, which is especially useful for input signals having a small amplitude. In addition, by providing a symmetric pre-amplification to the two cascode amplifier sections, the linearising effect of the capacitive coupling is further enhanced. This linearity improvement is caused by the additional AC path provided by the capacitive coupling, connecting the pre-amplifier outputs and thereby allowing a compensation of non-linear signal components to occur.
According to further example embodiments, the first and second loads each comprise an inductive coil.
The inductive coils may be arranged compactly on an integrated circuit.
According to further example embodiments, the coils are inductively coupled, thereby coupling the first and second loads.
By inductively coupling the first load and the second load, a transformer is realised at the output. Accordingly, second order non-linear signal components on the outputs of the first and second common-gate transistors are cancelled out by the inductive coupling. Additionally, by combining the first and second loads via an indirect inductive coupling, the cascode amplifiers are kept along separate branches and are not stacked on top of each other. This ensures that the biasing requiring only a low power supply is not compromised.
According to further example embodiments, the coils are capacitively coupled, thereby coupling the first and second loads.
By capacitively coupling the coils, the result of both cascode amplifiers is combined without comprising the separate low power DC biasing, since a capacitive coupling behaves as an open circuit in DC.
According to further example embodiments, the first and second loads each comprise a capacitor.
Applying a capacitor allows to fix a desired filtering behaviour of the first load and the second load, depending on the capacitor's capacitance.
According to further example embodiments, the first and second loads are capacitively coupled.
By capacitively coupling the first load with the second load, the result of both cascode amplifiers is combined without comprising the separate low power DC biasing, since a capacitive coupling behaves as an open circuit in DC.
According to further example embodiments, the LNA circuitry further comprises a coupling capacitor for providing the capacitive coupling.
By placing a capacitor, the capacitor's capacitance fixes the filtering behaviour of the first load and the second load, wherein the capacitance is a design parameter.
According to further example embodiments, the LNA circuitry further comprises an output amplifier, wherein the output signal is further applied to the output amplifier, thereby cascading the first and second cascode amplifiers with the output amplifier.
By further providing an output amplification stage, a useful part of the input signal may be provided for further processing. The output amplifier can be seen as an additional stage cascaded to the cascode amplifiers' output. It is noted that there is a significant difference between the term ‘cascode’, referring to the stacking of transistors along a configuration in series, and the term ‘cascade’. ‘Cascading’ refers to providing subsequent sub-circuitries or stages, usually designed to perform a certain operation, wherein signals are passed from one stage to another. These stages fulfil a certain functionality and may be independent electronic building blocks.
According to an embodiment, the output amplifier comprises an output transistor, arranged in a common-source configuration and connected to an output load.
The common-source configuration is suited for providing amplification due to its inherent property of providing a high gain. By providing a single common-source connected amplifier as the output amplifier, it may be compactly realised.
According to further embodiments, the output signal is the output of the first cascode amplifier and the output transistor is an N-channel metal oxide semiconductor, NMOS, transistor.
According to further embodiments, the output signal is the output of the second cascode amplifier and the output transistor is a P-channel metal oxide semiconductor, PMOS, transistor.
Due to the structure of the LNA circuitry, either of the first and the second cascode amplifier outputs may be utilised as the output signal. Accordingly, when taking the output signal as the output of the first cascode amplifier, the resulting N-channel MOS output transistor may provide a faster operation since electrons are known to propagate faster than holes.
The above, as well as additional, features will be better understood through the following illustrative and non-limiting detailed description of example embodiments, with reference to the appended drawings.
All the figures are schematic, not necessarily to scale, and generally only show parts which are necessary to elucidate example embodiments, wherein other parts may be omitted or merely suggested.
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. That which is encompassed by the claims may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided by way of example. Furthermore, like numbers refer to the same or similar elements or components throughout.
Low-noise amplifier, LNA, circuitries may be used for amplifying signals obtained from an antenna at a receiving side, e.g. in RFIC. RFIC refers to the field of generating and processing electromagnetic waves in the radio spectrum. The radio spectrum is often referred to as including radio waves, microwaves and infrared waves and may, for example, be defined between 3 hertz, Hz, and 3 terahertz, THz or even more. Examples of radio frequency applications comprise telecommunications, radio broadcasting and satellite navigation.
In the present disclosure, a transistor is described to have a source terminal, a gate terminal, and a drain terminal, according to field-effect transistor, FET, terminology. Since the issues concerning LNA circuitries are inherently tied to low-power signals, FET technology, e.g. complementary metal oxide semiconductor, CMOS, technology, lends itself to the purpose and may be used for LNA circuitries. Apart from FET transistors, other types of transistors may also be used, e.g. bipolar junction transistors. Using other transistor technologies, the terms ‘source’, ‘gate’ and ‘drain’ may be replaced by their corresponding terms, e.g., ‘emitter’, ‘base’ and ‘collector’ respectively in the case of bipolar junction transistors.
In
In
Further, the LNA circuitry 100 comprises a capacitive coupling 60 between the source terminals 31, 41 of the first and second transistors 30, 40. The LNA circuitry 100 also comprises a power supply (not shown) having two nodes or contacts: a lower power supply node and a higher power supply node, e.g. a negative and a positive node respectively. The power supply may, for example, be a voltage power supply providing a voltage difference of 0.8V.
A first cascode amplifier 400 comprises an initial amplification stage 10, which, for example, may comprise an initial transistor 10 arranged in a common-source configuration, as illustrated in
Further, the cascode amplifier 400 comprises a transistor 30. In
Further, it is noted that the term ‘cascode amplifier’ refers here to an amplifier comprising at least a transistor 30 that is arranged in a common gate configuration, wherein the transistor 30 is further connected in cascode, also referred to as in series, with a further amplification stage. The further amplification stage may, for example, comprise another transistor 10, as in the example of
The second cascode amplifier 500 of the other branch is complementary to the cascode amplifier 400. For example, as shown in
The inputs, i.e. source terminals 31, 41, of the transistors 30, 40 are capacitively coupled by a capacitor 60. The impedance of the capacitor 60 equals 1/(i*ω*C) with i the imaginary unit, C the capacitance of capacitor 60 and ω the angular frequency. Thus, depending on the frequency of the signal applied to the nodes of the capacitor 60, the impedance of capacitor 60 alters. For DC signals, the angular frequency equals zero and the capacitor 60 acts as an open circuit. The capacitor 60 does, however, allow AC signals to pass through as a function of the frequency components. The capacitance C determines the frequency characterising the capacitor 60. The capacitance C depends on the sizing of capacitor 60. The dimensions of capacitor 60, e.g. a capacitor area, thereby determine the frequency characterising the capacitive coupling. The capacitor 60 may be dimensioned such that the capacitor 60 behaves as a short circuit at a desired frequency of operation.
The same reference numerals as in
As used in this application, the term “circuitry” may refer to one or more or all of the following: (a) hardware-only circuit implementations (such as implementations in only analog and/or digital circuitry) and (b) combinations of hardware circuits and software, such as (as applicable): (i) a combination of analog and/or digital hardware circuit(s) with software/firmware and (ii) any portions of hardware processor(s) with software (including digital signal processor(s)), software, and memory(ies) that work together to cause an apparatus, such as a mobile phone or server, to perform various functions) and I hardware circuit(s) and or processor(s), such as a microprocessor(s) or a portion of a microprocessor(s), that requires software (e.g., firmware) for operation, but the software may not be present when it is not needed for operation.” This definition of circuitry applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term circuitry also covers an implementation of merely a hardware circuit or processor (or multiple processors) or portion of a hardware circuit or processor and its (or their) accompanying software and/or firmware. The term circuitry also covers, for example and if applicable to the particular claim element, a baseband integrated circuit or processor integrated circuit for a mobile device or a similar integrated circuit in server, a cellular network device, or other computing or network device.
Although the present disclosure has been illustrated by reference to specific embodiments, it will be apparent to those skilled in the art that the disclosure is not limited to the details of the foregoing illustrative embodiments, and that the present disclosure may be embodied with various changes and modifications without departing from the scope thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the disclosure being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. In other words, it is contemplated to cover any and all modifications, variations or equivalents that fall within the scope of the basic underlying principles and whose essential attributes are claimed in this patent application. It will furthermore be understood by the reader of this patent application that the words “comprising” or “comprise” do not exclude other elements or steps, that the words “a” or “an” do not exclude a plurality, and that a single element, such as a computer system, a processor, or another integrated unit may fulfil the functions of several means recited in the claims. Any reference signs in the claims shall not be construed as limiting the respective claims concerned. The terms “first”, “second”, “third”, “a”, “b”, “c”, and the like, when used in the description or in the claims are introduced to distinguish between similar elements or steps and are not necessarily describing a sequential or chronological order. Similarly, the terms “top”, “bottom”, “over”, “under”, and the like are introduced for descriptive purposes and not necessarily to denote relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and embodiments of the disclosure are capable of operating according to the present disclosure in other sequences, or in orientations different from the one(s) described or illustrated above.
While some embodiments have been illustrated and described in detail in the appended drawings and the foregoing description, such illustration and description are to be considered illustrative and not restrictive. Other variations to the disclosed embodiments can be understood and effected in practicing the claims, from a study of the drawings, the disclosure, and the appended claims. The mere fact that certain measures or features are recited in mutually different dependent claims does not indicate that a combination of these measures or features cannot be used. Any reference signs in the claims should not be construed as limiting the scope.
| Number | Date | Country | Kind |
|---|---|---|---|
| 23210737.5 | Nov 2023 | EP | regional |
