Patent Application
20100289568
1. Field of the Invention
The present invention relates to the field of operational and instrumentation amplifiers.
2. Prior Art
One of the key performance specifications of an operational amplifier is its DC error or offset voltage. The offset voltage limits the ability of the amplifier to resolve small DC input voltages. The total offset voltage is usually specified assuming a single source of error at the input terminals. The value of this imaginary voltage source represents the input referred offset voltage of the amplifier. The significance of this parameter lies in the fact that the amplifier will not be able to resolve any DC voltages at its input that are smaller than the input referred offset voltage.
In monolithically integrated operational amplifiers, the input referred offset voltage (also called input offset, offset voltage or just offset for short) is mostly due to statistical mismatch between critical components in the circuit. Commonly, these critical components include the input stage transistors, but other devices may contribute significantly to the offset as well. Typical offset voltages due to component mismatch lie in the order of several millivolts.
In the past, many techniques have been proposed and implemented to limit the effect of statistical mismatch on the input referred offset voltage. These techniques fall into one of two categories (see “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, C. C. Enz and G. C. Temes, IEEE J. Solid-State Circuits, vol. 84, November 1996, pp. 1584-1614).
1. Chopper Stabilization
2. Autozeroing
The following will address each of these techniques, along with their respective advantages and disadvantages.
Chopper stabilization relies on periodically swapping the signal paths for the negative and positive input terminals of the amplifier. On average, this causes the offset between the two terminals to even out (see “Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and Chopper Stabilization”, C. C. Enz and G. C. Temes, IEEE J. Solid-State Circuits, vol. 84, November 1996, pp. 1584-1614).
The input referred offset voltage of the input stage gm1 is represented by voltage source Vos. The behavior of the choppers is to multiply their input signal by +1 or −1, depending on the state of clock phase φ2. In the case of a differential signal (e.g. chopper chop1), multiplying by −1 simply means swapping the input signals. Multiplying by +1 indicates direct connections between inputs and outputs.
Note how for one clock phase the input offset source Vos will cause a negative error voltage at the output, while for the other phase the effect will be a positive voltage. The net output error voltage, averaged over time, will be zero.
For the input signal the situation is different. In this case the signal passes to both choppers chop1 and chop2, and the polarity of the output signal will not change. Therefore, the output signal will consist of the unmodified input signal, and a ripple voltage caused by chopping by chopper chop2 of the input offset voltage Vos.
Alternatively, in the frequency domain the choppers chop1 and chop2 can be regarded as multipliers or mixers, shifting the input frequencies by the chopper frequency fchop. From this point of view, chopper chop1 will convert up a DC input signal to the chopper frequency fchop. Input stage gm1 will then amplify the resulting signal at fchop, while chopper chop2 converts the signal back to DC. Note that the DC input signal reappears as a DC signal at the output of chopper chop2. This is because at this point the signal has passed through two choppers, implementing up and down conversion of the input signal.
The situation for the offset source Vos is different, however. Since there is only one chopper between the offset source Vos and the output, the DC offset voltage Vos will get up converted to the chopper frequency fchop at the output. By low pass filtering (or averaging) the output the effect of the offset source Vos can then be eliminated.
Besides to the DC offset, the same frequency up conversion applies to any 1/f or low frequency noise of input stage gm1. Therefore, the 1/f noise is shifted out of the signal band in the same way the DC offset is.
The gain stages gm1, gm4 and gm5 comprise the chopped signal path. Since DC offset is—by definition—a low-frequency phenomenon, the chopped signal path does not require a very high bandwidth. Instead, the parallel input stage gm3 is added to the circuit to deal with high frequency signals. Together, input stages gm1 and gm3 handle the entire spectrum from DC up to the bandwidth of the amplifier. Capacitors Cm1 and Cm2 implement frequency compensation to ensure stability when applying feedback to the amplifier, as well as a smooth transition between the high and low frequency portions of the amplifier gain. This frequency compensation setup is based on Multipath Nested Miller Compensation (see “Frequency Compensation Techniques for Low-Power Operational Amplifiers”, R. Eschauzier and J. Huijsing, section 6.1, Boston, M A: Kluwer, 1995, section 6.1, Boston, Mass.: Kluwer, 1995).
A significant benefit of the chopping technique, besides its effectiveness in reducing offset and 1/f noise, is that the noise power density spectrum (PSD) at low frequencies approaches the thermal noise limit of the amplifier without choppers.
The main disadvantage of chopping is that the output spectrum of the chopper stabilized amplifier will show a sharp peak around the chopper frequency fchop (
This noise peak is caused by the up conversion of the offset voltage and 1/f noise of the input stage gm1, and corresponds to the ripple voltage at the output of the amplifier in the time domain.
Autozeroing includes techniques that calibrate out the input offset by measuring the offset, storing it into some kind of internal memory, and then compensating for the error during normal operation. This process is very similar to zeroing a weighing scale for example. The moment of calibration can be during manufacturing, in which case the measured offset needs to be stored onto a non-volatile memory, to ensure that the measured offset value does not disappear after the part is powered down. Alternatively, the autozeroing can be performed during normal operation, by periodically interrupting the signal path for a brief calibration. In this case, the measured voltage needs to be retained for a short amount of time only, allowing the use of volatile memory, or even a capacitor to store the value. The advantage of autozeroing during normal operation is that as the offset of the amplifier shifts, e.g. due to temperature changes or aging, the autozeroing will track the changes and continue to compensate for it. Autozeroing during manufacturing does not compensate for varying conditions, and is therefore susceptible to offset drift.
It comprises of input stage gm1 with its associated input referred offset voltage source Vos. The switches S1 and S2, transconductor gm2 and capacitor Ci implement the autozero function. When clock phase φ1 is high (autozero), switch S1 shorts the input terminals of input stage gm1. Switch S2 closes a feedback loop around stage gm2, which forces the output voltage of input stage gm1 to zero. After the feedback loop settles, the voltage on autozero capacitor Ci counteracts the input referred offset voltage Vos.
The moment clock phase φ1 goes low (normal operation), switch S2 opens the feedback loop around transconductor gm2. Because of the high input impedance of transconductor gm2, the voltage across the autozero capacitor Ci remains constant (sample-and-hold), and continues to compensate for the offset voltage Vos.
With clock phase φ1 low, input switch S1 goes from shorting out the input stage gm1 to directly connecting the input terminals of the amplifier to the input stage gm1. Input stage gm1 now operates as a normal input stage, connected between the input terminals of the amplifier and the subsequent gain stages gm4 and gm5. As a result of the calibration in the previous clock phase, the small current I2 that transconductor gm2 adds to the output current of input stage gm1 exactly compensates for the error current at the output of gm1 due to offset voltage Vos. In other words, the autozero current I2 effectively eliminates the input referred offset voltage Vos of the amplifier.
Besides eliminating DC offset, the autozero process is also very effective against low-frequency or 1/f noise. This noise component can be regarded as a slowly varying offset voltage, and as long as the amplifier is autozeroed with short enough intervals, any 1/f noise will be removed in the same fashion DC offset is.
The autozeroed amplifier in
Although autozeroing according to
Wide-band noise sampling, which is inherent to any sample-and-hold action, is caused by the fact that the instantaneous noise value at the output of input stage gm1 (and also autozero stage gm2) is sampled by autozero capacitor Ci and held for the entire period that φ1 is low (normal operation). The sampling of the noise takes place by switch S2 and capacitor Ci, which are both components with a bandwidth that far exceeds the bandwidth of the amplifier. Therefore, the noise is sampled with a very high bandwidth, which results in a corresponding high rms value (or standard deviation σ) of the sampled noise voltage in the time domain. As a result, the sampled voltage on autozero capacitor Ci at the end of each autozero period shows a significant random variation. This variation causes a random input referred offset voltage that changes at the end of each autozero interval, and is then kept constant throughout an entire period of normal operation.
In the frequency domain, this wide-band noise sampling causes an increase in the noise floor for low frequencies (see
The corner frequency ωc of this elevated noise band is set by the bandwidth of the autozero loop through transconductor gm2, switch S2 and autozero capacitor Ci and equals gm2/Ci.
In the circuit of
The noise power spectral density (or PSD) of the overall amplifier is shown in
In the attached drawings, for reference, in instances where it matters, all switches are shown in states for a respective low control signal. In that regard, the word switch is used herein and in the following claims in both the singular and the plural sense, and in the sense to include an on/off switch or switches, and switches that alternately connect one line to either of two other lines. However when used in the plural sense, each such switch is responsive to the same control signal. Also the word amplifier as used herein means an amplifier of one or more stages, and may include frequency compensation.
Table 1 summarizes the properties of the chopping and autozeroing techniques for reducing the DC offset and 1/f noise of an amplifier.
Clearly, each of the techniques has its own set of advantages and disadvantages. Chopping results in low noise, but causes a significant output ripple, while autozeroing suffers from wide-band noise sampling, and hence high noise, but does not generate a ripple at the output.
Ideally, we would like to find an alternative approach that combines the advantages of chopping and autozeroing, i.e. low noise and small output ripple.
The circuit consists of autozeroed input stage gm1 that is “embedded” between the two choppers chop1 and chop2. The order of operation of the various parts is as follows. When clock phase φ1 is high, input stage gm1 is being autozeroed by switch S2, transconductor gm2 and autozero capacitor Ci. When clock phase φ1 goes low, input stage gm1 enters normal operation, while the output current of transconductor gm2 compensates for its input referred offset Vos. During this half cycle of normal operation, the two choppers chop1 and chop2 will go through a full clock cycle φ2, averaging out any remaining offset of autozeroed input stage gm1. The cycle repeats by clock phase φ1 going high again, entering the amplifier into autozero.
At first sight, the circuit of
Clearly, the low frequency noise resulting from the wide band noise sampling by autozero capacitor Ci, is shifted to the chopper frequency fchop. Finally, since both the autozeroing and chopping contribute to reducing the offset, the resulting input referred offset can be much lower than by using chopping or autozeroing alone.
The noise PSD of
A simple way to avoid the wide-band noise sampling in the circuit of
Here, the input stage of the amplifier is implemented using two independent transconductors gm1a and gm1b in a so-called ping-pong setup. The two input transconductors are alternately being autozeroed. While one transconductor is in its autozero mode, the other will provide a signal path between the input terminals and the intermediate stage gm4, and vice versa. As a result, the normal signal path will never be interrupted, and no wide-band noise sampling takes place on the Miller capacitor Cm2. This is apparent from the noise PSD in
For low frequencies, the noise of the ping-pong circuit is identical to the thermal noise of the amplifier without chopping and autozeroing. The noise bump due to the autozeroing of gm1a and gm1b is shifted to the chopper frequency fchop by the two choppers chop1 and chop2, as was the case in the circuit of
Although the noise PSD of
An alternative approach to combining the advantages of chopping and autozeroing, without the die size and power penalty of a ping-pong autozeroed input stage, is shown in
This circuit is similar to the circuit of
By placing the autozero pulse in the middle of each half cycle of the chopper clock phase φ2, chopper Chop2 will average out any residual offset after autozeroing in the time between two autozero pulses. This residual offset averaging stems from the fact that during a period between two autozero pulses, the signal is passed through chopper chop2 directly and with reversed polarity with the same duration.
The modified clocking scheme substantially reduces the wide-band noise sampling by switch S2 and Miller capacitor Cm2. Even though the hold voltage on Miller capacitor Cm2 after opening S2 still has the same large random variation as was the case in the circuit of
By choosing a suitably small autozero duty cycle, the overall noise increase due to the wide-band noise sampling can become arbitrarily small. In practice, by choosing a duty cycle less than 10% the noise floor of the circuit will be within several percent of the theoretical thermal noise floor limit.
Notice how in the previous circuit of
Operation is as follows. The first state of the circuit is when clock phase φ3 is high; the circuit is in autozero mode, with the switches labeled φ3 closed. As a result, the inputs of transconductor gm1 are both tied to the positive input terminal. Hence, the input differential voltage of gm1 is zero, while the voltage at the positive input sets the common-mode voltage. The output terminals of input transconductor gm1 are connected to the autozero capacitors Ci1 and Ci2, closing the autozero loop.
The second state occurs after clock phase φ3 goes low again. Now there are two possible situations: either clock phase φ1 goes high, while phase φ2 remains low, or vice versa. Assuming the first case, φ1 high and φ2 low, input stage gm1 is connected directly between the input terminals and the intermediate stage gm4. Offset voltage source Vos will cause a positive error voltage at the output of the amplifier. The two autozero capacitors Ci1 and Ci2 are disconnected from the signal path and hold their voltage to cancel out any offset of input stage gm1.
The circuit enters its third and final state when φ1 and φ2 reverse polarities (φ1 low and φ2 high). In this situation, input stage gm1 is effectively turned upside down, swapping both the input and output terminals. The polarity of the signal path remains the same, but the effect of input offset voltage Vos at the output changes sign: it will cause a negative excursion of the output voltage.
Since states two and three have the same duration, the average effect of the offset source Vos will be zero. State 1 is effectively operating at twice the frequency of states 2 and 3, though states 2 and 3 are each interrupted by state 1, with each half cycle of the chopping being temporarily interrupted by the auto-zeroing process.
The order of states two and three after each autozero pulse φ3 alternates. This results in the following overall order of the circuit states: 2-1-2, 3-1-3, 2-1-2 etc. The average (residual) offset across one autozero cycle, whether it is the 2-1-2 or the 3-1-3 cycle, will be zero.
Input stage gm3 again implements a separate signal path for high frequencies. Together with capacitors Cm1, Cm2a and Cm2b, this parallel input stage gm3 implements Multipath Nested Miller Compensation (see “Frequency Compensation Techniques for Low-Power Operational Amplifiers”, R. Eschauzier and J. Huijsing, section 6.1, Boston, Mass.: Kluwer, 1995). This frequency compensation technique ensures stability when applying feedback to the overall amplifier, while enabling a smooth frequency response without artifacts in the cross-over region between the high and low frequency signal paths. Capacitor C3 is an optional component that can help the gain of the low-frequency signal path (gm1, gm4 and gm5) to drop off steeply enough at high frequencies not to interfere with the high-frequency signal path through parallel input stage gm3.
A final refinement of the circuit in
This circuit is identical to the circuit of
Because of the additional gain stage gm6, the circuit of
By adding an additional input stage to any of the circuits in
In order for the chopping and autozeroing to work properly in the modified circuit, only the input stage devices (including the parallel devices for Multipath frequency compensation) and input switches need to be repeated from the original opamp. The autozeroing can be done across both input stages combined, and therefore does not require additional autozero capacitors, nor autozero feedback switches.
Clock phases φ1 and φ2 are the chopper clock phases. During autozeroing, clock phases φ1 and φ2 are low and the clock phase φ3 is high. Note that if the two drain currents I1 are not perfectly matched, that mismatch, itself, will also cause an offset in the differential pair of transistors M1 and M2. However that offset is also autozeroed by the foregoing process so that a perfect match of the two drain current sources I1 is not required.
In any autozero circuit, the input to the input stage is periodically disconnected and then shorted, with the offset then being stored on one or more capacitors for subtraction from the signal path between autozeroing operations. In the embodiments of
The clock phase φ3 can be thought of as the autozero phase, while the clock phase φ1 and φ2 can be (broadly) thought of as the two chopper phases. One complication that arises in the circuits of
A prior art circuit for generating two-phase non-overlapping clock signals is shown in
It generates the two non-overlapping clock phases φ1′ and φ2′ from the potentially overlapping input clock phases φ1 and φ2. This process is illustrated in
Operation of the circuit is as follows (assuming for simplicity that all gates are delay free, except for the inverters I3 and I4). With clock phase φ1 low and clock phase φ2 high, the output clock phases φ1′ and φ2′ will also be low and high respectively. When the two input clock phases φ1 and φ2 change states (φ1 transitioning to high and φ2 to low), output φ2′ will change almost instantaneously (see
The next change of input state, input clock phase φ1 will go low again, and input clock phase φ2 high. The process reverses, and in this case the output φ1′ responds directly to the falling edge of φ2, while clock phase φ1′ tracks the rising edge of input φ1 with a slight delay. This timing again avoids overlap of the two output clock signals φ1′ and φ2′. Note in
In this case, the circuit needs to make sure that none of the three output clock phases φ1′, φ2′ and φ3′ will ever be high at the same time. Operation is similar to that of the circuit in
For simplicity, all components are assumed to be delay-free again, except for the inverters I4, I5 and I6.
When the input clock phase φ3 is low, the output of inverter I4 is high, and the circuit part consisting of the nand gates N2 and N3, and inverters I2, I3, I5 and I6 behave identically to the prior art circuit in
When input clock phase φ3 transitions high, the output clock phase φ3′ will wait for both other inputs to the nand gate N1 to become high as well, before it follows input clock phase φ3 in going high. The other two inputs of the nand gate N1 will go high—albeit with some delay—because both input clock phase φ1 and φ2 will be low once input clock phase φ3 has gone high. The delay is caused by one of the two inverters I5 and I6, depending on the state of the input clock phase φ1 and φ2. If input clock phase φ1 was low before the input clock transition, it will remain low, while input clock phase φ2 goes from high to low. In this case the delay is caused by inverter I5. Inverter I6 becomes responsible for the delay in the situation where input clock phase φ2 starts off and remains low, while input clock phase φ1 makes the high-to-low transition. The delay before the output clock phase φ3′ goes high, results in the non-overlap time for this clock phase.
A high-to-low transition of input clock phase φ3 affects output clock phase φ3′ almost immediately, as it causes one input to the nand gate N1 (the one connected to input φ3) to go low. One low input to the nand gate is sufficient to make the output clock phase φ3′ go low as well, regardless of the other inputs to the nand gate N1.
Since the circuit of
The overall result of the timing in the circuit of
When operating any of the circuits
A transmission gate consists of the parallel connection of a PMOS and NMOS switch, each of which is operated by an opposite phase signal at its gate. To turn the transmission gate on, the gate of the NMOS device is pulled high, while the gate of the PMOS device is pulled low. At supply voltages below the sum of the threshold voltages of the NMOS and PMOS device, an area in the middle of the common-mode voltage range of the switch will occur where neither of the two devices can develop enough voltage across its gate-source terminals to be turned on.
The alternative to a transmission gate is to use a single NMOS or PMOS device, with a gate drive voltage that can rise above (NMOS) or drop below (PMOS) the supply voltage of the circuit.
Operation of the bootstrapped switch is as follows. While the input terminal clk is held low (switch turned off), device MN7 pulls down node G (gates of the switching transistor) through cascode device MN6. Switch devices MR and MS are in their off states, while capacitor C1 is being charged to the supply voltage by devices MP5 and MN1. Devices MP0 and MP1 are off. Stepping the control voltage clk high (turning the switch on), device MN0 pulls down node E, and device MP1 will start to conduct current. Device MP1 on its turn will connect the pre-charged capacitor C1 between the gate and source of device MR, which will also turn on. With devices MP1 and MR in their on states, the gate-source voltage of the switching device MS equals the voltage Vdd stored on the capacitor C1. With its gate-source voltage Vgs above the threshold voltage, the switch devices MS will turn on.
Even though the voltages at node G and node B can rise significantly above the supply voltage (maximally twice Vdd), safe operation of all devices is guaranteed.
There are two apparent drawbacks of the prior art circuit in
The circuit of
The circuit of
The key modification to allow driving multiple switch devices with one bootstrap circuit is the use of voltage vcm as a reference to lift gate-control capacitor C1, instead of the source of the switch device Ms in the prior art circuit of
The key to successfully operating the switch devices MS1 and MS2 in
1. The voltage vcm will track the minimum of the two voltages at the gates of input transistors MP6 and MP7. This is due to the fact that the input device with the lowest gate voltage, e.g. MP6, will start acting as a source follower, tracking the voltage at its gate with the source, while the other device (MP7 in this example) will be turned off by lack of a sufficiently high gate-source voltage Vgs. In a typical amplifier application, the differential input will be minimal, so that the voltage vcm will accurately reflect the common mode voltage of the differential input. Note also, that only one source follower MN8 need be used for all switches coupled to that differential input.
2. Because of source follower MN8, the common mode voltage vcm can never exceed the positive rail Vdd, even if the tail current source of the input pair MP6 and MP7 is connected to a voltage higher than the supply voltage Vdd. A common situation where the input stage tail current source is tied to a higher supply voltage than the remainder of the amplifier is in amplifiers that employ a charge-pump to obtain a rail-to-rail input common-mode range. The charge pump generates a boosted supply voltage for the input stage, extending its common mode input voltage range.
Because of these two points, the circuit continues to guarantee safe operation of all devices in the circuit. The gate of the switching devices MS1 and MS2 will never be pulled higher than one supply voltage Vdd above the minimum of the two input voltages Vinp and Vinm. Consequently, the gate-source voltages Vgs of switching devices MS1 and MS2 cannot exceed the supply voltage Vdd. Also, node E, which is connected to vcm when switch devices MN0 and MR are closed, cannot exceed the supply voltage Vdd. This is critical to avoid forward biasing of the backgate diode of MP3.
Operation of the circuit is similar to that of the prior art circuit in
The embodiments shown and described herein use differential amplifiers. It should be noted that a single ended amplifier is functionally a differential amplifier with one input and/or one output connected to a circuit ground. Similarly, a chopper alternately reverses two inputs, independent of whether one is a circuit ground or not. Accordingly references herein and in the following claims to differential amplifiers is a reference that includes amplifiers with one input and/or one output connected to a circuit ground, i.e., commonly referred to as single ended amplifiers. Also the embodiments shown and described herein are shown and described with respect to MOS transistors, though other active devices may be used, such as, by way of example, bipolar transistors.
Thus the present invention has a number of aspects, which aspects may be practiced alone or in various combinations or sub-combinations, as desired. While certain preferred embodiments of the present invention have been disclosed and described herein for purposes of illustration and not for purposes of limitation, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the full breadth of the following claims.
