Patent Application
20090302812
Multi-core microprocessors require many clock domains and hence many phase locked loops (PLL). The jitter requirements for PLL's on multi-core microprocessors are much more stringent, requiring a sigma jitter of 1.5 ps, compared to the standard 5-8 ps jitter typically associated with PLLs presently used. One possibility to achieve such a low jitter is to use an inductive-capacitive (LC) PLL. However, this requires the process to incorporate integrated inductors, which adds significant cost and complexity to the manufacturing. In addition, the LC PLLs have a very thin tuning range, which disqualifies them in many applications which require banding. Transistor-based low jitter PLL's have been suggested, but require on chip voltage regulators (VR) which have very low noise characteristics, referred to as low-noise voltage regulators (LNVR).
When there are many PLLs and VRs present on chip, the impedance of the VRs as seen from the analog power supply pin can cause the LC network on the package to oscillate. In digital microprocessor chips, the package network of the analog supply typically has much less supply traces than the digital supply. This may cause a relatively high inductance at this supply, namely several nH. For many VRs the phase of the impedance seen from the supply pin will become >90 degrees near the bandwidth of the VR (e.g., 100-200 MHz) which will cause negative real impedance. If the frequency that the impedance crosses from positive to negative is in the resonant range of the LC network (e.g., <500 MHz) and the inductance of the LC network is high enough, then oscillations can occur.
The features and advantages of the various embodiments will become apparent from the following detailed description in which:
The VREF may be provided to the negative (inverting) terminal and the FB may be provided to the positive (non-inverting) terminal of the OP1110. The output of the OP1110 may be coupled to the shunt component 160 so that V2 is provided thereto. The shunt component 160 may be used to shunt the current from node 2 to a first supply (e.g., ground). The V2 applied to the shunt component 160 may control the amount of current that is shunted from node 2. The shunt component 160 may include one or more transistors. The shunt component 160 may include a negative channel transistor (e.g., NMOS). The shunt component 160 is illustrated as an NMOS transistor but is not limited thereto. The V2 may be coupled to a gate of a shunt transistor 160. The source of the shunt transistor 160 may be coupled to the first supply (ground) and the drain may be coupled to the output of the VR 100, the drain of the shunt transistor 150, the capacitor 140 and the divider 170 (node 2).
The OP2120 may receive the V2 and its output (feedback) as input and may provide an output voltage (V1). The V1 may be provided to the negative (inverting) terminal and the V2 may be provided to the positive (non-inverting) terminal of the OP2120. The OP2120 may be configured as a unity-gain buffer so that V1 follows V2 (V1=V2). The output of the OP2120 may be coupled to the drive component 150 so that V1 is provided thereto. The drive component 150 may be used to drive the current from node 2 to a second supply (e.g., voltage rail (VCCA)). The V1 applied to the drive component 150 may control the amount of current that is driven to node 2. The drive component 150 may include one or more transistors. The drive component 150 may include a positive channel transistor (e.g., PMOS). The drive component 150 is illustrated as a PMOS transistor but is not limited thereto. The V1 may be coupled to a gate of a drive transistor 150. The source of the drive transistor 150 may be coupled to the second supply (VCCA) and the drain may be coupled to node 2 (the output of the VR 100, the drain of the shunt transistor 160, the capacitor 140 and the divider 170).
The capacitor 130 may be used to insert a low bandwidth pole at the output of OP2120 and may also improve the power supply rejection ratio (PSRR) of the VR 100 by enabling the drive transistor 150 to better reject VCCA noise. The capacitor 140 may be a decoupling capacitor used to decouple the output of the VR 100.
The OP1110 and the shunt transistor 160 may provide a first path to the output. The first path may be a fast path that may provide an AC high bandwidth path to enable fast corrections for any changes in the output voltage. The OP2120 and the drive transistor 150 may provide a second path to the output. The second path may be a slow path that may provide a DC low bandwidth path to ensure the gate of the drive transistor 150 does not change too quickly which may prevent the VR 100 from having a negative impedance as seen from the second supply (VCCA).
In operation, when there is a change in the VREG (as detected by OP1110 comparing FB and VREF), the OP1110 may adjust the V2 (voltage applied to shunt transistor 160) quickly to compensate and the shunt transistor 160 accordingly may quickly adjust the amount of current shunted from node 2. The OP2120 may also adjust the V1 (voltage applied to the drive transistor 150) slowly and the drive transistor 150 may accordingly slowly adjust the amount of current passed to node 2.
If the FB were to increase above VREF, the OP1110 may increase the V2, and the OP2120 may increase the V1 since it is configured as a unity-gain buffer. The increased V1 may reduce the magnitude of the gate-to-source voltage (Vgs) of the drive transistor 150 which may cause the drive transistor 150 to source less current to node 2 thereby counteracting the increased VREG and FB. The increased V2 may increase the magnitude of the Vgs of the shunt transistor 160 which may cause the shunt transistor 160 to shunt more current from node 2 thereby also counteracting the increased VREG.
If the FB were to decrease below VREF, the OP1110 may decrease the V2 and the OP2120 may accordingly decrease the V1. The decreased V1 may increase the magnitude of the Vgs of the drive transistor 150 which may cause the drive transistor 150 to source more current to node 2 thereby counteracting the decreased VREG and FB. The decreased V2 may decrease the magnitude of the Vgs of the shunt transistor 160 which may cause the shunt transistor 160 to shunt less current from node 2 thereby also counteracting the decreased VREG.
The lower bandwidth of OP2120 may mean that the magnitude of the Vgs of the drive transistor 150 is changed (increased or decreased) at a slower rate than the Vgs of the shunt transistor 160 so that the adjustment to the current provided by the drive transistor 150 is slower than the adjustment to the current shunted by the shunt transistor 160. The quick adjustment of the shunt transistor 160 current may compensate for any changes in the current provided by the drive transistor 150 which may be caused by variations in the second supply (VCCA). The total current flowing out of the VR 100 at its output may stay constant. This may assist in the PSRR of the VR 100.
The capacitor 130 between V1 and VCCA may strongly couple the gate of the drive transistor 150 to its source. Thus, when the power supply (second source) changes at high frequency, this change is delivered to the gate of drive transistor 150 so that the Vgs stays stable. This may help stabilize the current in the drive transistor 150 and assist in the PSRR.
The adjustment of the V1 may slowly return the VR 100 to a DC condition. Since the gate of the drive transistor 150 may be changed slowly, the gate of the drive transistor 150 may not be overshoot. The VR 100 may accordingly exhibit only positive impedance as seen by the input supply (VCCA) and avoid problems (e.g., oscillations) caused by negative impedance at certain phases. By utilizing a fast path and a slow path, the OP1110 and the OP2120 may be kept in phase. The VR 100 may provide a PSRR in the approximate range of 20-30 dB.
The OP2120 being configured as a unity-gain buffer (as a follower to OP1110) so that V2=V1 may result in the voltage required at the gate of the drive transistor 150 (V1) being used to determine the DC voltage at the gate of the shunt transistor 160 (V2). The voltage at gate of drive transistor 150 (V1) may equal VCCA−Vgs of the drive transistor 150. Thus, V1 may vary as a function of VCCA, threshold voltage (Vth) of the drive transistor 150 and the current required to be passed by the drive transistor 150. Accordingly, the V2 may vary as a function of V1 (VCCA, Vth, I) as well as a function of Vth of shunt transistor 160 and the current required to be shunted by the shunt transistor 160. Accordingly, the current shunted by the shunt transistor 160 may vary over at wide range based on process, voltage and temperature (PVT) variations in the shunt transistor 160, the drive transistor 150 and VCCA. The wide current swing of the shunt transistor 160 for PVT variations may result in the VR 100 being inefficient (shunt transistor 160 drawing too much or not enough current). This effect may also cause a lower performance in the VR 100.
Tightening the current spread in the shunt transistor 160 may improve the performance of a VR beyond the limitations of the example VR 100 of
The gate of the transistor 330 may receive the VREF and the gate of the transistor 340 may receive the FB from node 1. The gates of the transistors 350, 360 may be connected to an output voltage (V3) node of the transistor stack 340, 360. The reference voltage provided as an input to the OP2120 may be V3. The V3 may be provided to the positive terminal and the V2 may be provided to the negative terminal of the OP2120. The OP2120 (the slow path) may be used to drive the V2 towards the V3.
The V2 and the V3 being the same may create a virtual current mirror between the transistors 160, 350, 360. All of these currents may be a multiple of the current source 320. The current source 320 may be generated by a central current reference, or any other current source. For example, a constant, trimmable PVT-independent current source may be utilized. In this configuration, the current in the transistor 360 may be derived from the current source 320, while the currents in the transistors 350, 160 may be derived from the current in the transistor 360 and hence also from the current source 320. Accordingly, the V3 node may be referred to as the current mirror node and the transistor 360 may be referred to as the current mirror transistor.
The V2 being driven to V3 limits the swing in the current driven by the transistor 160 due to PVT variations. In addition to the current control, the DC gain of the LNVR 300 may be higher since the drains of the transistor and the transistor 350, 360 are regulated by the OP2120 (V2 and V3 are the inputs). The DC gain of the LNVR 300 is thus determined by both the fast path through the OP1310 and the slow path through the OP2120. The AC gain is determined by the fast path which is the much higher bandwidth path.
By controlling the currents in the OP1310 and in the shunt transistor 160, one can increase the bandwidth and thus significantly improve performance in terms of the parameters mentioned earlier.
Since V2 and V3 may be at the same voltage, the transistors 420, 430 may reduce the DC gain of the fast path which allows an increase in the bandwidth. The DC gain of the fast path may be reduced without affecting performance of the LNVR 400 due to the increase in the DC gain caused by regulating the drains of the transistors 350, 360 (discussed above with respect to
The performance of the LNVRs 300, 400 may be directly dependent on the current source 320. Utilizing a trimmable PVT-independent current source as the current source 320 enables the current provided to be adjusted. For example, the current may be increased when the LNVR 300, 400 is utilized in applications where better PSRR/noise properties are desired. The current may be decreased for lower power or lower performance applications. The adjustment of the current and performance of the LNVR 300, 400 may be useful in applications where only some of the PLLs, such as the peripheral component interconnect (PCI), require very high jitter performance, and other PLLs can function at lower power with a compromise in the PSRR and noise. The LNVRs 300, 400 may be configurable by trimming the current source 320 current so that in critical applications it can achieve very high performance, and in less critical applications it can be low power (current efficient).
The LNVRs 200, 300, 400 provide very good control of the current in the shunt transistor by driving the output of the OP11110, 310, 410 (V2) to a steady reference voltage (VREF, V3). The separation between the AC and DC gain paths enables high gain and accuracy in the DC path without affecting stability. The AC path has a lower gain, but much higher bandwidth, which enables lower thermal noise and better PSRR. The LNVRs 200, 300, 400 may achieve greater than 42 dB of PSRR. The LNVRs 200, 300, 400 may keep the impedance phase below 60 degrees at the frequencies of interest and may keep the real impedance from becoming negative.
The LNVRs 200, 300, 400 may be utilized to drive PLLs, specifically LNPLLs. As there are several sources of noise in the LNPLL, it is highly desirable to minimize the VR noise as much as possible in order to meet the jitter limits for LNPLLs utilized in multicore processors (e.g., 1.5 ps). The noise in the LNVRs 200, 300, 400 may have a negligible effect on the overall jitter of a LN PLL.
The LNVRs 200, 300, 400 may be fabricated using only CMOS devices and can be used to drive LN PLLs fabricated using only CMOS devices which provides significant cost and complexity advantage.
The various embodiments of the LNVR described herein (e.g., 200, 300, 400) may be implemented in the microprocessor 500 as LNVR 550. The LNVR 550 may provide regulated voltages to loads, for example, PLLs that are used within the microprocessor 500. The various embodiments of the LNVR may also be implemented in the other computer system components. The various embodiments of the LNVR are not limited to being implemented in computer systems. Rather, the various embodiments of the LNVR may be implemented in any number of systems or components requiring regulated voltages, for example systems or components that desire low noise regulated voltages or the ability to obtain a low noise regulated voltage when desired.
Although the disclosure has been illustrated by reference to specific embodiments, it will be apparent that the disclosure is not limited thereto as various changes and modifications may be made thereto without departing from the scope. Reference to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described therein is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment” appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
The various embodiments are intended to be protected broadly within the spirit and scope of the appended claims.
