The present invention relates to electronic circuitry and, in particular, to a low-offset, cascoded gain single stage sense amplifier used in high voltage applications with wide common mode range (CMR).
Typical common gate differential pairs have an offset, especially those used as sense amps which require a wide common mode range (CMR). This offset is caused by the following two components. 1) The popularly known one is threshold voltage (VT) mismatch, which is dependent on how effective matching techniques have on the technology process. 2) The usually over looked component is the effect even a small drain-to-source voltage (Vds) mismatch has on the offset of the diff pair due to lambda issues. Table 1, below illustrates this numerically.
The source voltage of sense amp is given by;
Table 1, below uses the equation above to illustrate the effect of • on the input pair offset. The following assumptions are made; no VT mismatch, ID (drain current) is equal in both legs, and VG (gate voltage) is equal.
From Table 1, it can be seen that when pushing for a very small offset, even a 100 mV Vds mismatch on the input diff pair can cause a >1 mV input (Vs) offset if the process has a poor lambda. This tells us using a normal cascoded topology will not be adequate especially if the Vds mismatch of the cascoded transistors is significant, which is expected in most sense amp applications.
A prior art single stage common gate sense amplifier is shown in
A low-offset, wide CMR, cascoded gain single stage amplifier includes: a common gate differential pair; a first amplifier having a first input coupled to a first leg of the differential pair, and a second input coupled to a second leg of the differential pair; a current mirror coupled to the differential pair; a second amplifier having a first input coupled to a first leg of the current mirror, and a second input coupled to a second leg of the current mirror.
In the drawings:
A preferred embodiment low offset, wide CMR, cascoded gain single stage sense amp is shown in
The preferred embodiment device of
A single stage gain of up to 140 dB can be obtained based on the well known gain boost technique in the preferred embodiment of
Output resistance of a conventional prior art cascoded current mirror shown in
Where gm2 is the transconductance of transistor 32, go1 is the inverted output impedance of transistor 22, and go2 is the inverted output impedance of transistor 32.
However, output resistance of the preferred embodiment regulated cascode current mirror shown in
If AL=AH=A, is open loop gain of nested amps Al and Ah.
Where gm2 is the transconductance of transistor 62, go1 is the inverted output impedance of transistor 52, and go2 is the inverted output impedance of transistor 62.
Therefore the gain of the preferred embodiment sense amp is:
Where gm
From above equation it is clear that the preferred embodiment topology of
While this invention has been described with reference to an illustrative embodiment, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiment, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
This application claims priority under 35 U.S.C. 119(e)(1) to U.S. Provisional Application No. 60/787,354 (TI-61492PS) filed Mar. 30, 2006.
Number | Date | Country | |
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60787354 | Mar 2006 | US |