This description relates to driver circuitry and systems using the driver circuitry.
Low-dropout (LDO) voltage regulators supply electrical power in a variety of applications, as for example in low-voltage devices such as voltage-controlled oscillators (VCOs), analog-to-digital converters, digital-to-analog converters (DACs), high-end processors, radio frequency (RF) amplifiers, serializer-deserializer (SerDes) circuits, field programmable gate arrays (FPGAs) and the like. The power management circuitry, which is configured to drive the LDO, can affect performance of the LDO. For example, the speed and headroom of the power management circuitry can impact the overall LDO performance.
In a described example, a circuit includes an input stage, first and second path stages and a load transistor. The input stage has a control voltage input, a feedback input, a first control output and a second control output. The feedback input is coupled to a driver output. The first path stage has a first voltage input and a third output. The first voltage input is coupled to the first control output, and the third output is coupled to the driver output. The second path stage has a second voltage input and a fourth output. The second voltage input is coupled to the second control output, and the fourth output is coupled to the driver output. The load transistor has a control input and a voltage output. The control input is coupled to the driver output, and the input stage configured to apply gm-boosting to the first path stage to turn on the load transistor responsive to an output voltage at the voltage output.
In another described example, a circuit includes a common path input stage configured to provide a first gm-boosted control signal at a first output responsive to an error signal requesting turn on of a load transistor. The common path input stage is configured to provide a second control signal at a second output responsive to the error signal requesting turn off of the load transistor. A first path stage is configured to provide a first voltage to a driver output responsive to the first gm-boosted control signal. A second path stage is configured to provide a second voltage to the driver output responsive to the second control signal. The load transistor is configured to regulate the output voltage responsive to the voltage at the driver output by turning on responsive to the first voltage and turning off responsive to the second voltage.
In a further described example, a system includes an outer loop circuit, a class AB driver and a load. The outer loop circuit has a reference input, a feedback voltage input and an error output. The class AB driver includes a common path stage, a pull-up path circuit, and a pull-down path circuit. The common path stage has an error input, a feedback input, a first gm-boosted output and a second output. The error input is coupled to the error output. The pull-up path circuit includes a first buffer and a pull-up transistor. The first buffer has a first buffer input and a first buffer output, in which the first buffer input is coupled to the first gm-boosted output. The pull-up transistor has a first control input and a third output. The first control input is coupled to the first buffer output, and the third output is coupled to a driver output. The pull-down path circuit includes a second buffer and a pull-down transistor. The second buffer has a second voltage input and a second buffer output, in which the second voltage input is coupled to the second output. The pull-down transistor has a second control input and a fourth output. The second control input is coupled to the second buffer output, and the fourth output is coupled to the driver output. The load has an input and a feedback output, in which the input is coupled to the driver output and the feedback output is coupled to the feedback voltage input. The feedback output is configured to provide a signal representative of an output voltage.
Example embodiments relate to driver circuitry, such as class AB driver circuits and to systems and circuits implementing one or more class AB driver circuits.
As an example, a driver circuit includes a common path input stage and first and second output stages coupled in parallel between first and second voltage terminals. Each of the first and second output stages can be implemented as including a respective buffer and output transistor. The output transistors can be coupled between the first and second voltage terminals, in which each output transistor is coupled to a driver output. The common path input stage has first and second outputs, in which the first output is coupled to an input of the respective buffer of the first output stage and the second output is coupled to an input of the respective buffer of the second output stage. The common path input stage is configured to provide a transconductance (gm)-boosted control signal at the first output to control the respective output transistor of the first output stage responsive an error signal. The common path input stage is configured to provide a second control signal at a second output to control the respective output transistor of the second output stage responsive to the error signal. The common path input stage is configured to apply the gm boost to the same polarity as the common path input or load transistor being driven. For the example of n-channel metal oxide semiconductor (NMOS) inputs or loads, the common path input stage is configured to apply the gm boost to the pull up, or turn on, of the load NMOS. For the example of p-channel metal oxide semiconductor (PMOS) inputs or loads, the common path input stage is configured to apply the gm boost to the pull down, or turn on, of the load PMOS. In some examples, the common path circuit includes a compensation filter to reduce peaking in the closed loop response of the driver circuit.
The driver circuit described herein can be implemented as a closed loop class AB driver configured to supply a drive signal to a capacitive circuit, which is adapted to be coupled to the driver output. The capacitive circuit can include a field effect transistor (FET), such as an n-channel FET (NFET) or p-channel FET (PFET), a bipolar junction transistor (BJT), such as an NPN or PNP, and/or other device having an input capacitance. For example, the driver output is coupled to the gate of a low-threshold-voltage (Vth) low-dropout (LDO) power FET. The driver circuit is configured to use gm-boosting to turn on the power FET. The driver circuit can also be configured to drive the gate of the LDO power FET close to ground for full turn off in low-input low-output (LILO) operation, which enables the driver circuit to achieve low headroom. The driver circuit further can maintain a low output impedance at the driver output for a finite current budget in order to remain stable in a high bandwidth (e.g., greater than 1 MHz) LDO loop. The class AB driver circuits and systems described herein thus can be configured to implement a low headroom, high bandwidth driver circuit. The driver circuit can also achieve a reduced output impedance with less current to allow upstream power management implemented by the common path circuit to have a smaller area and use reduced current compared to many existing designs.
As used herein, the term “circuit” can include a collection of active and/or passive elements that perform a circuit function, such as an analog circuit or control circuit. Additionally or alternatively, for example, the term “circuit” can include an integrated circuit (IC) where all and/or some of the circuit elements are fabricated on a common substrate (e.g., semiconductor substrate, such as a die or chip). In an example, the driver circuit 100 is implemented in an integrated circuit (IC) chip or as part of a system on chip (SoC).
The input stage 106 includes an input transistor M1 having a gate coupled to (or providing) the common path input 112. In the example of
The first output stage 108 includes a buffer 130 and an output transistor M4. An input of the buffer 130 is coupled to the first output 114, and the buffer output is coupled to the gate of M4. M4 is coupled between the voltage terminal 118 and the driver output 102. For example, the input of buffer 130 has a positive polarity. The input stage 106 is configured to supply a gm-boosted control signal at 114 responsive to the error signal V_ERROR having a value representative of a command to increase (or decrease) an output voltage. For example, the gain-boosting circuitry, which includes current source 124 and filter network 126, is coupled to the output of the current mirror (the drain of M3 and output 114). As described herein, the gain-boosting circuitry provides a gain described by the gm of M3 times an output impedance at 114 based on combined impedance at the drain of M3, current source 124 and filter network 126. The gain-boosting circuit thus is configured to implement gm-boosting for the first output stage 108. The input stage 106 thus is configured to provide the gm-boosted control signal to the input of output stage 108. In the example of
The second output stage 110 includes a buffer 132 and an output transistor M5. An input of the buffer 132 is coupled to the second output 116, which is coupled to the common gates of M2 and M3. The output of the buffer 132 is coupled to the gate of M5, and M5 is coupled between the driver output 102 and the voltage terminal 120. For example, the input of buffer 132 has a negative polarity (e.g., opposite of the polarity at the input of buffer 130). The input stage 106 is configured to supply a respective control signal at a second output 116 responsive to the error signal V_ERROR requesting a decrease or no change in the output voltage. In the example of
In some examples, M5 can be implemented using a transistor that is of the same flavor of transistor as M4. As used herein, a given type of transistor (e.g., FET or BJT) has multiple subtypes, which are referred to herein as flavors (e.g., N or P flavors). For example, a FET transistor type (e.g., a MOSFET or junction FET (JFET)) can be implemented in n-channel FET (NFET) and PFET flavors. Similarly, a BJT type of transistor can be implemented in NPN and PNP flavors. A given driver circuit 100 can include more than one type of transistor, and different types of transistors can be the same or different flavors, such as described herein. For an example where the driver circuit 100 is implemented using FETs, M4 and M5 are both NFETs or M4 and M5 are both PFETs. In other examples, such as where M4 and M5 are implemented as bipolar junction transistors (BJTs), M4 and M5 are both NPN BJTs or M4 and M5 are both PNP BJTs.
In an example where the output circuitry 104 is implemented to include a load transistor (e.g., an LDO power transistor, such as M12 shown in
By configuring the input stage 106 to implement gm-boosting, as described herein, the output impedance at 102 can also be reduced for a given bias current. As a result, the driver circuit 100 can be implemented with low headroom and high bandwidth, particularly suitable for LILO operation and fast speed. This further enables upstream power management circuitry (e.g., charge pump circuitry—not shown) to be implemented with reduced area and configured to operate at lower current than many existing approaches.
The regulator system 200 includes an outer loop circuit 204 configured to control the output voltage VOUT responsive to feedback. In the example of
The input stage 106 includes an input transistor M1 having a gate coupled to the output of the amplifier 206. A filter 208 is coupled in an inner loop feedback path between the source of M1 and the driver output 102. For example, the filter 208 includes a parallel resistor R2 and a capacitor C2 configured to dampen peaking in the driver output signal VDRV provided at the output 102. The drain of M1 is coupled to a current mirror 122 formed of FETs M2 and M3. The gate and drain of M2 are coupled to the drain of M1. M2 and M3 have a common gate and a common source coupled to terminal 118. The drain of M3 is coupled to ground terminal 120 through current source 124. The current source 124 is configured to provide a bias current to the drain of M3, such as a fixed or dynamically biased current source. The current source 124 can be implemented as including an arrangement of current mirrors coupled to a main bias current generator (e.g., within an IC implementing the system 200). In the example of
The first output stage 108 of the driver circuit 100 includes a PFET M6 coupled in series with respective current sources 210 and 212 between voltage terminals 118 and 120. The gate of M6 is coupled to the output 114 of the input stage 106. The source of M6 is coupled to the gate of NFET M4, and the source of M4 is coupled to the driver output 102. Another NFET M7 is coupled between the gate of M4 and the ground terminal 120. The gate of M7 is coupled to the drain of M6. Thus, in the example of
The second output stage 110 of the driver circuit 100 includes a PFET M8 having a source coupled to voltage terminal 118 (e.g., VDD) and a drain coupled to the drain of M9 and to the gates of both M9 and M10. Like M8, the sources of M9 and M10 are coupled to voltage terminal 118. A current source 214 is coupled between the drain of M9 and voltage terminal 120 (e.g., ground). The current source 214 is configured to bias the current mirror network formed by M8, M9 and M10. The drain of M10 is coupled to the drain of NFET M11, which is diode-connected between M10 and voltage terminal 120 (e.g., ground). The gate and source of M11 are coupled to the gate of output FET M5. In the example of
The system 200 also includes a load FET M12 having a gate coupled to driver output 102. The source of M12 is coupled to the output terminal 202, and the drain of M12 is coupled an input voltage terminal 216 adapted to be coupled to an input voltage VIN. For example, M12 is implemented as an LDO power FET. As described herein, M12 can be implemented as an N or P flavor load transistor. In the example of
Each of M4, M5 and M12 can be implemented using the same flavor of transistor, such as described herein. In the example of
In an example, the regulator system 200, including the outer loop circuit 204, the driver circuit 100 and the output FET M12, is implemented in a single IC (e.g., on a given IC die). In another example, the output FET M12 is part of a separate IC external to an IC implementing the driver circuit 100 and the outer loop circuit 204.
In the example of
is representative of the gain of the input stage 106 due to M1 and M2;
is representative of the gain of the output stage 110 due to M8, M10, M5, M9 and M11; and
is representative of the gain of the output stage 108 due to M4 and M3 and the output impedance of M3 in parallel with the impedance of current source 124 in parallel with the filter network 126, which includes resistor R3 and capacitor C3.
Thus, in practice the values of the components can be configured to tune the gm-boost is applied to input of the output stage 108 during pull-up of VDRV at the driver output 102 or when M12 is being turned on. For example, the current source 124 and the filter network 126 are configured to increase impedance at the gate of M6 (e.g., at the output 114) to implement the gm-boosting to the first path stage, as shown in the above equations. In a typical example, gm-boosting can increase transconductance gain (gm) by a factor of one hundred or more due to the increased impedance at the output 114 of the input stage 106 (e.g., due to
The gm-boosting during turn on of M4 can thus push a pole of a capacitive power FET gate (or other capacitive load coupled to driver output 102) out of the LDO loop to a higher frequency while using a small amount of bias current. The second output stage 110 is configured to turn off the load transistor M12 to within a saturation voltage VDSAT of ground or a supply voltage (depending on the configuration of the driver circuit 100). For example, responsive to M5 being turned on to pull-down the driver output 102, the drive voltage VDRV swings to a saturation voltage of M5 (e.g., VDSAT,M5) above the voltage (e.g., ground) at 120 while maintaining low wideband output impedance. Such features can be implemented in a low cost, low bias current circuit configuration (e.g., on an IC), which is useful for high bandwidth LDO operations.
In view of the foregoing, the voltage regulation system 200 includes a class AB driver circuit that provides desired voltage headroom and high bandwidth over a range of expected operating conditions. The driver circuit is particularly efficient and economical for LILO applications.
The driver circuit 100 includes a common path input stage 106 and respective output stages 108 and 110. As described herein, the common path input stage 106 is configured to implement a gm-boost to the output stage 108. The gm-boosting enables the driver circuit to react more quickly to increased current demand and reduce undershoot. As a result, the driver circuit 100 is configured to implement a stronger turn on for the LDO power FET M12 or to pull up VDRV at 102. This is in contrast to some existing designs that tend to be configured to implement a stronger turn off of the LDO power FET to reduce overshoot transients.
In an example, the system 300, including the outer loop circuit 204, the driver circuit 100 and the output FET M12 are implemented in a common IC. In another example, the output FET M12 is part of a separate IC external to the IC implementing the driver circuit 100 and outer loop circuit 204.
In the example of
The other graph 402 includes plots 410 and 412 for respective open and closed loop phase responses for the driver circuit 100 in the absence of RC filter 208 shown in
As another example,
In the example of
The first output stage 108 includes a buffer 130 and an output transistor M4. An input of the buffer 130 is coupled to the first output 114, and the buffer output is coupled to the gate of M4. M4 is coupled between the voltage terminal 120 and the driver output 102. For example, the input of buffer 130 has a negative polarity. The input stage 106 is configured to supply a gm-boosted control signal at 114 responsive to the error signal V_ERROR having a value representative of a command to decrease (or not change) VOUT. For example, the gain-boosting circuitry, which includes current source 124 and filter network 126, is coupled to the output of the current mirror (the drain of M3 and output 114). As described herein, the gain-boosting circuitry provides a gain described by the gm of M3 times an output impedance at 114 based on combined impedance at the drain of M3, current source 124 and filter network 126. The gain-boosting circuit thus is configured to implement gm-boosting for the first output stage 108. The input stage 106 thus is configured to provide the gm-boosted control signal to the input of output stage 108. In the example of
The second output stage 110 includes a buffer 132 and an output transistor M5. An input of the buffer 132 is coupled to the second output 116, which is coupled to the common gates of M2 and M3. The output of the buffer 132 is coupled to the gate of M5, and M5 is coupled between the driver output 102 and the voltage terminal 118. For example, the input of buffer 132 has a positive polarity (e.g., opposite of the polarity at the input of buffer 130). The input stage 106 is configured to supply a respective control signal at a second output 116 responsive to the error signal V_ERROR requesting an increase in VOUT. In the example of
In view of the foregoing, circuits and systems described herein can implement a driver circuit having lower headroom, higher bandwidth and an improved transient response. The driver circuit can also be configured with a lower output impedance for a given bias current, which enables the driver circuit to achieve higher bandwidth operation than other driver designs.
As a result, circuits and systems implementing a class AB driver circuit, as described herein, can be used to provide lower supply voltages to end equipment loads, which results in power savings. Furthermore, an improved transient response, particularly due to reduced undershoot, can further achieve improved speed, and higher accuracy. The lower bias currents used in the driver circuit (e.g., by current sources 124, 210 and 212) affords power savings and enables smaller charge pump. Collectively, such factors enable the driver circuit to be implemented in smaller size than comparable existing solutions.
In this description, the term “couple” or “couples” means either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, so device B is controlled by device A via the control signal generated by device A.
The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
This application claims priority to U.S. provisional patent application no. 63/257,040, filed on Oct. 18, 2021, which is incorporated herein by reference in its entirety.
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