Patent Application
20170076798
Aspects of the present disclosure relate generally to memories, and more particularly, to reading of content addressable memories (CAMs).
Content-addressable memories (CAMs) compare input search data, called “tags” against a table of stored data, and return the address of the matching data. Content-addressable memories (CAMs) may have a single clock cycle throughput making them faster than other hardware-based and software-based search systems. Content-addressable memories (CAMs) can be used in a wide variety of applications requiring high search speeds. These applications include coding and decoding, compression, and image coding. Other applications include classifying and forwarding Internet protocol (IP) packets in network routers.
In networks, like the Internet, a message such an as e-mail or a Web page is transferred by first breaking up the message into small data packets of a few hundred bytes and then sending each data packet individually through the network. The packets are routed from the source, through network routers, and reassembled at the destination to reproduce the original message.
One function of a network router is to compare the destination address of a packet to all possible routes, in order to choose the appropriate route. A content-addressable memory (CAM) is a good choice for implementing this lookup operation due to its fast search capability.
However, the speed of the content-addressable memory (CAM) comes at the cost of increased silicon area on the associated chip as well as at the cost of power consumption. Because portable consumer devices such as cellular phones, tablets, laptops, personal digital assistant (PDA), smart phones, entertainment devices, and the like commonly benefit from smaller form factors and reduced power consumption, techniques to reduce the silicon area occupied by content-addressable memories (CAMs) as well as techniques to reduce their power consumption are desirable.
Example implementations of the invention are directed to apparatuses, methods, systems, and non-transitory machine readable media for reading and/or testing a content addressable memory (CAM).
One implementation includes a method for reading a content addressable memory (CAM). The CAM includes a plurality of bitcells arranged into an array of rows and columns, where each column of the array includes both a first compare line and a second compare line coupled to each bitcell included in the column Further, each row of the array includes a match line coupled to each bitcell included in the row, where each match line is configured to indicate a match, during a first mode of operation, between compare data received via the first and second compare lines with bitcell data stored in the bitcells of a respective row. The method include controlling a first compare line of a first column of the array to a first logic state while controlling the second compare line of the first column as well as the first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, to provide bitcell data stored in at least one bitcell of the first column to a respective match line. The method also includes reading the bitcell data on the respective match line.
Another implementation includes an apparatus for reading a content addressable memory (CAM). The CAM includes a plurality of bitcells arranged into an array of rows and columns, where each column of the array includes both a first compare line and a second compare line coupled to each bitcell included in the column. Further, each row of the array includes a match line coupled to each bitcell included in the row, where each match line is configured to indicate a match, during a first mode of operation, between compare data received via the first and second compare lines with bitcell data stored in the bitcells of a respective row. The apparatus includes means for controlling a first compare line of a first column of the array to a first logic state while controlling the second compare line of the first column as well as the first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, to provide bitcell data stored in at least one bitcell of the first column to a respective match line. The apparatus also includes means for reading the bitcell data on the respective match line.
Another implementation includes an apparatus for reading a content addressable memory (CAM). The CAM includes a plurality of bitcells arranged into an array of rows and columns, where each column of the array includes both a first compare line and a second compare line coupled to each bitcell included in the column. Further, each row of the array includes a match line coupled to each bitcell included in the row, where each match line is configured to indicate a match, during a first mode of operation, between compare data received via the first and second compare lines with bitcell data stored in the bitcells of a respective row. The apparatus includes drive logic coupled to each column of the array, for controlling a first compare line of a first column of the array to a first logic state while controlling the second compare line of the first column as well as the first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, to provide bitcell data stored in at least one bitcell of the first column to a respective match line. The apparatus also includes sense logic coupled to the respective match line for reading the bitcell data on the respective match line.
Another implementation a non-transitory computer-readable medium including program code stored thereon for reading a content addressable memory (CAM), the CAM having a plurality of bitcells arranged into an array of rows and columns, where each column of the array includes both a first compare line and a second compare line coupled to each bitcell included in the column Further, each row of the array includes a match line coupled to each bitcell included in the row, and wherein each match line is configured to indicate a match, during a first mode of operation, between compare data received via the first and second compare lines with bitcell data stored in the bitcells of a respective row. The program code includes instructions to control a first compare line of a first column of the array to a first logic state while controlling the second compare line of the first column as well as the first and second compare lines of each of the other columns of the array to a second logic state during a second mode of operation, to provide bitcell data stored in at least one bitcell of the first column to a respective match line. The program code also includes instructions to read the bitcell data on the respective match line.
This Summary is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The accompanying drawings are presented to aid in the description of implementations of the technology described herein and are provided solely for illustration of the implementations and not limitation thereof.
The Detailed Description references the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the drawings to reference like features and components.
Commonly, in order to read out the contents of a content-addressable memory (CAM) a dedicated read port is designed into the content-addressable memory (CAM) to facilitate reading and/or testing of the content-addressable memory (CAM). In one aspect, the subject matter disclosed herein is directed to reading and/or testing of the content-addressable memory (CAM) by re-purposing an existing match line in the content addressable memory (CAM) as a bit line and reading out the content addressable memory (CAM) one column at a time. Eliminating the read port saves space because wires that would normally exist coupling the match lines to the read port are eliminated. Eliminating the read port also may improve power consumption because there are fewer wires and components that would dissipate heat.
As shown in
During a compare mode of operation, compare data is received at the drive logic 104 from register 108 and then broadcast from the drive logic 104 to the bitcells 102 via the compare lines (CLT(0)-CLT(X) and CLC(0)-CLC(X)), where the match lines, (ML(0)-ML(Y)), then indicate whether the compare data matches the bitcell data stored in the bitcells of a respective row. Thus, during the compare mode of operation, compare data is broadcast to each bitcell of a respective row, where the match line then indicates whether the compare data matches the row's word. Each match line is also coupled to a respective sense logic 106 for reading out the result of the compare operation.
In some situations, there may be a need to provide the capability to actually read out the bitcell data stored in one or more of the bitcells. These situations may include the testing of the CAM, such as to verify the hardware is working correctly or for debugging associated software. However, common solutions for reading out the bitcell data include adding dedicated read ports to the bitcells. For example,
As shown in
In one embodiment, CAM 100 is a subsystem included within a larger electronic system. The electronic system may be a mobile phone, a computer, a digital camera, a medical device, or otherwise, and may further include a computing or processing unit for system level operation or other functionality of the electronic system. For example, the electronic system may be a mobile phone that also includes a central processor unit and radio frequency or microwave electronics for wireless communications.
As further shown in
During a compare mode of operation, pre-charge logic 224 pre-charges the match line ML(0) to a logic HIGH state, putting it temporarily in a state indicating a match. Drive logic (e.g., drive logic 104 of
Similarly, compare port 220 compares the true bitcell data on first compare data output 210 with the complementary compare data on compare line CLC(1), while compare port 218 compares the complementary bitcell data on the second compare data output 212 with the true compare data on compare line CLT(1).
In one aspect, the true bitcell data at one compare port (e.g., compare port 206) and the complementary bitcell data at a corresponding compare port (e.g., compare port 208) of the same bitcell storage (e.g., 202) may be referred to as a bitcell data pair (e.g., (1,0) or (0,1)). Similarly, the true compare data provided by one compare line (e.g., CLT(0)) and the complementary compare data provided by a corresponding compare line (e.g., CLC(0)) of the same column may be referred to as a compare data pair (e.g., (1,0) or (0,1)). In one embodiment a mismatch refers to the true bitcell data of one bitcell data pair not matching the true compare data of a corresponding compare data pair and/or the complementary bitcell data not matching the corresponding complementary compare data.
However, as mentioned above, each of the compare ports 214 and 218 are coupled to compare the complementary bitcell data with the true compare data and each of the compare ports 216 and 220 are coupled to compare the true bitcell data with the complementary compare data. Thus, compare port 214 (and 218) is configured to control the transistors 226 and 228 within the compare port 214 to allow the match line ML(0) to remain in the logic HIGH state indicating a match if the complementary bitcell data at the compare data output 208 is not the same as true compare data received via the compare line CLT(0). For example, if the complementary bit cell data provided at compare data output 208 is a logic HIGH (e.g.,
In the case of a mismatch between data pairs, the compare port 214 controls the transistors 226 and 228 to effectively pull the match line ML(0) to a logic LOW state (e.g., ground) indicating the mismatch. A mismatch may be indicated if the complementary bit cell data at the compare data output 208 is the same as the true compare data. That is, it follows that if
In one embodiment, the transistors (e.g., 226 and 228) within each compare port 214, 216, 218, and 220 are n-channel field-effect transistors (nFET). Thus, in one example a compare port may indicate a mismatch by pulling the match line ML(0) to the logic LOW state only if both the bitcell data and the compare data received at the compare port are a logic HIGH (e.g., “1”).
A mismatch between any of the bitcell data pairs stored in this row and the compare data pairs provided will cause the match line ML(0) to transition to the logic LOW state, thus indicating a mismatch. If, however, the compare data pairs broadcast on each compare line matches with their respective stored bitcell data pairs, then match line ML(0) will remain in its pre-charged logic HIGH state indicating a match. Thus, during the compare mode of operation, the state of the match line, after the comparison operation is then read out by sense logic 222 via match line ML(0).
In addition to the compare mode of operation, discussed above, embodiments disclosed herein include a second (e.g., read) mode of operation for reading out the bitcell data stored in the bitcells. As further discussed above, this is achieved without the addition of dedicated read port circuitry and instead includes the reading out of bitcell data via the existing match lines (e.g., ML(0)).
In one aspect, reading out bitcell data stored in a CAM includes controlling a first compare line of a first column of the array to a first logic state while controlling the second compare line of the first column, as well as the first and second compare lines of each of the other columns of the array, to a second logic state during the read mode of operation. Thus, during a read operation of the first column of the array, the first compare line of the first column is the only compare line of the array that is enabled (i.e., each of the other compare lines included in the array are disabled). Doing so, allows the match lines to serve as a bit line for allowing the bitcell data to then be read out via existing sense logic.
By way of example, attention is again directed to
Returning now back to
As shown in
During the compare mode of operation, the compare data is provided by way of the DATA/INDEX signal, where logic gate 404 provides the true compare data to first compare line CLT(n) and where logic gate 408 controls logic gate 406 to provide the complementary compare data to compare line CLC(n).
The operation of drive logic 402 in conjunction with the bitcells of
Similarly, at time T1, the respective drive logic 402 associated with column 1 receives a DATA/INDEX signal that is a logic LOW state, indicating that column 1 is not selected for a read operation. Thus, the drive logic 402 for column 1, controls both the compare line CLT(1) and the compare line CLC(1) to the logic LOW state. With CLT(0) at the logic HIGH state and CLC(0), CLT(1), and CLC(1) at the logic LOW state, bitcell data stored in bitcell storage 202 is provided onto match line ML(0), as shown in
Next, a read operation of column 1 is commenced at time T3 coinciding with the beginning of another clock cycle 504. At time T3, the READ MODE signal remains in the logic HIGH state, still indicating the read mode of operation. Also, between time T2 and time T3, pre-charge logic 224, again, precharges the match line ML(0) to the logic HIGH state such that the match line ML(0) is precharged by time T3. Further, at time T3, the drive logic 402 associated with column 0 receives a DATA/INDEX signal that transitions to a logic LOW state, indicating that column 0 is not selected for a read operation. Thus, the drive logic 402 for column 0, controls the both the compare line CLT(0) and the compare line CLC(0) to a logic LOW state.
Similarly, at time T3, the drive logic 402 associated with column 1 receives a DATA/INDEX signal that is a logic HIGH state, indicating that column 1 is now selected for a read operation. Thus, the drive logic 402 for column 1, controls the compare line CLT(1) to the logic HIGH state and the compare line CLC(1) to the logic LOW state. With CLT(1) at the logic HIGH state and CLC(1), CLT(0), and CLC(0) at the logic LOW state, bitcell data stored in bitcell storage 204 is provided onto match line ML(0), as shown in
Aspects of the technology described herein and related drawings are directed to specific implementations of the technology. Alternative implementations may be devised without departing from the scope of the technology described herein. Additionally, well-known elements of the technology will not be described in detail or will be omitted so as not to obscure the relevant details.
Although steps and decisions of various methods may have been described serially in this disclosure, some of these steps and decisions may be performed by separate elements in conjunction or in parallel, asynchronously or synchronously, in a pipelined manner, or otherwise. There is no particular requirement that the steps and decisions be performed in the same order in which this description lists them, except where explicitly so indicated, otherwise made clear from the context, or inherently required. It should be noted, however, that in selected variants the steps and decisions are performed in the order described above. Furthermore, not every illustrated step and decision may be required in every implementation/variant in accordance with the technology described herein, while some steps and decisions that have not been specifically illustrated may be desirable or necessary in some implementation/variants in accordance with the technology described herein.
Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the implementations disclosed herein may be implemented as electronic hardware or a combination of hardware and software. To show clearly this interchangeability of hardware and hardware and software combinations, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or combination of hardware and software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present technology described herein.
The various illustrative logical blocks, modules, and circuits described in connection with the implementation disclosed herein may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
A method or algorithm described in connection with the aspects disclosed herein may be implemented directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in an access terminal. Alternatively, the processor and the storage medium may reside as discrete components in an access terminal.
The previous description of the disclosed implementations is provided to enable any person skilled in the art to make or use the technology described herein. Various modifications to these implementations will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of the technology described herein. Thus, aspects of the technology described herein are not intended to be limited to the implementations shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
