Patent Application
20160285968
This application relates to integrated circuits, and more particularly to the enumeration of integrated circuits.
A number of digital signaling protocols have been developed to support communication between integrated circuits in a system such as a mobile device. Examples of such digital signaling protocols include general purpose input/output (GPIO) and universal asynchronous receiver transmitter (UART). As technology advances, these various digital signaling protocols have been enhanced. For example, the assignee of the present matter has developed a “virtual” GPIO architecture in which a GPIO finite state machine serializes GPIO data received from a processor through a GPIO interface and transmits the serialized GPIO data over a dedicated transmit pin. Since the processor needs no software modification in that it may continue to interface with the GPIO interface in a conventional fashion as it would to transmit GPIO date over conventional GPIO pins, the virtualizing of the GPIO data is transparent to the processor. The processor thus needs no software or hardware modifications with regard to communication through the virtual GPIO interface. A remote integrated circuit receives the serialized virtual GPIO data over a dedicated receive pin. In addition, each virtual GPIO integrated circuit may include a clock pin to synchronize the VGPIO transmission and reception. In other embodiments, no clock pin is utilized such that there are both two-pin and three-pin virtual GPIO embodiments.
Since there are different digital signaling protocol configurations, it is desirable for a host processor or device in a system to identify the particular configuration being used by the remaining devices in a system during a process denoted as device enumeration. However, existing device enumeration techniques are problematic. For example, one conventional approach to device enumeration involves the burning of fuses or similar one-time-programmable memories in the various devices within a system. Upon power-up, the system's host device reads the fuse states in the various remaining devices to obtain their enumeration data. Such fuse-based enumeration, however, suffers from the die area demands for the fuses. As an alternative, I/O bootstrapping enumeration involves the tying of dedicated pins to either power or ground to program the enumeration data. I/O bootstrapping thus increases packaging costs and requires additional components on the circuit board. Finally, firmware has been used for enumeration but this also increases die demands and complexity.
Accordingly, there is a need in the art for improved enumeration techniques.
An enumeration technique is provided that requires no pre-assignment of addresses to slave devices connected through point-to-point (P2P) links to a host device. With regard to any P2P link between devices, one device has a master interface and the remaining device has a slave interface. To distinguish between the master and slave interfaces, a master/slave status bit may be used. Each P2P link has a link ID that may be concatenated with the status bit for a corresponding interface (slave or master) to form a node ID. Each master interface and slave interface may be deemed to comprise a “node” having the corresponding node ID that is a concatenation of the master/slave status for the node and the link ID for the P2P link coupled to the node. The host device receives a unique concatenated address from each node in the slave devices that represents a concatenation of the node ID for the node and the node ID for any intervening nodes between the node and the host device. This unique concatenated address is designated in the following discussion as a “host-facing node ID.”
Each P2P link couples between a corresponding slave interface and a master interface. The host-facing node ID for each node is guaranteed to be unique because the P2P links that couple to the master interfaces of a device (host or slave) having more than one master interface are unique. In that regard, each P2P link may have a default link ID that is unchanged if the master interface coupled to the P2P link is the only master interface in the device including the master interface coupled to the P2P link. A device including more than one master interface includes a state machine designated herein as a “node aggregator” that is configured to assign a unique link ID to each P2P link coupled to one of the multiple master interfaces. For example, if a device includes two or more master interfaces, the node aggregator may leave one of the master interface's P2P link with its default link ID but change the remaining master interface's P2P links to each have a unique changed link ID such that each link ID for the device's master interfaces' P2P links are unique. This uniqueness then guarantees that the host-facing node IDs for each node will in turn be unique.
Given the unique host-facing node IDs, the host device then assigns a bit-optimized address such as a unique Cartesian address to each slave device, wherein each Cartesian address comprises an X address and a Y address. Routing through the resulting network of slave devices may be performed using the Cartesian addresses without the complication of routing tables.
Embodiments of the disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
Enumeration systems and methods are provided that eliminate the need for pre-assigning an address to any given device. The complexity and die area demands of conventional enumeration techniques such as the use of fuses, I/O bootstrapping, or firmware are thus advantageously reduced or eliminated. To provide these advantageous properties, a host device includes one or more point-to-point (P2P) interfaces for communicating with a plurality of slave devices. Although there is only one host device, the slave devices themselves may be sub-hosts with respect to other slave devices over corresponding P2P interfaces. Within the resulting system, the direct physical connection (the P2P connection) between any two nodes is not shared with any other node. Since the P2P connection between such nodes is thus unique, no pre-assignment of addresses is required.
The enumeration of the slave devices by the host device occurs over two stages. In a first enumeration stage, the host obtain the “raw addresses” of the slave devices. As will be explained further herein, a raw address represents a concatenation of a device's status (slave or master) and a link ID. Note that a slave device may link through another slave device to the host device or integrated circuit (as used herein, “device” and “integrated circuit” are used interchangeably). For example, a first slave device may link through a second slave device to the host device. With regard to the first slave device, the second slave device is a master device, which simply means that the second slave device is a “host-facing” device with respect to the P2P link between the first and second slave devices. The host device itself is of course the ultimate “host-facing” device as it is always the master device on its P2P links with the associated slave devices.
With regard to the P2P links from a master device to its slaves, each link has a unique ID. The default ID for each P2P link may be given some binary value such as zero. Upon the initiation of enumeration, the host device determines how many P2P links it has. One of its P2P links will retain its default ID whereas the remaining links are given their own unique binary ID by the host device. A “Cartesian” addressing technique will be discussed further herein that is particularly advantageous because no routing tables are then required in the slave devices. As suggested by the designation of “Cartesian,” each resulting assigned address is actually a pair of addresses. A first one of the addresses in each pair is deemed to be the “X” coordinate whereas a remaining address in each pair is deemed to be the “Y” coordinate. Each Cartesian address is thus formed by an (X,Y) pair of addresses. The first address in the pair may be deemed to be the equivalent of the x coordinate in a Cartesian coordinate system whereas the second address in the pair may be deemed to be the equivalent of the y coordinate in a Cartesian coordinate system However, a single address may be assigned to each slave device in alternative embodiments such as through the assignment of successive binary values although will be appreciated that non-consecutive numbering schemes may be used so long as each P2P link to the host is assigned a unique link ID. To distinguish those slave devices having a direct P2P link with the host device as compared to those slave devices that must link to the host device through other slave devices, the slave devices having the direct P2P link with the host device are denoted as “first-hop” slave devices. Responsive to an enumeration initiation, the host device signals to each first-hop slave device what the link ID will be for the P2P link between the first hop slave device and the host device.
Slaves devices that must couple through another slave device to communicate with the host device are by definition not first-hop slave devices. A slave device that intervenes between an non-first-hop slave device and the host device acts as a master device with regard to the non-first-hop slave device. Such “master” slave devices may have more than one slave device having a direct P2P link to the master slave device. A master slave device will then be triggered by the initiation of the enumeration to communicate to each slave device having a P2P link to the master slave device the corresponding link ID for the P2P link. With respect to any given slave device (regardless of whether it acts as a master device to another slave device), there is only one master device with which it has a P2P link. Each slave device has a slave interface through which it interfaces with its master device over the corresponding P2P link. With the link IDs all assigned, each slave device may then report to its master device a “node ID” for its slave interface that is a concatenation of its status as a slave and the link ID for the P2P link between the slave device and the master device. For example, a slave status may be represented by a binary zero that is then concatenated with the link ID to form the node ID.
Each master slave device has an interface for each P2P link through which it directly couples to other slave devices. This interface may be denoted as a master interface since it serves another slave device. Such a master interface may be given a node ID that is a concatenation of the corresponding link ID and its status as a master. For example, a master status may be represented by a binary one that is then concatenated with the link ID to form the node ID for the master interface. In turn, the master slave device has a slave interface for the P2P link through which it communicates with its master device. For example, the master device to a first-hop slave device would be the host device itself. So the interface in the first-hop slave device for the P2P link to the host device is a slave interface and is given a slave status accordingly.
The resulting formation of the various node IDs may be better appreciated with regard to an example system 100 shown in
Given this 7-bit width for the link IDs, the assignment of the node IDs for each interface 135, 130, 125, and 120 may occur as follows. The default link ID for each of P2P links 140 and 145 is [0 00 00 00]. The one-bit status as slave or master for each interface is concatenated with this link ID to form the resulting node ID. A slave status is represented by a 0 bit whereas a master status is represented by a 1 bit. For example, the node IDs for both slave interfaces 130 and 120 is [00 00 00 00]. In contrast, the host-facing node IDs for master interfaces 135 and 125 is [10 00 00 00]. Given this assignment of node IDs for each interface (slave or master), a “host-facing node ID” is determined for each interface. The host-facing node ID is the concatenation of each node ID from a given slave device to host device 105. For example, the host-facing node ID for first-hop slave device 110 is [00 00 00 00 10 00 00 00]. In contrast the host-facing node ID for slave device 115 is [00 00 00 00 10 00 00 00 00 00 00 00 10 00 00 00]. The formation of host-facing node IDs for each slave device is quite advantageous because the host-facing node IDs are guaranteed to be unique despite there being no pre-existing assignment of IDs to the devices such as through the use of fuses or boot-strapping I/O. Thus, system 100 is much more compact and less expensive as compared to conventional enumeration systems.
Each master interface and slave interface may comprise a virtual GPIO (VGI) interface such as shown in
Each hybrid virtual GPIO FSM 117 monitors the GPIO state changes discussed below. At a power-on reset (POR) for the corresponding integrated circuit, each UART interface 116 may be configured to use the same baud rate and same settings for the virtual GPIO frame length and messaging signal frame length. Each UART interface 116 may also be software configured by the corresponding integrated circuit's processor (CPU) 102 as indicated by the CPU link to each UART interface 116.
Each processor 102 is configured to transmit and receive GPIO signals through a corresponding GPIO interface 103. In particular, each processor 102 may present a transmit set of GPIO signals to the corresponding GPIO interface 103 for transmission to the remote processor. Similarly, each processor 102 may receive a receive set of GPIO signals from the corresponding GPIO interface 103 as transmitted from the remote processor. With regard to the transmit set of GPIO signals, a first portion of the GPIO signals may be transmitted and received on conventional GPIO pins 126 as GPIO signals 131. For illustration clarity, only four GPIO signals 131 are labeled in
In addition, each processor 102 may write a transmit set of messaging signals to a set of messaging registers 136 in the corresponding hybrid virtual GPIO FSM 117. Each messaging register 136 corresponds to a particular address 137 for a corresponding message signal 138. In system 104, each hybrid virtual GPIO FSM 117 is shown having a plurality of (M+1) messaging registers ranging from a zero register 136 to an Mth register 136. The value of the positive integer M may vary depending upon the needs of a given implementation. Each hybrid virtual GPIO FSM 117 presents its transmit set of messaging signals and the transmit set of virtual GPIO signals to the corresponding UART interface 116 that is explained further below. Note that virtual GPIO signals 139 do not each have their own dedicated pins as is the case for conventional GPIO signals 130. This is quite advantageous in that hybrid virtual GPIO system 104 achieves a significant reduction of pins for integrated circuits 101 and 106 as compared to a conventional GPIO embodiment in which virtual GPIO signals 139 would each require their own GPIO pin.
Since virtual GPIO signals 139 and messaging signals 138 are transmitted and received through a finite state machine such as hybrid virtual GPIO FSM 117, processor 102 may be asleep or in another type of dormant state yet still be able to receive virtual GPIO signals 139 and messaging signals 136. In this fashion, hybrid virtual GPIO system 104 not only advantageously economizes the number of pins for each GPIO interface 103 but is also low power. With regard to each processor 102, there is no difference between GPIO signals 130 and virtual GPIO signals 139: they are both treated as GPIO signals that are transmitted and received as necessary through GPIO interface 103.
A processor 102 may need to receive an interrupt signal in response to changes in selected ones of virtual GPIO signals 139. For example, a modem power manager (MPM) 140 may monitor the state of selected virtual GPIO signals 139 such as programmed through interrupt configuration registers (not illustrated). Each virtual GPIO signal 139 may have a corresponding interrupt configuration register. Should a virtual GPIO signal 139 be required to generate an interrupt in response to that signal changing state, the corresponding configuration register would be programmed accordingly. Similarly, should a virtual GPIO signal 139 be one that does not generate an interrupt regardless of whether that signal has changed state, the corresponding interrupt configuration register would also be programmed accordingly. MPM 141 may also comprise a finite state machine. Thus, just like hybrid virtual GPIO FSM 117, MPM 141 is low power and is active regardless of whether its processor 102 is in a sleep mode or some other dormant state.
Virtual GPIO signals 139 may be subdivided into a transmit set and a receive set. Similarly, messaging signals 136 may be subdivided into a transmit set and a receive set. In a symmetric system, each set would have the same number. However, it will be appreciated that hybrid virtual GPIO system 104 is advantageous in that it can readily accommodate an asymmetric signaling embodiment in which the transmit and receive sets of virtual GPIO signals 139 and messaging signals 136 have different sizes. Regardless of whether system 104 is symmetric or asymmetric, each hybrid virtual GPIO FSM 117 receives the transmit set of virtual GPIO signals 139 in parallel from GPIO interface 103 in that each signal in the transmit sets is carried on its own lead (not illustrated) between GPIO interface 103 and the corresponding hybrid virtual GPIO FSM 117. In contrast, the resulting transmission of the transmit sets by hybrid virtual GPIO FSM 117 takes place over a single transmit pin 111
Comparing network 100 to hybrid virtual GPIO system 104, it may be seen that master interface 135 in host IC 101 is formed by hybrid virtual GPIO FSM 117 and UART 116 as well as MPM 141. The collection of hybrid virtual GPIO FSM 117, UART 116, and MPM 141 form an implementation of a VGI interface. Similarly, slave interface 130 in slave IC 106 is formed by the same components. Each hybrid virtual GPIO FSM 117 may be configured to practice the enumeration techniques discussed herein. The leads between pins 111 and 112 form a P2P link 140 between host IC 101 and slave IC 106.
Another example system 200 is shown in
Each interface in each device may be designated as a “node” regardless of whether the interface is a master interface or a slave interface. First-hop slave devices 250, 255, and 265 thus have two node IDs: one for their slave interface, and another for their master interface. In system 200, first-hop slave 250 includes a slave interface 245 for P2P link 225. The node ID for slave interface 245 is thus the concatenation of its slave status such as represented by a zero bit [0] with the link ID link-0 [00 00 00 0] for P2P link 225. The node ID for slave interface 245 is thus [00 00 00 00]. First-hop slave 250 serves as a master slave device for a slave device 290 and a slave device 201 through P2P links 275 and 206, respectively. First-hop slave 250 includes a master interface 280 for P2P link 275 and a master interface 282 for P2P link 206. Since there are two master interfaces in first-hop slave 250, it will include a node aggregator (not illustrated) such as node aggregator 202 discussed with regard to host device 205 for assigning a link-0 ID to P2P 275 and a link-1 ID to P2P link 206. The node ID for master interface 282 is thus the concatenation of its status as master such as represented by a one bit [1] with the link ID link-1 of [00 00 00 1]. The node ID for master interface 282 is thus [00 00 00 11]. Similarly, the node ID for master interface 280 is [00 00 00 01]. Note that it doesn't matter what order the concatenation is formed in so long as it is consistent for all the nodes.
On their face, the link IDs (Link-0 and Link-1) for P2P links 275 and 206 are identical to the ones used for P2P links 225 and 230, respectively. But that does not matter since the resulting node IDs will still be unique in system 200. Slave device 290 includes a slave interface 295 for P2P link 275. Similarly, slave device 201 includes a slave interface 211 for P2P link 206.
The final host-facing ID for a given node is thus the concatenation of the node ID for the given node with the node IDs of all intervening nodes between the given node and the host device. For example, the host-facing ID for slave interface 295 is the concatenation of its node ID with the node ID for master interface 280, slave interface 245,1 and master interface 210. For brevity, the node ID for each master or slave interface in
Note that first-hop slave 265 is analogous to first-hop slave 250 in that first-hop slave 265 includes two master interfaces 231 and 236 for corresponding P2P links 226 and 241, respectively. First-hop slave 265 also includes a slave interface 270 for P2P link 240 to host device 205. Since first-hop slave 265 couples to two additional slave devices, first-hop slave 265 would thus also include a node aggregator (not illustrated) such as discussed with regard to node aggregator 202 for assigning a link-0 ID to P2P link 226 and for assigning a link-1 ID to P2P link 241. P2P link 226 couples to a slave interface 251 in a slave device 246. Similarly, P2P link 241 couples to a slave interface 261 in a slave device 256. The link ID assignment for P2P link 226 is thus communicated to slave interface 251 from first-hop device 265. Similarly, the link ID assignment for P2P link 241 is communicated to slave interface 261.
P2P links 226 and 241 have the same link IDs as used for P2P links 275 and 206 coupled to first-hop slave 250. But this overlap of link IDs does not matter as the resulting assignment of host-facing IDs to the various nodes is guaranteed to be unique because of the different link IDs assigned to P2P links 225 and 240. Slaves 246 and 290 are both “end point” slave devices in that these slave devices do not act as a master device to additional downstream slaves. The node ID for first-hop master interfaces 280 and 231 and also for a first-hop master interface 216 in first-hop slave device 255 is each 0x80 whereas the node ID for first-hop master interfaces 282 and 236 is 0x81. The concatenation of the node ID for slave interface 295 with the node ID for master interface 280 and also the concatenation of the node ID for slave interface 251 with the node ID for master interface 231 will thus both be 0x00, 0x80. Similarly the concatenation of the node ID for slave interface 211 with the node ID for master interface 282 and also the concatenation of the node ID for slave interface 261 with the node ID for master interface 236 will both be 0x01, 0x81.
But such identical partial concatenation results become unique upon further concatenation. For example, note that first-hop slave device 250 couples to host device 205 over a Link-0 ID whereas first-hop slave device 265 couples through a Link-2 ID to host device 205. Despite the partial concatenations being the same, the final host-facing node IDs for slave interfaces 295 and 251 will thus be different. Specifically, the host-facing node ID for slave interface 295 in end-point slave device 290 is 0x00, 0x80, 0x00, 0x80. In contrast, the host-facing node ID for slave interface 251 in end-point slave device 246 is 0x00, 0x80, 0x02, 0x82. Similarly, the host-facing node ID for slave interface 211 in slave device 201 is 0X01, 0X81, 0X00, 0X80 whereas the host-facing node ID for slave interface 261 in slave device 256 is 0X01, 0X81, 0X02, 0X82. In this fashion, all the nodes (whether the node is a master interface or a slave interface) end up with unique host-facing node IDs. Note that slave device 256 interfaces with a plurality of I/O terminals 266.
First-hop slave device 255 couples through first-hop master interface 216 over a P2P link 221 to a slave interface 276 having a node ID 0X00 in a master slave device 271. In turn master slave device 271 includes a master interface 281 having a node ID 0X80 couples though a P2P link 289 to a slave interface 291 having a node ID 0X00 in an end-point slave device 286. The physical topology of a given P2P link may vary. For example, each P2P link may comprise either a 2-wire or a 3-wire virtual GPIO link. Alternatively, a P2P link may comprise a cable such as illustrated for P2P link 221.
Although the resulting host-facing node IDs are all unique, note that they are relatively long and will thus involve some latency with regard to signaling involving such relatively lengthy addresses. Node aggregator 202 in host device 205 (or some other suitable state machine) may thus re-assign a bit-optimized address to each slave device. The host-facing node IDs may thus also be designated as “intermediate” addresses in that they may be replaced with corresponding bit-optimized addresses. Referring again to system 200, there are nine separate slave devices that will have a corresponding intermediate address determined through the concatenation process discussed above. Since there are nine such intermediate addresses, the various slave devices may instead be identified using at least a four-bit-wide (or greater) bit-optimized address. The resulting bit-optimized address assignment is quite advantageous in that no pre-determined addresses are required such that no fuses of I/O boot-strapping is necessary. In addition, the bit-optimized address assignment results in low-latency signaling between host device 205 and its slave devices.
After each node (master interface or slave interface) in the slave devices is assigned a host-facing node ID, node aggregator 202 in the host device may then proceed to address the nodes using their host-facing node IDs so that a more bit-optimized address may be assigned to each node. Processor 102 in host IC 101 of
The assignment of node IDs in network 100 of
An example method of address assignment will now be discussed with regard to the flowchart of
The method also includes an act 305 of counting the number of node IDs to determine the minimum number of bits necessary to uniquely identify each slave interface. The counting by node aggregator 202 in host device 205 is an example of act 305. The minimum number of bits is then equal to the integer value of log2(count), where count is the number of node IDs. In alternative embodiments, the bit-optimized address may include more bits than the integer value of log2(count).
The method also includes an act 310 of addressing each slave interface with a first message including the slave interface's node ID to assign a bit-optimized address to the slave interface that is at least the minimum number of bits wide. The assignment of the bit-optimized addresses to the first-hop slave devices by node aggregator 202 of host device 205 is an example of act 310.
Finally, the method includes an act 315 of addressing each slave interface with a second message including the slave interface's bit-optimized address to enumerate the slave interface. For example, each first-hop slave device's slave interface may identify its status as a 2-wire or 3-wire virtual GPIO interface as part of the enumeration in act 310 in a virtual GPIO implementation. Other examples of enumeration include the assignment of a frame length for the VGI interface in the slave and master interfaces for the slave devices. In addition, the enumeration may assign an error correction algorithm for each VGI interface as well as a flow control technique.
The assignment of the bit-optimized address to each node may be specialized to assist the routing of messages through nodes. Such slave-to-slave communication will in general involve the user of a routing table that is stored in each slave device. A “Cartesian” address assignment for the nodes in the slave devices will now be discussed that is not bit-optimized but results in greatly simplified routing through the slave devices at the cost of a slight decrease in bit efficiency with regard to the resulting assigned addresses. By a simple address comparison, each slave device node may route a received packet from another slave device (or from the host device) such that the appropriate destination is always achieved.
As implied by the name “Cartesian,” each address in a Cartesian address assignment comprises two ordered addresses (i.e., two numbers). It will be appreciated, however, that Cartesian addressing in alternative embodiments may be based on N coordinates in an N-dimensional space, N being an integer greater than 2. The following discussion will thus be directed to a 2-dimensional Cartesian addressing implementation without loss of generality. The first address in each address pair is denoted herein as the X address whereas a remaining second address in each address pair is denoted as the Y address. Each Cartesian address pair thus comprises an (X,Y) pair of addresses. The Cartesian addressing begins from some root address such as (0,0) for the host device itself. The Y address indicates the number of hops from the host device. For example, slave devices having a Y address of 1 have a direct P2P link to the host. Since these slave devices are directly coupled to the host device, they may also be denoted as “level 1” slave devices. Similarly, slave devices having a Y address of 2 are one hop removed from the slave through a connection though a level 1 slave device. Those slave devices having a Y address of two may thus be designated as “level 2” slave devices. Additional increments of the Y address corresponding to additional hops from the host device: Level 3 slave devices have a Y address of 3, level 4 slave devices have a Y address of 4, and so on.
The X address relates to a slave device's position in a given cluster. As used herein, a “cluster” of slave devices are all those slave devices that indirectly couple to the host device through the same level 1 slave device. An example organization of clusters for a network 400 is shown in
With regard to the assignment of the X address, a first level 1 slave device such as device 405 may be given an X address of 1 (or some other starting integer). This same starting X address is then given to all slave devices directly or indirectly coupled to slave device 405 until a Y level is reached in which a slave device couples to more than one slave device in the subsequent Y level. In network 400, level 2 slave device 415 acts as a master device to level 3 slave device 410 as well as to another level 3 slave device 420. Slave device 410 may thus be given the same starting X address as used for level 2 slave device 415 but level 3 slave device 420 requires a higher X address such as the starting address plus one (in this case, 2). The Cartesian address for level 3 slave device 410 is thus (1,3) whereas it is (2,3) for level 3 slave device 420. Level 3 slave device 420 in turn acts as a master device to a first level 4 slave device 425 and to a second level 4 slave device 430. Slave device 425 may thus have a Cartesian address of (2,4) whereas slave device 430 may have a Cartesian address of (3,4). There are no further hops from slave devices 425 and 430.
Cluster 1 has another level 2 slave device 435 with a direct P2P link to level 1 slave device 405. The X address for this slave device is incremented from the highest already-existing X address in the cluster (which is 3 for level 4 slave device 430). Thus level 2 slave device 435 may be assigned an X address of 4. The Cartesian address for level 2 slave device 435 is thus (4,2). The same X address of 4 may be given to a directly-coupled level 3 slave device 440 and to a level 4 indirectly-coupled slave device 445. Level 3 slave device 440 also acts as a master to another level 4 slave device 455 so this slave device has an incremented X address from slave device 440 (namely, an X address of 5). Another level 3 slave device 450 couples to level 2 slave device 435 through a corresponding P2P link. The X address for slave device 450 is thus incremented by one with respect to the greatest already-existing X address in the cluster such that the X address for slave device 450 may equal 6 (an increment of one over the X address of 5 for slave device 455).
Once all slave devices in cluster 1 have been assigned a Cartesian address, a second cluster (cluster 2) may be addressed, starting from a level 1 slave device 460. The X address for level 1 slave device 460 is incremented from the maximum X address in the preceding cluster. Thus, the X address for slave device 460 may equal 7 (an increment of one over the maximum X address of 6 for cluster 1). Two additional slave devices 465 and 470 may also have the same X address as slave device 460 but have incremented Y addresses corresponding to their respective levels. A final slave device 475 has an incremented X address since both it and slave device 470 directly couple to slave device 465.
In contrast to the node IDs discussed with regard to
The assignment of the Cartesian addresses may follow the order indicated in
A level 1 slave device can then route the received message to the host device or upstream within its cluster. This upstream or downstream decision for a level 1 slave device is determined by whether the X address is within the bounds for the corresponding cluster. With regard to cluster 1, it extends from X=1 to X=6. Thus, if level 1 slave device 405 received a message with an X coordinate of 7 or greater, it would route the message downstream to the host device so that the host device may route the message to the appropriate cluster based upon the X coordinate. In the preceding example, the X coordinate for the received message at level 1 slave device 405 is 3 such that level 1 slave device 405 routes the received message to level 2 slave device 415. Note that level 2 slave device 415 has two possible choices for its upstream routing as it can route to either level 3 slave 410 or to level 3 slave device 420. The rule is thus that the upstream routing is conducted to the slave device having the greatest X address that is less than or equal to the X address in the destination Cartesian address. Given this rule, slave device 415 would thus route the message to slave device 420. Slave device 420 also has a choice but under the routing rule would route to level 4 slave device 430. Upon receipt of a message, each slave device checks to see if the destination Cartesian address matches its own. For slave device 430, there would be a match such that the intended slave device would receive its message despite the lack of a routing table in any of the slave devices.
The method also includes an act 505 of assigning a Cartesian address to each of the second slave devices by: assigning a Y address to each second slave devices that is incremented from the first Y address depending upon a number of intervening ones of the second slave device that the second slave device couples through to couple to the first slave device, the number of intervening ones of the second slave devices being zero or greater for each second slave device, and assigning an X address to each second slave device that is incremented from the first X address depending upon whether others of the second slave devices share the same Y address with the second slave device being assigned the X address. The assignment of the X and Y addresses to slave devices 415, 410, 425, and 430 in
Finally, the method includes an act 510 of enumerating the second slave devices by addressing each second slave device with its Cartesian address. The enumeration of the slave devices in
As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
This application claims the benefit of U.S. Provisional Application No. 62/137,687, filed Mar. 24, 2015. In addition, this application claims the benefit of U.S. Provisional Application No. 62/208,312, filed Aug. 21, 2015.
| Number | Date | Country | |
|---|---|---|---|
| 62137687 | Mar 2015 | US | |
| 62208312 | Aug 2015 | US |
