Patent Application
20180226972
The disclosure generally relates low power down-voltage conversion circuits and methods, and more specifically to semiconductor Complementary Metal-Oxide Semiconductor (“CMOS”) circuits adapted to convert an input signal from a first voltage level to an output signal at a second voltage level with reduced power requirements. The novel low power down-voltage conversion circuits and methods are suitable for use in low power microprocessors, microcontrollers, or power management devices.
In general, in the descriptions that follow, the first occurrence of each special term of art that should be familiar to those skilled in the art of integrated circuits (“ICs”) and systems will be italicized. In addition, when a term that may be new or that may be used in a context that may be new, that term will be set forth in bold and at least one appropriate definition for that term will be provided. In addition, throughout this description, the terms assert and negate may be used when referring to the rendering of a signal, signal flag, status bit, or similar apparatus into its logically true or logically false state, respectively, and the term toggle to indicate the logical inversion of a signal from one logical state to the other. Alternatively, the mutually exclusive Boolean states may be referred to as logic_0 and logic_1. Of course, as is well known, consistent system operation can be obtained by reversing the logic sense of all such signals, such that signals described herein as logically true become logically false and vice versa. Furthermore, it is of no relevance in such systems which specific voltage levels are selected to represent each of the logic states.
Hereinafter, reference to a facility shall mean a circuit or an associated set of circuits adapted to perform a particular function regardless of the physical layout of an embodiment thereof. Thus, the electronic elements comprising a given facility may be instantiated in the form of a hard macro adapted to be placed as a physically contiguous module, or in the form of a soft macro the elements of which may be distributed in any appropriate way that meets speed path requirements. In general, electronic systems comprise many different types of facilities, each adapted to perform specific functions in accordance with the intended capabilities of each system. Depending on the intended system application, the several facilities comprising the hardware platform may be integrated onto a single IC, or distributed across multiple ICs. Depending on cost and other known considerations, the electronic components, including the facility-instantiating IC(s), may be embodied in one or more single- or multi-chip packages. However, unless expressly stated to the contrary, the form of instantiation of any facility shall be considered as being purely a matter of design choice.
In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments which may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments and disclosure. It is to be understood that other embodiments may be utilized, and that logical, mechanical, electrical, and other changes may be made without departing from the scope of the embodiments and disclosure. In view of the foregoing, the following detailed description is not to be taken as limiting the scope of the embodiments or disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
It will be appreciated that for simplicity and clarity of illustration, where considered appropriate, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the implementations described herein. However, it will be understood by those of ordinary skill in the art that the implementations described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the implementations described herein. Also, the description is not to be considered as limiting the scope of the implementations described herein.
The detailed description set forth herein in connection with the appended drawings is intended as a description of exemplary embodiments in which the presently disclosed apparatus and system can be practiced. The term “exemplary” used throughout this description means “serving as an example, instance, or illustration,” and should not necessarily be construed as preferred or advantageous over other embodiments.
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As is known, conventional electronic circuits are powered by a voltage applied between two nodes, i.e., the power supply node and the ground node. Furthermore, in many instances, multiple power supplies may be used within a given integrated circuit or electronic facility, each power supply having a voltage different from the others. By way of example, a supply voltage may be provided by a power source such as a battery, e.g., lithium-ion or coin-cell battery. The battery determines the power supply voltage level. This power supply voltage level may be too high or too low for optimal circuit operation, and therefore may require certain adjustments to the voltage supply level. Alternatively, some semiconductor devices such as flash memory cells may require as much as 10 volts (10V) to twenty volts (20V) during a programming operation of the flash memory cells, while the memory read operations of the same may be conducted at a much lower voltage level, i.e., 1.8 volts (1.8V).
SRAM circuits capable of storing digital information are widely used in a variety of mobile and handheld devices, e.g., smart-phones, tablets, laptops, and other consumer electronics products. SRAM facilities may include, without limitation, stand-alone memory circuits, with a dedicated substrate, or embedded memory circuits, where the SRAM circuit shares a substrate with other electronic components.
As is known, MOS transistors have a gate, a source, a drain and a bulk node. As one of ordinary skill in this art would understand, by applying a voltage on the gate the amount of current that can flow from the drain to the source can be modulated. One of the main characteristics of MOS transistors is its threshold voltage. This voltage quantity, in its simplest definition, is the voltage applied on its gate in order to pass current.
In recent years, due to the growth of portable electronics, there has been a push to lower the supply voltage of the circuits used in portable electronic appliances. With a lower supply voltage, and the concomitant reduction in power, smaller batteries may be used. One industry standard technique used in semiconductor devices and their integrated circuits to reduce power is to selectively lower the supply voltage on selected portions of the integrated circuit during a retention mode or standby mode.
In one embodiment, an integrated circuit facility operating in a standby mode having reduced leakage current, said circuit comprising a first circuit comprising a high threshold voltage PMOS device, and a high threshold voltage NMOS device, the first circuit being adapted to operate in response to a first input a first supply voltage, and a first ground voltage, and develop a first output, a second circuit comprising a second PMOS device comprising a source coupled to a second supply voltage, a gate coupled to said first output, and a drain coupled to a second output, and a second NMOS device comprising a source coupled to a second ground voltage, a gate coupled to said first output, and a drain coupled to said second output, wherein if said first output turns on said second NMOS device, said second PMOS device gate-to-source voltage is positively biased, and if said first output turns on said second PMOS device, said second NMOS device gate-to-source voltage is negatively biased.
In another embodiment, an integrated circuit facility operating in a standby mode having reduced leakage current, said circuit comprising a first circuit comprising a high threshold voltage PMOS device, and a high threshold voltage NMOS device, said first circuit being adapted to operate in response to a first input, and a first supply voltage, and develop a first output, and a second circuit comprising a second PMOS device comprising a source coupled to a second supply voltage, a gate coupled to said first output, and a drain coupled to a second output, a second NMOS device comprising a source coupled to a ground supply, a gate coupled to said first output, and a drain coupled to said second output, wherein if said first output turns on said second NMOS device, said second PMOS device gate-to-source voltage is positively biased.
The several embodiments may be more fully understood by a description of certain preferred embodiments in conjunction with the attached drawings in which:
In the drawings, similar elements will be similarly numbered whenever possible. However, this practice is simply for convenience of reference and to avoid unnecessary proliferation of numbers, and is not intended to imply or suggest that identity is required in either function or structure in the several embodiments.
Semiconductor devices may utilize multiple power domains, each power domain with a specified supply voltage level. For power sensitive systems, e.g., battery-powered mobile systems, use of a lower voltage power domain has the advantage of lowering power consumption, as there is less energy spent charging and discharging the nodes of the circuitry inside the power domain. As is known, the energy spent charging a node is proportional to the square of the voltage to which this node is charged. Thus, operating an electronic circuit with a lower voltage tends to reduce or minimize power consumption. A semiconductor device with one or more low-voltage power domains may consume less power than if the semiconductor device did not have the low-voltage power domains.
Semiconductor devices that include multiple power domains and thus multiple logic domains that operate at different supply voltages must communicate across power domain or logic domain boundaries. In order to communicate, or pass signals, from a high voltage power domain to a low voltage power domain, the signals must be converted from high voltage signals to low voltage signals, i.e., the high voltage power domain signal must be level shifted to the low voltage power domain voltage levels.
Voltage conversion is also useful in circuits supporting standby power states. By way of example, many electronic integrated circuits (“IC”) have an active state, where switching of at least some circuit nodes occurs, and a standby state or idle state, where the nodes are idle and are not switching states. Power consumption in the active state is largely determined by the switching current of the transistors that comprise the logic gates and circuit blocks, as well as by the charging and discharging of the capacitive circuit nodes. Contrastingly, the power consumption in the standby state is largely determined by the leakage current, or off current, of the transistors that are inactive or turned off. Leakage current, or off current, is proportional to the size of the device, i.e., the larger the device, the higher the off current. Circuits with a voltage down step may be configured to minimize power consumption in standby. By way of example, a circuit block or logic block operating at a first voltage supply may have output buffers, drivers, or inverters. The power consumption may be reduced or minimized by operating the majority of the circuitry at a first voltage supply, and operating the final output circuit, e.g. buffer, driver, or inverter, at a second, lower voltage.
As is known, CMOS circuitry is built using MOS transistors, NMOS transistors and PMOS transistors. MOS transistors have a gate, a source, a drain and a bulk node. Typically, the current that flows from the drain of a device to the source of a device may be modulated by applying a voltage to the gate of the device. A primary characteristic of a typical MOS device when considering its operation is the threshold voltage of the MOS device, typically abbreviated as Vth. The threshold voltage is the voltage applied between gate and source of a MOSFET that is needed to turn the device on for linear and saturation regions of operation, and thus to pass current through the device. With a sufficiently high supply voltage, circuitry can be build using high threshold voltage MOS devices. One advantage of a high threshold voltage MOS device is that when its gate is turned off, i.e., Vgs is 0 volts, the leakage current from drain to source is very low. Accordingly, the device consumes very little power while in the off state. Generally, however, high threshold voltage MOS device are not efficient when operating in a low supply voltage environment. Signals developed by high threshold voltage MOS devices in a low supply voltage environment are typically of too low a voltage level to allow the high threshold voltage MOS device to pass large amounts of current. This inefficiency in passing large current values negatively effects the switching speeds of the associated MOS devices. As is known, low threshold devices are more effective and efficient in low supply voltage environments, as they are able to pass sufficient current to achieve proper switching speeds. However, low threshold MOS devices typically pass more leakage current when in the off state than their high threshold counterparts.
Placing a MOS device in its respective off state is accomplished by bringing its gate to source voltage (Vgs) to zero volts (0V). In the case of a PMOS device, with its source tied to a supply voltage, applying a voltage to the gate of the PMOS device, where the applied voltage is equal to the supply voltage, effectively brings its Vgs to 0V, thus placing the PMOS transistor into its off state. In the case of a NMOS devices, with its source tied to ground (GND) or zero volts, applying a voltage to the gate of the NMOS device, where the applied voltage is equal to the GND voltage, effectively brings its Vgs to 0V, thus placing the NMOS transistor into its off state. The leakage current for each of the PMOS and NMOS in their off state is commonly known as Toff. By applying a negative Vgs to an NMOS transistor, or by applying a positive Vgs to a PMOS transistor, Ioff may be significantly reduced. By way of example, a positive Vgs applied to a PMOS device may be where the source of the PMOS device is connected to a supply voltage at 0.6 volts, and the gate of the PMOS device is connected to a signal whose voltage is at 0.9 volts. Similarly, by way of example, a negative Vgs applied to an NMOS device may be where the source of the NMOS device is connected to a GND voltage at 0.3 volts, and the gate of the NMOS device is connected to a signal whose voltage is at 0 volts. Other voltage combinations are anticipated.
Referring back to
A similar structure can be developed which will negatively bias the NMOS device of output inverter in the case where the output is high in standby mode, and achieve a similar leakage power reduction.
Embodiments such as these may be utilized in various logic blocks to reduce overall leakage current of a semiconductor device.
Decoders as described above may be utilized in various circuits and logic blocks to reduce the overall leakage current of a semiconductor device.
While these methods and techniques disclosed herein may be used in a variety of circuits within a semiconductor device such as circuit block 302 of
A comparison of
Apparatus, methods and systems according to embodiments of the disclosure are described. Although specific embodiments are illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purposes can be substituted for the specific embodiments shown. This application is intended to cover any adaptations or variations of the embodiments and disclosure. For example, although described in terminology and terms common to the field of art, exemplary embodiments, systems, methods and apparatus described herein, one of ordinary skill in the art will appreciate that implementations can be made for other fields of art, systems, apparatus or methods that provide the required functions. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention.
In particular, one of ordinary skill in the art will readily appreciate that the names of the methods and apparatus are not intended to limit embodiments or the disclosure. Furthermore, additional methods, steps, and apparatus can be added to the components, functions can be rearranged among the components, and new components to correspond to future enhancements and physical devices used in embodiments can be introduced without departing from the scope of embodiments and the disclosure. One of skill in the art will readily recognize that embodiments are applicable to future systems, future apparatus, future methods, and different materials
All methods described herein can be performed in a suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., “such as”), is intended merely to better illustrate the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure as used herein.
Terminology used in the present disclosure is intended to include all environments and alternate technologies that provide the same functionality described herein.
Thus it is apparent that a method and apparatus adapted to size circuits more accurately, in particular we could reduce power consumption of SRAM circuits with such techniques while consuming less power than known prior art has been disclosed. Further, we submit that our method and apparatus provides performance generally superior to the best prior art techniques.
This application is related to U.S. Provisional Patent Application Ser. No. 62/454,745, filed Feb. 4, 2017, entitled Low Power Buffer with Voltage Conversion (the “Parent Provisional Application”). This application claims priority to the Parent Application and hereby claims benefit of the filing dates thereof pursuant to 37 CFR § 1.78(a)(4). The subject matter of the Parent Application is expressly incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 62454745 | Feb 2017 | US |
