1. Field
The present disclosure relates generally to a circuit, and more particularly, to a low power divide-by-seven divider circuit.
2. Background
High speed divide-by-seven dividers may be used in transmitters/receivers of user equipment (UE) to support wireless communications. Existing divide-by-seven dividers have a relatively high power consumption. Divide-by-seven dividers with a lower power consumption than existing divide-by-seven dividers are needed to reduce UE power consumption in wireless communications.
In an aspect of the disclosure, a divide-by-seven divider apparatus includes a first module clocked with a clock input, and a second module coupled to the first module and clocked with an output of the first module. The first module and the second module are configured to divide the clock input by seven and to output the divided clock input. In particular, the first module may be configured to store a count between 0 and 3 in a count cycle. The divide-by-seven divider may further include a feedback module coupled between the first module and the second module that is configured to cause the first module to skip one count in the count between 0 and 3 once every other count cycle. Specifically, the first module may be configured to store incrementally the count “00,” “10,” “11,” and “01” in a count cycle and to skip the count “01” every other count cycle based on input from the feedback module.
In an aspect of the disclosure, a method of operating a divide-by-seven divider apparatus and a divide-by-seven divider apparatus are provided. The divide-by-seven divider apparatus stores a count between 0 and 3 in a count cycle within a first module. The first module is clocked with a clock input. The divide-by-seven divider apparatus clocks a second module with an output of the first module. The second module is coupled to the first module. The divide-by-seven divider apparatus causes, by a feedback module, the first module to skip one count in the count between 0 and 3 once every other count cycle. The feedback module is coupled between the first module and the second module. The first module, the second module, and the feedback module are configured to divide the clock input by seven. The divide-by-seven divider apparatus outputs the divided clock input.
The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring such concepts. Apparatuses and methods will be described in the following detailed description and may be illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, elements, etc.
High speed divide-by-seven dividers may be used in transmitters/receivers of UE to support wireless communications. Divide-by-seven dividers may include data/delay (D) flip-flops (DFFs). Such DFFs may each be clocked at full speed by an input clock, which results in a higher power consumption by each of the DFFs. Further, divide-by-seven dividers may include a feedback path from the most divided-down logic (lowest speed) to the first stage input (highest speed). The feedback signal in such a feedback path needs to match the input clock speed, resulting in a higher power consumption of logic gates in the feedback path. Accordingly, existing divide-by-seven dividers have a relatively high power consumption. Exemplary divide-by-seven dividers are provided infra with a lower power consumption than existing divide-by-seven dividers.
The TX encoder 108, the preemphasis/equalizer block 110, the TX driver 112, and the RX Decoder 128 each receive a clock input. Divide-by-seven dividers 140 and 142 also receive the clock input. The divide-by-seven dividers 140, 142 divide the received clock input by seven and provide a divided-by-seven clock input to the multiplexers/demultiplexers of the SerDes. Specifically, the divide-by-seven divider 140 receives a clock input, divides the received clock by seven (i.e., the period is seven times larger), and provides the divided-by-seven clock to the 16-to-7 multiplexer 104 and the 7-to-1 multiplexer 106. In addition, the divide-by-seven divider 142 receives a clock input from the re-time and sampler block 126, divides the received clock by seven, and provides the divided-by-seven clock to the 1-to-7 demultiplexer 130 and the 7-to-16 demultiplexer 132. Each of the divide-by-seven dividers 140 and 142 may be the divide-by-seven divider as provided infra in relation to
Each of the DFFs may include a master latch and a slave latch. On a rising edge of the clock, the master latch may store an input bit. On a falling edge of the clock, the master latch may output the stored bit to the slave latch and the slave latch may store the bit inputted by the master latch. The bit stored in the slave latch is outputted by the DFF.
A method of operation of the illustrated divide-by-seven divider will now be described. Assume the first DFF 214, the second DFF 216, and the third DFF 220 are in state 000 in which each are outputting a 0. While in state 000, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 1, 0, and 1, respectively. In a next clock transition (rise and fall of the clock), the first DFF 214, the second DFF 216, and the third DFF 220 are in state 100 in which the first DFF 214 is outputting a 1, the second DFF 216 is outputting a 0, and the third DFF 220 is outputting a 0. While in state 100, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 1, 1, and 1, respectively. In a next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 are in state 110 in which the first DFF 214 is outputting a 1, the second DFF 216 is outputting a 1, and the third DFF 220 is outputting a 0. While in state 110, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 0, 1, and 1, respectively. In a next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 are in state 010 in which the first DFF 214 is outputting a 0, the second DFF 216 is outputting a 1, and the third DFF 220 is outputting a 0. While in state 010, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 0, 0, and 1, respectively. In a next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 are in state 001 in which the first DFF 214 is outputting a 0, the second DFF 216 is outputting a 0, and the third DFF 220 is outputting a 1. The output 242 of the third DFF 220 changed from a 0 to a 1 because the output 238 of the first module 202/second DFF 216 changed from a 1 to a 0, and therefore the bit 1 stored in the master latch of the third DFF 220 was moved to the slave latch of the third DFF 220. While in state 001, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 1, 0, and 0, respectively. In a next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 are in state 101 in which the first DFF 214 is outputting a 1, the second DFF 216 is outputting a 0, and the third DFF 220 is outputting a 1. While in state 101, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 1, 1, and 0, respectively. In a next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 are in state 111 in which the first DFF 214 is outputting a 1, the second DFF 216 is outputting a 1, and the third DFF 220 is outputting a 1. While in state 111, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 0, 0, and 0, respectively. In a next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 return to state 000. Specifically, in the next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 are in state 000 in which the first DFF 214 is outputting a 0, the second DFF 216 is outputting a 0, and the third DFF 220 is outputting a 0. The output 242 of the third DFF 220 changed from a 1 to a 0 because the output 238 of the first module 202/second DFF 216 changed from a 1 to a 0, and therefore the bit 0 stored in the master latch of the third DFF 220 was moved to the slave latch of the third DFF 220.
Referring to when the first DFF 214, the second DFF 216, and the third DFF 220 are in state 111, both of the inputs of the feedback module 206 are 1, thus providing a feedback out signal of a 1. The feedback out signal of a 1 forces the input 236 of the second DFF 216 to a 0. Thus, the first DFF 214, the second DFF 216, and the third DFF 220 receive as inputs 0, 0, and 0, respectively, rather than inputs 0, 1, and 0, respectively. With inputs 0, 1, and 0, respectively, at the first DFF 214, the second DFF 216, and the third DFF 220, the next state would be 011. However, because the input 236 of the second DFF 216 is forced to a 0, in the next clock transition, the first DFF 214, the second DFF 216, and the third DFF 220 change to state 000 rather than 011. Accordingly, in state 111, the feedback module 206 forces the divide-by-seven divider to skip the state 011 and return/reset to the next state 000 on the next clock transition. By skipping the state 011, the output 242 has one period for every seven clock cycles, with an output of a 0 for 4/7 of the period, and an output of a 1 for 3/7 of the period, providing approximately a 43% duty cycle, or roughly a 40% duty cycle.
Each of the DFFs may include a master latch 470 and a slave latch 472. On a rising edge of the clock, the master latch 470 may store an input bit. On a falling edge of the clock, the master latch 470 may output the stored bit to the slave latch 472 and the slave latch 472 may store the bit inputted by the master latch 470. The bit stored in the slave latch 472 is outputted by the DFF.
A method of operation of the illustrated second divide-by-seven divider will now be described. The operation with respect to the first module 402, the second module 404, and the feedback module 406 is as described with respect to the first module 202, the second module 204, and the feedback module 206 of
As shown in
Referring again to
The feedback module 206/406 has a feedback module input 238, 242/438, 442 and a feedback module output 244/444. The feedback module input 238, 242/438, 442 is coupled to the third stage output 242/442 and the second stage output 238/438. The feedback module output 244/444 is coupled to the second stage input 236/436. The first stage 214/414 is a first DFF, the second stage 216/416 is a second DFF, and the third stage 220/420 is a third DFF.
The first module 202/402 may include a first inverter 208/408 coupled to the first stage output 234/434, a NOR gate 210/410 coupled between the first inverter 208/408 and the second stage input 236/436, and a second inverter 212/412 coupled between the second stage output 238/438 and the first stage input 232/432. Alternatively, the first module may include other logic gates that perform similar functions as the logic gates shown in
As shown in
In one configuration, a divide-by-seven divider apparatus includes means for storing a count between 0 and 3 in a count cycle within a first module. The first module is clocked with a clock input. The means for storing the count may be the first module 202/402. The divide-by-seven divider apparatus further includes means for clocking a second module with an output of the first module. The second module is coupled to the first module. The means for clocking the second module may be the first module 202/402, and second module 204/404, and a connection 238/438 between the first and second modules for clocking the second module 204/404 with an output of the first module 202/402. The divide-by-seven divider apparatus further includes means for causing, by a feedback module, the first module to skip one count in the count between 0 and 3 once every other count cycle. The feedback module is coupled between the first module and the second module. The first module, the second module, and the feedback module are configured to divide the clock input by seven. The means for causing the first module to skip one count may be the feedback module 206/406. The divide-by-seven divider apparatus may further include means for adjusting a duty cycle from less than 50% to approximately 50%. The means for adjusting may be the duty cycle adjustment module 460. The divide-by-seven divider apparatus further includes means for outputting the divided clock input.
Referring again to the divide-by-seven dividers of
It is understood that the specific order or hierarchy of steps in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged. Further, some steps may be combined or omitted. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.” Unless specifically stated otherwise, the term “some” refers to one or more. Combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and/or C, and may include multiples of A, multiples of B, or multiples of C. Specifically, combinations such as “at least one of A, B, or C,” “at least one of A, B, and C,” and “A, B, C, or any combination thereof” may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, where any such combinations may contain one or more member or members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”