Patent Application
20240364320
This present disclosure relates generally to current sinking circuits, and more particularly to a low-power, fast-transient current-sink capable of sinking large currents for use in a switching regulator or power management unit.
Many electronic products, such as Bluetooth radios, automotive infotainment systems, and Wi-Fi hubs and receivers include microcontroller units (MCU) or programmable systems on a chip (PSoC), in which a processor unit, memory, and communication interfaces and peripherals are integrally formed as a single integrated circuit (IC) or die with a power management unit (PMU) or Switching Regulator (SR) designed to provide stable, noise free DC voltage to logic devices in the IC. Typically, the logic devices are fabricated using metal-oxide-semiconductor field-effect (MOS) transistors capable of operating with gate-to-source voltage of about 1.8 volts (V) across their gate oxides (Gox), i.e., 1.8V Gox devices. In the past the PMU or SR could be fabricated on the same IC using 2.5V Gox devices, which were required to allow continuous operation at battery or DC input voltages ranging from 1.6V to 4.8 V. However, as semiconductor fabrication technologies shrink the size of logic MOS devices to 28 nanometers (nm) or 22 nm and beyond, process limitations prevents the use of 2.5V Gox and 1.8V Gox devices in the same die, thus only 1.8V Gox devices are available to use for both the logic devices of the MCU and power transistors or devices of the PMU or SR. With only 1.8V Gox devices available for use, the PMU or SR must use a floating-rail architecture to limit the gate-to-source voltage across the power transistors or devices to 1.8 V. However, this 1.8V Gox limitation will limit a minimum battery or DC input voltage of state-of-the-art floating-rail architectures.
In operation a floating-rail reference voltage (VSSHV_REF) is applied to a first input of the differential amplifier 106, that is the gate of the second PMOS transistor 110, and the output of the differential amplifier on the drain of the third PMOS transistor 112 is coupled to the gate of the first PMOS transistor 108, which functions as a PMOS voltage follower to generate a floating-rail voltage (VSSHV) on an output node between the source of the first PMOS transistor and the second current source 104. The VSSHV is coupled to a gate of the third PMOS transistor 112, a second input of the differential amplifier 106, and to a power amplifier or switching transistor in the PMU or SR 118, represented in this figure by a laterally-diffused PMOS (LDPMOS) transistor 120 and an inverter 122.
The current-sink 100 described above, while satisfactory under normal operating conditions, is subject to a number of disadvantages or limitations.
Firstly, to enable fast transient load current sinking requires a high quiescent current (Idq) through the first PMOS transistor 108, resulting in the need for high quiescent biasing currents (Ibias) through the through the first and second current sources 102, 104, increasing the power consumed by the current-sink 100, and reducing the efficiency of the PMU or SR in which it is embodied. This is especially problematic when amount of transient current the current-sink 100 must sink is large.
Secondly, the floating-rail voltage (VSSHV) generated needs to be able to go to 0V in order to satisfy the above described limitation on Gox by maintaining VSSHV at 1.8V below VBAT while allowing continuous operation at battery voltages ranging from 1.6V to 4.8 V. However, the minimum VSSHV that can be generated by the current-sink 100 is limited by a diode voltage of the first PMOS transistor 108 and a drain-source voltage (Vdsat) of the third PMOS transistor 112. Thus, a minimum operating battery voltage is limited to 2.7 V.
Accordingly, there is a need for a current-sink capable of rapidly sinking large transients in a current load (ILOAD) to provide a stable floating-rail voltage (VSSHV). It is further desirable that the current-sink is capable of operating at battery voltages less than 2.7 V, and able to quickly sink transient load currents (high Idq) without requiring high Ibias currents.
A current-sink and method are provided for rapidly sinking to ground large, transients in a load current of a circuit or load coupled to a floating-rail. The current-sink and method are particularly useful in power management units (PMU) or switching regulators (SR) including a high-side switching transistor, such as a laterally-diffused p-channel metal-oxide semiconductor or LDPMOS.
Generally, the current-sink includes a dynamically controlled latch system having a latch system input operable to receive a transient load current signal from the load coupled to the floating-rail, and a current sinking switch coupled between the floating-rail and ground. The current sinking switch is controlled by a voltage output from a latch system output, and is operable to sink at least a portion of the transient load current from the load coupled to the floating-rail to provide a stable floating-rail voltage (VSSHV).
The latch system generally includes a set-reset (S-R) latch, a comparator and a dynamic biasing circuit. The S-R latch is operable to output the voltage to turn on the current sinking switch when set by a pulse applied to a set input. The comparator has a first input coupled to VSSHV on the floating rail, a second input coupled to a floating-rail reference voltage (VSSHV_REF), and an output coupled to a reset input of the S-R latch. The comparator is operable to output a voltage to reset the S-R latch when a difference between VSSHV and VSSHV_REF is less than a predetermined voltage. The dynamic biasing circuit is coupled between the latch output and a number of biasing inputs to the comparator and is enabled and enables the comparator only while the transient load current is present.
In some embodiments, the latch system further includes a logic-gate and a pulse generator. The logic-gate includes a first logic-gate input coupled to the comparator output and a logic-gate gate output coupled to the set input of the S-R latch. The pulse generator includes a pulse generator input coupled to and operable to receive the transient load current signal from the load coupled to the floating-rail, a pulse generator output coupled directly to the set input of the S-R latch, and an inverter through which the pulse generator output is coupled to a second logic-gate input of the logic-gate.
Further features and advantages of embodiments of the invention, as well as the structure and operation of various embodiments of the invention, are described in detail below with reference to the accompanying drawings. It is noted that the invention is not limited to the specific embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to a person skilled in the relevant art(s) based on the teachings contained herein.
Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts. Further, the accompanying drawings, which are incorporated herein and form part of the specification, illustrate embodiments of the present invention, and, together with the description, further serve to explain the principles of the invention and to enable a person skilled in the relevant art(s) to make and use the invention.
A low-power, fast-transient, large current-sink and method for sinking large transient currents in an output of a floating-rail voltage generator are provided. The current-sink and methods of the present disclosure are particularly useful in portable and low-power applications such as in a power management unit (PMU) or switching regulator (SR) for Bluetooth (BT) radios, Wi-Fi hubs or receivers, and other microcontroller units (MCU).
In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention can be practiced without these specific details. In other instances, well-known structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.
Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term to ‘couple’ as used herein can include both to directly electrically connect two or more components or elements and to indirectly connect through one or more intervening components.
An embodiment of a current-sink 200 will now be described with reference to
In some embodiments, such as that shown, the current-sink 200 further includes a sinking capacitor 214 coupled in parallel with the current sinking switch 202 between the floating-rail 206 and ground to sink large, fast-transients or spikes in load current.
Generally, as in the embodiment shown, the current sinking switch 202 is an n-type or n-channel MOS (NMOS) transistor.
The latch system 204 generally includes a comparator 216, a set-reset (S-R) latch 218 and a dynamic biasing circuit 220 coupled between an output of the S-R latch and the comparator. The comparator 216 has a non-inverting input coupled to VSSHV_REF, an inverting input coupled to the floating-rail 206, and an output coupled through a first input of a logic-gate 224 to the S-R latch 218. The S-R latch 218 has a reset input (R) coupled through an output of the logic-gate 224 to the comparator, a set input (S) coupled to a pulse generator 226 operable to receive a transient load current signal 222 from the load 208 coupled to the floating-rail and output a pulse 228 to set the S-R latch 218 on a leading edge. The S-R latch 218 further includes a latch output coupled to the control gate of the current sinking switch 202.
In some embodiments, such as that shown, the logic-gate 224 is a two input AND gate and includes a second input coupled to the pulse generator 226. The pulse generator 226 has, in addition to an input coupled to and operable to receive the transient load current signal 222, a pulse generator 226 coupled to the set (S) input of the S-R latch 218, and an inverter 232 to the second input of the logic-gate 224. The inverted pulse applies a logic ‘0” to the second input of the logic-gate 224, thereby ensuring that any noise or glitch generated by dynamic biasing of the comparator 216 does not result in an erroneous reset signal to the S-R latch 218. After a predetermined time equal to a pulse width of the pulse 228, a logic ‘1’ is applied to the second input of the logic-gate 224, thereby enabling a reset signal to be coupled from the comparator 216 to the reset (R) input of the S-R latch 218 when a difference between VSSHV_REF and VSSHV is less than a predetermined voltage.
In response to the transient load current signal 222, the pulse generator 226 outputs from the pulse generator 226 a pulse having a logic ‘1’ to the set input (S) of the S-R latch 218. This results in a logic high, or output of about 1.8V on the latch output, which is coupled to the gate of the current sinking switch 202 turning on the switch and connecting the floating-rail 206 to ground to sink at least a portion of the transient load current. The output pulse drives the input of the inverter 232 resulting in a pulse logic ‘0’ being applied to the second input of the logic-gate 224. This momentarily suppresses a possible glitch from the comparator 216 applied to the reset input (R) of the S-R latch 218.
At substantially the same time a logic ‘1’ on the output of the S-R latch 218 functions as a bias enable signal, causing the dynamic biasing circuit 220 to output one or more biasing voltages to bias inputs in the comparator 216 to output a logic high when VSSHV is greater than VSSHV_REF by a predetermined amount. At substantially the same time a logic ‘1’ on the output of the S-R latch 218 functions as a bias enable signal, causing the dynamic biasing circuit 220 to improve the comparator 216 response time and accuracy.
At substantially the same time a load current from load 208 begins to flow into node VSSHV which causes node VSSHV to rise above VSSHV_REF. This subsequently switches the comparator 216 from a marginally ON state to operating in a high-precision mode, forcing the comparator to output a logic ‘0’ through the logic-gate 224 into the reset input (R) of the S-R latch 218. The S-R latch 218 output therefore remains high forcing the current sinking switch 202 to start sinking load current from node VSSHV to ground, which then causes VSSHV to eventually decrease below VSSHV_REF. When this condition occurs the dynamically biased comparator 216 asserts logic ‘1’ thus the S-R latch 218 is reset and the current sinking switch 202 is turned-off.
Operation of the current-sink 200 in response to a transient in load current will now be described with reference to the graphs of
Referring to
Referring to
Referring to
Referring to
The cascode stage 506 generally includes a PMOS current mirror 520 coupled to a voltage supply (VDDQ), and first and second pairs of NMOS transistors 522, 524, coupled between the PMOS current mirror and ground and configured to amplify an output from the input stage 504. The output buffer 508 includes series connected PMOS and NMOS transistors 526, 528, and an inverter 530. The PMOS transistor 526 has a source coupled to VDDQ, a drain coupled ground through the NMOS transistor 528, and a gate coupled to receive an output from the cascode stage 506. The NMOS transistor 528 has a drain coupled to VDDQ, through the PMOS transistor 526, a source coupled ground and a gate coupled to receive the voltage Vgn1. Like the biasing stage 502 and the input stage 504, the biasing current of the cascode stage 506 and output buffer 508 is also increased when the dynamic biasing is enabled, and thus the propagation delay of the comparator 500 is reduced accordingly to ensure precise timing to turn off current sinking switch 202 at the end of current sinking phase. In particular, it is noted that as shown in
Next, a pulse 228 having a pulse width is generated and coupled to the set input (S) of the S-R latch 218, and the inverted pulse coupled to the second logic-gate input of logic-gate 224 (step 604). It will be understood from the above description of
The S-R latch 218 is then set in response to the pulse coupled to the set input (step 606), and the voltage on the latch output of the set S-R latch 218 turns on the current sinking switch 202 and enables the dynamic biasing circuit 220 (step 608). At least a portion of the transient load current is sunk to ground through the current sinking switch 202 while the S-R latch 218 remains set (step 610).
Next, the comparator 216 is biased or enabled using the dynamic biasing circuit 220, the floating-rail voltage (VSSHV) on the floating-rail 206 compared to the floating-rail reference voltage (VSSHV_REF) and the comparator output coupled to the first logic-gate input of the logic-gate 224 (step 612).
Finally, after a time corresponding to the pulse width has passed so that logic ‘1’ is on the second input of the logic-gate 224, if the comparator 216 output has reached a voltage corresponding to a logic ‘1’, the logic-gate will output a logic ‘1’ to the reset input to reset the S-R latch 218, turning off the current sinking switch 202, disabling the dynamic biasing circuit 220 and end biasing of the comparator (step 614).
Referring to
The SR 704 is operable to convert a voltage from a battery or other DC power source into output voltages required by other subsystems or devices in the host system 700. The SR 704 generally includes a high-side switching transistor, such as a laterally-diffused PMOS (LDPMOS) transistor 718, controlled by or receiving a floating-rail voltage (VSSHV) from a floating-rail voltage generator 720 to supply the required output voltages. In addition to the dynamically biased current-sink 706 of the present disclosure, the floating-rail voltage generator 720 can further include a floating-rail reference generator 722 and a current buffer 724 to generate and buffer a floating-rail reference voltage (VSSHV_REF). The dynamically biased current-sink 706 sinks transients in a load current, which can undesirably impact VSSHV.
Thus, low-power, fast-transient current-sink and methods of operating the same have been disclosed. Embodiments of the present invention have been described above with the aid of functional and schematic block diagrams illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.
The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present invention.
It is to be understood that the Detailed Description section, and not the Summary and Abstract sections, is intended to be used to interpret the claims. The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present invention as contemplated by the inventor(s), and thus, are not intended to limit the present invention and the appended claims in any way.
The breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.
