Fast modulation of optical signals with low cost devices is of great interest to many fields ranging from on-chip or intra-chip interconnections to Si photonics for telecommunication. Among the different technologies proposed to develop modulators, silicon photonics is one of the most promising as it allows mass production at an attractive cost, and can allow monolithic integration with advanced electronics on a single die. Electro-optical effects in strained silicon or quantum-confined stark effect in SiGe/Ge quantum wells have been demonstrated recently, but at the moment fast modulators integrated in silicon are based on the plasma dispersion effect. A three terminal Bipolar Mode FET (BMFET) integrated in a low loss single mode SOI waveguide with a switching time of less than 3.5 ns and π-phase shift interaction length (Lπ) of 1 mm has been described in the literature, and more recently there has been described a P-I-N silicon modulator, with bit rates of 10 Gb/s, and an Lπ of 100 to 200 μm. Another device recently described is a PN junction based fastest modulator of 40 Gb/s with an Lπ of 1 mm, using a carrier depletion structure combined with travelling wave electrodes. Another device described in the literature as a depletion mode PN junction based SOI modulator was reported with rise and fall times of 7 ps with an effective bandwidth of 60 GHz. A shorter EO modulator length has been demonstrated by incorporating resonant light-confining structures in the device. Group III-V-based travelling wave electro-absorption modulators (TWEAM) using a high quantum-confined stark effect have been reported to operate at 80-100 Gbits/s.
One pathway to modulate light is based on the traditional Mach Zender interferometer structure (MZI). However, the proposed approach to light modulation also impacts many photonic optical structures that involve phase shift of a light beam induced by the so called free carrier effect. A generic photonic structure that could utilize this effect is shown in
These structures need to bring two optical guides close together to induce directional coupling as shown in
Following Okamoto, the Jones matrix representation of the fields at the outputs of the combiner mixer is given by
where d is the length of the directional coupling sections, and Δφ is the amount induced by the phase shifter. Defining
k=sin2(κd)
one can compute the intensities corresponding to the two output fields E3 and E4.
One then has a system component that can mix signals from two sources with mixing coefficients that can be adjusted through the k (coupling coefficients) and
Δφ=2πnΔL/λ,
Most work in the past for light modulatin has been dominated by advanced physics studies involving Multiple Quantum Well and other quantum effect structures, such as the Stark Effect in SiGe. However these structures are not in the panoply of existing Silicon devices manufactured today. It would be extremely difficult to incorporate such devices into existing manufacturing flows where photonics could be quickly adopted, and disseminated throughout the infrastructure. Instead a pre-quantum mechanical idea due to Paul Drude in the early 1900's has shown promise. It utilizes the tendency for carrier plasma in semiconductors to lower the propagation velocity of light as it passes through the plasma.
INTEL announced in the 2004 issue of NATURE that it had successfully modulated light in silicon using the Drude effect by reflecting light in the region of Silicon under the active carrier plasma under a FET capacitor structure. Early results demonstrated 2.4 Gb/s as a bit rate, and this has now been improved to 10 Gb/s. Part of the trick for attaining 10 Gb/s was developing a driver for the huge 2.5 mm W (channel “width”) of the phase shifting FET capacitor. Additionally there is a requirement for L (channel length) of one wavelength because the “channel length” of the structure has to be comparable to a wavelength of light. This limits the fT of this FET free carrier light modulator device. The light modulator involves a phase shift from passing light through the carrier plasma in the thin inversion region of along a very long FET capacitor (2.5 mm in one case) until a phase shift of π was obtained. The structure is shown in
The Drude Effect creates a kind of programmable dielectric in the hole-electron plasma region with changes in effective optical index and attenuation per unit length given by:
Soref has published empirical modifications of these equations where additional semiconductor effects exist at a wavelength of 1.55 microns.
Δn=Δne+Δnh=−[8.8×10−22ΔNe+8.5×10−18(ΔNh)0.8]
Δα=Δαe+Δαh=8.5×10−19ΔNe+6.0×10−18ΔNh
where the subscript “e” and “h” denote the electron and hole contributions to the change in index seen by the light as it passes through the free carrier plasma. One can see a slight nonlinearity in the hole component. One can also see from the change in the index of refraction that light passing through the graded base SiGe HBT can be slowed down based upon voltages applied to the HBT, which alters the free carrier densities and that this slowing of light introduces a phase shift. Hence the graded base SiGe HBT is a kind of phase shift modulator.
Here Δn and Δα are the variation of the real part of the refractive index (n) and of the absorption coefficient (α) when the free carrier concentration deviates from the values of the intrinsic semiconductor; e is the electron charge, ε0 is the dielectric constant in free space, n is the refractive index of intrinsic Si, μ is the free carrier mobility, mc,mh are the effective (i.e. normalized) masses, ΔN is the free carrier concentration variation, and λ is the wavelength. The subscripts e and h refer to electrons and holes, respectively. Since the effective masses are on the order of 0.1-1.0, and the electron and hole mobilities are 1450 and 505 in the cgs-volt system respectively, one can see that the attenuation change effect is in Si semiconductors. This is primarily due to the factor of the speed of light c3 in the denominator for Δα vs. c2 for Δn. The Si based Drude Effect device is essentially a phase modulator whose change depends on plasma carrier density changes induced by device voltage changes. The imaginary part of the index, namely k, is for undoped silicon typically between 5 and 9 orders of magnitude down from the real part, n in the range of 1-1.4 um for IR (Palik). Hence, on a materials and device basis, loss is very low in the Si materials system. In these formulas it is important to keep in mind the relation between the attenuation coefficient α, the extinction coefficient k, and wavelength:
α=4π
As can be seen from these equations the phase shift one can induce depends on the general order of magnitude of carriers in the semiconductor which tends to be set by the maximum doping densities compatible with normal CMOS operation and this is typically around 1017 per cubic centimeter. The other factor is the volume over which the carriers are concentrated by the device, and particularly the volume over which the light photons actually interact with the carrier plasma. For the FET device this is restricted to an extremely thin region of inversion or accumulation near the thin oxide, typically one or two Debye lengths or about 200-400 Angstroms. MEDICI can be used to compute this carrier density. Using the meshing profile shown in
Since a primary focus is the hole concentration for the npn HBT the FET selected is the p-channel device in CMOS for comparison, as shown in
In spite of very high doping in the source drain region the absolute maximum carrier density in deep channel inversion is only 2×1017, and has fallen already to half its peak at about 400 Ångstroms. The INTEL device was used for the phase shifting capability of the Drude Effect in a Mach Zender Interferometer structure as shown in
Although the INTEL breakthrough is significant and useful in these types of shifters, it has some disadvantages, primarily its large physical size, which exceeds several millimeters in length. Large physical size complicates creating large structures with many such phase shifters. This is because differences between RF and optical signal propagation velocity along the device can degrade the coherence between the applied RF signal and the corresponding light signal subjected to this RF signal. Large size also creates long optical paths which can accumulate loses.
The use of SiGe-on-Si technology for high speed optical modulation based on a free carrier plasma effect, where for a wavelength of 1.55 μm, an L, of 190 μm is obtained with an insertion loss of 4.7 dB, is described in R. D. Lareau, L. Friedman, and R. A. Soref, “Waveguided electro-optical intensity modulation in a Si/GexSi1-x/Si heterojunction bipolar transistor,” Electron. Lett. 26(20), 1653-1655 (1990) (“Soref”). It describes the structure shown in
Younquian Jiang et al. in Applied Physics Letters describe the structure shown in
These prior art devices accordingly have disadvantages. The results for SiGe modulators that have been reported in the literature exhibited longer device lengths, and RC limited bandwidths. The FET has at least one obvious and inherent limitation. Its speed is inherently limited by its channel length. To reach an fT of 80 GHz the channel length must be less than 0.1 micron. The wavelength of infrared capable of propagating at low loss in Si is 0.8 micron. Since the direction of propagation is down the W direction of the FET, this puts a severe limitation on the channel length. It must be fairly wide compared with the wavelength of light. Hence, the FET is severely limited in the speed of modulation. The fastest modulator reported by INTEL using the FET is 40 Gb/s which suggests a bandwidth of 20 GHz. This in turn suggests a channel length of about 0.5 um at most if a single device is used. Multiple finger gate FET's are possible but one must account for source and drain contacts which separate the gate fingers.
It would therefore be desirable to provide a device without these limitations.
According to the invention, a graded base silicon-germanium (SiGe) heterojunction bipolar transistor (HBT)-based electro-optical (EO) modulator includes a graded base HBT and a light beam directed under the graded base HBT and passing through the free carrier plasma within for the purpose of inducing a phase modulation of the light beam.
The invention and the numerous applications incorporating the invention provide faster internet communication capabilities, and mitigation of what is termed the ultra narrow wire resistivity barrier which does not follow Moore's law scaling. The latter problem otherwise poses challenges for semiconductor manufacturers.
SiGe HBT is significantly smaller and more amenable to integrated circuit incorporation than a FET. The SiGe alloy can permit up to 2 orders of magnitude higher B doping in the base region (1019 cm−2 up from 1017 cm−2), and especially with base pushout the volume would be much larger for the HBT than for the FET (400-md 1000 Å for the bipolar base and emitter thickness only—plus collector, vs. 2004 for the Debye length inversion channel thickness for the FET). However the high doping in the base would degrade beta, and in early SiGe HBT's this was a problem.
However with the advent of graded base SiGe HBT's the built in field resulting from the grading compensated the beta degradation from the high base doping, making the SiGe HBT an interesting device for manufacture for amplifiers, modulators, and logic devices. This found for the SiGe HBT a viable economic basis for manufacture, leading to eventual incorporation of this device into BiCMOS at companies such as IBM, Jazz, Infineon, ST Micro, and Phillips worldwide. While the majority of the industry is based on FET technology, the SiGe graded base HBT has a solid place in standard silicon technology. Here it can be interfaced monolithically with powerful microprocessors, analog circuits such as LNA's, VGA's and supporting interface circuits such as SERDES or Serializer Deserializers.
SiGe HBT SERDES work: Numerical analysis of the carrier density in a 2D model for the HBT was performed using the MEDICI device simulation and carrier modeling CAD program, with good results. The Drude Effect functions in the INTEL FET light modulator, and the graded base SiGe HBT provides improved performance. Secondarily since the graded base HBT light modulator uses a carrier plasma density to induce varying of the velocity of light and hence accumulated phase shift with a higher carrier density over a larger volume, that the light may be made to pass back and forth through this plasma to attain a reuse of the same carriers using a low Q resonant structure such as a slow wave structure, a photonic crystal. By reusing the same carriers, the injection current needed to place them into the volume of interaction may be significantly lowered, lowering the power needed for the modulator, and the device may be made more compact.
Another advantage of the HBT of the invention is its much higher doping density, therefore it can be much shorter than the FET, increasing the total amount of optical attenuation from Si absorption. The shorter the device the less current is required to place the plasma into that volume.
The SiGe graded base has an advantage over the original SiGe HBT investigated by Soref in the late 1980's because it permits higher doping densities without loss of the beta which would make the device useless for other millimeter wave applications. Also, silicon has been, are, and probably will be the materials system of choice for commercial electronics. Two and only two devices have a track record and have a justified existence for product production.
Referring now to
The B-doped SiGe graded base layer 11 (composition-rate graded base layer) has a composition ratio of germanium to silicon that varies in its thickness direction, with the Ge content decreasing toward the top, thus forming a gradient of a bandwidth on the base layer to accelerate electrons.
Graded base SiGe HBT 100 operates as a Drude Effect phase shifter that is enhanced by also including a photonic crystal slow wave-guide designed to further shorten the device and reduce losses further. It operates in the range disclosed by Soref while providing phase shift devices as short as 10 microns.
The cross section of the graded base SiGe HBT electro-optical (EO) modulator 200 with the light modulating functionality-adding light source 202 is shown in
The MEDICI meshing for HBT showing SiGe base at 1000 Angstroms and doping profile used to obtain the injected current and carrier distributions under in and under the HBT is shown in
We have mentioned the inherent efficiency of reusing the carrier plasma under the HBT. It requires a certain amount of current to inject the holes and electrons in the emitter, base and collector. But once the carriers are there light can pass more than once through the plasma and slow down by the same amount each time. This can be accomplished by reflecting the light through different pathways in the plasma, back into it at different angles. But the most impressive reuse is to build a low Q resonator, in one example by employing a slow wave photonic crystal. Such a photonic crystal is shown in
An additional consideration is that the light passing through the graded base SiGe HBT must be confined from the bottom. This typically will require perhaps an oxide, diamond or other dielectric layer which keeps reflecting the light back up under the free carrier plasma. If this is not done the light will eventually leak out from under the SiGe HBT into the Si substrate. For SiGe HBT devices implemented on a (possibly thick) Silicon on Oxide or SOI substrate the oxide of that wafer can provide this underlayer light confinement. This confinement from the bottom is not unlike the use of oxide walls on the optical waveguides used to route the light up to and away from the The graded base SiGe HBT 100 can be fabricated via the standard process described in Saitoh et al. No special Multiple Quantum Well or Stark Effect devices are needed that would require nonstandard processing at the device level. Even the INTEL FET capacitor is a somewhat non-standard device requiring process steps not in the standard line. So the SiGe HBT offers more straightforward way to incorporate HBT CML or CMOS circuitry into hybrid photonic/electronic systems. However, the Saitoh et al. process is an electronics wafer, and does not incorporate the new functionality of the invention to make this a photonics substrate. Consequently the optical guiding structure needs to be provided to get the light under the HBT. 3D processing techniques can thin the backside of the SiGe wafer exposing the underside of the HBT. By bonding this wafer onto a SOI wafer one has a chance to combine a wafer, which is more typically used for photonic wave guiding in Si. Other optical structures such as waveguides, photonic crystals, resonators, and polarizers which are not in the Saitoh et al. process can be fabricated on this second wafer, and by using 3D wafer to wafer bonding steps these two substrates can be joined, as shown in
To implement the underlayer beam confinement layer, in the case that this is not obtained using an SOI substrate, this underlayer needs to be implemented using further wafer thinning and stacking processes, which may involve 3D wafer bonding processes. As a method for realizing an embodiement, and for completeness, one such process will be discussed here. The first wafer bonding process is to a handling wafer, which then permits thinning the back side of the SiGe wafer to only a few microns to expose the HBT collector underside.
Since electrical conductivity below this is expected for the HBT and CMOS in the Saitoh et al. process any photonic substrate must provide this pathway. The second wafer bonding process would place the photonic substrate with its waveguides, gratings, photonic crystals, etc onto the exposed underside of the SiGe wafer, and the handling wafer is totally removed, leaving the upside down SiGe HBT's on the top of the photonic substrate. The photonic substrate can be either built into the back of that thinned substrate or bonded face to face with a separate photonic substrate (or a combination of these). Having a second substrate permits incorporation of a number of devices that might require very different fabrication steps, some at high temperature, which would be incompatible with the SiGe device wafer. Such integration is called 3D Heterogeneous Integration or HI. The minimal expectation is that the second substrate would be an SOI wafer with low loss waveguides, photonic crystal structures, Ge detectors, grating or rib structures, closely spaced directional coupler structures, ring resonators, and vertical couplers. The available equipment natively will produce 1 um alignment in x and y directions across the entire 8 inch wafer, but this can be enhanced by use of vertical surface asperities to help “nudge” or slide the wafers mechanically into closer alignment. This could be brought to 0.25 micron alignment in x or y, and wave crossing between the bonded wafers can be designed to be tolerant of this small alignment error.
The reason for the 3D approach is that the waveguide structure and associated photonic crystal must be positioned below the emitter, base and collector of the HBT, with protrusion of portions of the optical mode into the base and emitter. We have already shown that the photonic crystal can be used as a slow wave structure to reuse carrier plasma through repeated backward and forward reflections within the structure. However, the same photonic crystal can mode shape the propagating wave coupling into the HBT emitter base and collector region through the wafer bonding gap (which must be tuned) and up into the carrier plasma by evanescent extension through the plasma. The design of such a structure requires extensive calculations. The problem of course is that the standard BiCMOS process with 8 or 9 levels of metal wires, has no BEOL room for optical interconnections or vias in the interconnect stack, and the best (i.e. lowest attenuation) material for waveguides is a Si crystal substrate in any case. Unfortunately the very advantage of the SiGe high yield commercial process is also the disadvantage, nobody will want to alter the process for optical interconnections, so these must be added using 3D wafer bonding approaches. At least with this approach the photonic wafer can be passive with simple geometric structures.
The challenges of this approach include the alignment accuracy of the two wafers, and the thickness, optical index, and uniformity of the bonding layer or approach. Typical face-to-face aligner accuracies today are only about 1 micron. However an approach to be developed in this work is the use of surface asperities to enhance that alignment accuracy. The thickness of the bonding layer is also a concern since it must couple well between the Si waveguide on the photonic wafer and the under-layer below the SiGe HBT (which is also on Si obviously). One can attempt to make the bonding layer extremely thin (much less than a wavelength of light for example) in order to minimize this effect, or deposit multilayer adhesives designed to tune for transmission between two Si layers. The presence of this layer between the waveguide on the photonic substrate must be modeled and incorporated into the photonic crystal design. Establishment of this intimate bond is extremely demanding given the wafer TTV, flexure and deformability of Si and bonding agents. In addition, while the photonic wave-guiding substrate can be fabricated on 8-inch SOI wafers where the BOX layer forms a natural etch stop layer in wafer-thinning, the HBT wafer is not implemented on an SOI wafer, and alternative methods for stopping the thinning process (such as hard Tungsten studs inserted from the top of the wafer) must be implemented and evaluated on blank wafers first. An example of this layered structure is shown schematically in
One can see that there are a number of issues here, including alignment strategy, design of the Photonic Crystal, and coupling structure, guiding structure, coupling into the collector, base and emitter, and exquisite control over wafer thinning. However, it is clear that the main challenge of the 3D wafer bonding approach is the unknown loss and coupling efficiency associated with coupling light across the bonding layer between these two wafers and back into the photonic substrate waveguides to the next HBT involved in switching. One of the key technologies needed is precision wafer thinning. Unfortunately, with the SAITOH ET AL. SiGe HBT BiCMOS process the wafers are not SOI wafers and have no precision etch stopping layer. Yet the SiGe wafer must stop etching at or just below the sub-collector layer. Several approaches have been developed for etch stopping in this case, including an approach by Tezzaron to use W based plugs to act as hard stops on a CMP polishing wheel. These W plugs have to be inserted into the wafer to be thinned, and most importantly space in the chip layout to insert these must be provided ahead of time. The idea works with many non-SOI processes such as DRAM. However, the density of W studs is high, and this approach may not be precise enough to obtain 1-2 μm residual thicknesses with 1 to 10% thickness control on the final thickness.
An interesting alternative is to measure the thickness of a partially thinned wafer (say at 50 um) using equipment made by Sematech and use the mathematics of computerized tomography to vary the dwell time of etching along a linear orifice through which an etchant meniscus just touches the wafer, proceeding along lateral sweeps across the wafer at different angles. The superposition of etch dwell times from different sweeps at all sweep angles across the same wafer surface can be arranged to just etch off the precisely computed excess.
This type of structure is called a Fabry Perot resonator. This type of resonator typically has a low Q or quality factor meaning that the bandwidth of the optical resonator is not excessively narrow, and does not degrade the bandwidth of the optical modulation signal. The Low Q resonator enhances the performance of the SiGe HBT phase shifter by passing the light back and forth many times through the free carrier plasma. This permits a reuse of the same plasma, thereby enabling the reduction of the length of the device (with all the simplifications this implies) and a reduction in the total current needed to supply the free carrier charge, which reduces the average power and “energy per bit” in a digital modulation system. An optional photonic crystal 306 is positioned at a lower surface 204.
The SiGe HBT EO modulator of the invention in one embodiment has an operation bandwidth of from about 2.4 GHz to about 10.4 GHz with a short Lπ of 73.6 μm. The graded base NPN SiGe HBT that is based on Saitoh et al. as discussed below includes 8HP technology for fast EO modulation, and exhibits a [simulated] data transmission rate of 80 Gbits/s of the EO modulator for very short-haul backplane, interchip and intra-chip, board/package-level optical interconnections.
The free carrier effect is employed to shift the phase of light adequately to employ this mechanism in Mach Zehnder interferometers. Much faster speeds are possible using a SiGe HBT to inject and extract the free carrier plasma. Because only computational evidence is presented, at least two independent Computer Aided Design tools have been employed at each step of the simulation to cross check the results wherever possible. These tools strongly support the conclusion that modulation can be extended to 80 Gbits/s and perhaps to even higher speeds. An IBM certified CADENCE 8HP kit is used to validate the speed performance of the SiGe NPN HBT transistor. A two-dimensional MEDICI structure for the third generation SiGe HBT 8HP transistor is carefully constructed to study the necessary carrier dynamics. Comparison of these numerical simulations with those performed using MEDICI to extract the static, dynamic and transient characteristics of the device at small and large signal inputs confirms the accuracy of the model and the superior performance of SiGe 8HP compared to other Si based devices. The change in electron and hole carrier concentration is plotted from MEDICI for different base-emitter biases. The total charge obtained then is fed into the optical waveguide simulation software RSoft BeamProp, where an exactly similar structure compared to the MEDICI structure is created for mode calculation and extraction of Lπ. The modal profiles of the device at various biases are also analyzed. For further confirmation this has been duplicated using finite-difference-time-domain (FDTD). The Lπ for TM polarization is 240.8 μm at 1.1V base-emitter junction bias. A figure of merit is obtained of 0.0264 V-cm, which is the best combination obtained of the speed and device length without enhancement through the use of low Q resonant structures.
The HBT of the invention derives its electrical switching speed primarily from the thickness of its base region which is in the 0.04-0.1 micron range but the width of the emitter strength can be much wider than the channel length of a FET. Essentially the full capability of the HBT is retained up to very high switching frequencies, whereas the FET is severely limited in width and its ability to accommodate the optical wavelength at all. So the speed of the Graded Base SiGe HBT is its main advantage.
Thus, while the present invention has been described with respect to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that variations and modifications can be effected within the scope and spirit of the invention.
This Application claims the benefit of U.S. Provisional Application 61/310,754 filed on Mar. 5, 2010 and incorporated herein by reference.
Number | Date | Country | |
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61310754 | Mar 2010 | US |