Patent Application
20050123081
The present invention relates generally to wireline communications and more particularly to a system and method to cancel echo and crosstalk in such communications.
In this embodiment, the Rx signal has been distorted due to the impairments of the channel including inter-symbol interference (ISI), addition of Near End & Far End crosstalk from coupling from other transmit channels and echo of its own transmitter. The signal typically goes through the AGC to improve the signal dynamic range, and a local echo canceller to remove the intermediate transmit signal. System 10 requires a high resolution Analog to Digital converter (A/D 14), which translates the signal to high resolution digital information which is then equalized digitally through digital filters (possibly a Feed Forward Equalizer 16, or a Feed Back Equalizer). Furthermore, the data is sliced by slicer 20 and the data error is calculated (as an example through an LMS algorithm) which in turn sets the coefficients of the appropriate FIR filter for Echo, NEXT, and FEXT cancellers. The output of the FIR filters is subtracted from the signal prior to the slicer 20. The data decoder 22 represents possible additional data decoding, which is protocol dependent, required to completely decode the signal.
In a wireline communication channel, where multiple signals are sent over multiple wires, the wires can be electromagnetically coupled to one another and result in an interference from one channel to another, so called near end Xtalk (NEXT) or far end Xtalk (FEXT). At the same time signals traveling in a channel can reflect back off of the imbalances in the channel and interfere with itself, so called signal echo. In most communication systems, a cancellation scheme should exist to cancel out the effect of signal echo and crosstalk from adjacent lines to achieve an acceptable bit error rate (BER), echo and Xtalk (i.e., NEXT and FEXT) cancellation is possible as the system has the information about the bits sent and the bits received.
The typical method to cancel the effect of echo and Xtalk in communication theory is using finite impulse response (FIR) filters. The conventional method of performing echo and Xtalk cancellation using FIR filters is done fully in digital domain (other than the pre-echo cancellation for the immediate transmit pulse), where the calculated digital value of echo and Xtalk by the FIR filter is subtracted from the incoming noisy analog data input, which is digitized by an analog to digital converter (ADC). The digital approach, however, can have a significant complexity if the size of the FIR filters is large and thus results in large power and area on the silicon.
Accordingly, what is needed is a system and method for addressing the above-identified issues. The system and method should be cost effective, adaptable to and easily implemented existing processing systems.
The present invention addresses such a need.
A signal processing system is disclosed. The signal processing system comprises an AGC and pre-echo cancellation system for receiving an analog signal, boosting it up (over all frequencies) to a pre-determined range by AGC, and removing the immediate transmit pulse from this received signal by pre-echo canceller to provide a second analog signal. The signal processing system further comprises a summer for receiving the analog signal; a feed forward equalization (FFE) unit for receiving a signal from the summer; and a slicer for receiving a signal from the FFE unit and providing an output signal. The signal processing system also comprises an Echo and NEXT cancellation system for receiving the output signal and for providing a signal to the summer for canceling the echo and crosstalk in the signal processing system.
Accordingly, in a system and method in accordance with the present invention the Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE. This allows for a practical analog implementation which has a good dynamic range with the echo, and NEXT removed there is more dynamic range allowable for the signal; furthermore NEXT and Echo are of high frequency nature and if not removed will get significant boost from the FFE which will limit the dynamic range of not only the FFE, but also the follow on analog circuits) of the signal through the FFE and subsequent analog elements. This system can be utilized to great advantage in low power CMOS designs where supply voltages are limited.
The present invention relates generally to wireless communications and more particularly to a system and method to cancel echo and crosstalk in such communications. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
With this embodiment it is now advantageous for Echo, NEXT and FEXT to be subtracted prior to the FFE in a practical analog implementation, to allow for a reasonable dynamic range of the signal through the FFE and potential subsequent analog elements. This is especially true for lower power CMOS designs where supply voltages are limited to 3.3V, 2.5V, or lower.
The Echo, NEXT, and FEXT cancellers could be constructed in one of two ways:
1. Hybrid: The cancellers are in digital and the final summation of all cancellers passes through a digital to analog converter and subtracted as shown.
2. A mixed signal: Where the multiplication is done through DACs, and summation through current summing. To describe an all analog FIR filter refer to the following.
In a system and method in accordance with the present invention, a FIR filtering technique is implemented in a mixed signal fashion. There are three main functions that are required by a FIR filter, an accurate delay block (equal to a symbol period or an integer fraction of it), a multiplier (that multiplies the data/symbol value with a filter tap weight), and an adder (that adds all the multiplied values and subtracts them from the main data). In this embodiment, the delay block is implemented by clocked flip flop stages, so as long as the clock period is equal to or a fraction of the symbol rate, we can generate accurate delays in the digital domain.
The multiplication is performed with a digital to analog converter (DAC) where output current of the DAC is set by the tap weight and modulated by the symbol value (or vice versa). Therefore, the multiplication function hardly needs any logic and can be performed all in a DAC stage. The last function of summation/subtraction is simply done by current summing the output currents of all the DACs in same or opposite direction. This can be done either by sourcing and sinking current from the common current summing node in a single-ended design, or by just sourcing current to either branch of a differential scheme. The final summed output currents of the DACs are also summed with the analog input data (in form of current) and sent to the resistor 312 to be converted to a voltage.
As can be seen the summation and subtraction function require no extra stage or burn no extra power and simple done by current summing of the DAC outputs. The multiplication and summation that is mainly done in analog domain results in significant power saving that differentiates this scheme from the digital approach. It should, however, be noted that all DACs must have enough resolution to accurately cancel echo and Xtalk effect. The resolution of the DAC vary depending on the strength of each of this interference components and thus each DAC can be optimized for its resolution.
At the same time, as the current summing node can turn out to be highly capacitive, as it is shared by many stages, it can slow down the current summing process and the output voltage does not settling to its final value within a symbol time. To address this problem, this invention also proposed an equalization scheme that solves the low-passing effect of the capacitive output node.
The equalization applies pre-emphasis to each DAC outputs, so that in the beginning of each symbol period that DAC changes its value, the DAC sources/sinks a higher current value than its target for a limited time less than symbol period and then switches to its final value. The amount of time that the output current is preemphasized is directly proportional to the RC of the summing node and should be determined for each application and process technology.
where Wn+1(k)=Wn(k)+μen(FFE*TX) Equation 1
In this equation W is the value of the coefficients used for the cancellation (i.e., Echo, NEXT or FEXT). The Wn+1 is the subsequent coefficient value. Accordingly, the subsequent coefficient value is calculated by adding the previous value (Wn) to μ (a constant) Em (error at the slicer) by the transmit signal (TX) and a copy of the FFE.
This equation indicates that the input to each of the cancellers needs to now pass through a copy of an FFE before feeding the appropriate Echo, NEXT, and FEXT canceller. This copy of the FFE is much simpler than the actual FFE in the receive path, because the inputs to it are a finite number of transmit state. For example, in a PAM5 signaling the possible states of the transmitter is bounded to −2, −1, 0, 1, 2.
Accordingly, in a system and method in accordance with the present invention the Echo and crosstalk components associated with a signal processing system can be subtracted prior to the FFE. This allows for a practical analog implementation which has a good dynamic range of the signal through the FFE and subsequent analog elements. This system can be utilized to great advantage in low power CMOS designs where supply voltages are limited.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.
| Number | Date | Country | |
|---|---|---|---|
| 60527496 | Dec 2003 | US |
