Patent Application
20190207559
The present disclosure relates to multi-stage amplifier circuits and methods.
Non-invasive reading of bio-electric signals from the body is inherently challenging because the signals are often weak and much of the information is often at low frequencies. As a result, high-gain and low-noise amplifiers are required. However, traditional capacitive DC blocking cannot be used between amplifier stages because the series capacitors block substantial low-frequency information unless the series capacitors are prohibitively large.
Furthermore, for ultra-low power applications, the power consumption required for high gain amplifiers can be prohibitively large. The reading of bio-electric signals is even more challenging in large-area and flexible electronics because thin-film transistors (TFTs) have lower performance than VLSI transistors and complementary (e.g., both n-channel and p-channel) TFTs are typically not available or feasible.
A need therefore exists for improved amplifiers for capacitive reading of low-amplitude and low-frequency signals.
Embodiments of the disclosure provide low-power multi-stage amplifiers for capacitive reading of low-amplitude and low-frequency signals.
In one embodiment, an exemplary multi-stage amplifier comprises a plurality of amplification stages, wherein each of the amplification stages comprises an amplifying transistor and an active load, wherein substantially all of the amplification stages have one or more of an increasing DC bias level and a decreasing DC bias level relative to a prior stage, and wherein an output of a given one of the amplification stages is directly applied as an input to a subsequent one of the amplification stages.
In another embodiment, a method for amplifying a signal, comprises obtaining the signal; and applying the signal to a multi-stage amplifier, wherein the multi-stage amplifier comprises a plurality of amplification stages, wherein each of the amplification stages comprises an amplifying transistor and an active load, wherein each of the amplification stages has one or more of an increasing DC bias level and a decreasing DC bias level relative to a prior stage, and wherein an output of a given one of the amplification stages is directly applied as an input to a subsequent one of the amplification stages.
These and other objects, features and advantages of the present disclosure will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
Illustrative embodiments of the disclosure may be described herein in the context of illustrative low-power multi-stage amplifiers for capacitive reading of low-amplitude and low-frequency signals. However, it is to be understood that embodiments of the disclosure are not limited to the illustrative low-power multi-stage amplifiers but instead are more broadly applicable to other suitable devices.
In one or more embodiments, a multi-stage low-power high-gain amplifier is provided, comprised of, for example, a plurality of thin-film heterojunction field effect transistors (HJFETs), a multi-level voltage bias and substantially no capacitive DC blocking between the amplifier stages. In some embodiments, the HJFETs are biased in the sub-threshold regime and have pinch-off voltages that are substantially zero.
While one or more illustrative embodiments employ heterojunction field effect transistors, other transistor types, such as metal oxide semiconductor field effect transistors (MOSFETs), may be employed, as would be apparent to a person of ordinary skill in the art.
As discussed above, non-invasive reading of bio-electric signals from the body is inherently challenging because the signals are often weak and much of the information is often at low frequencies. For example, an Electroencephalogram (EEG) that measures brain activity would be measuring signals in the range of 1˜50 μV. Similarly, an electrooculogram (EOG) that measures eye activity would be measuring signals in the range of 1˜50 mV. Electrocardiograms (ECGs) that measure heart activity would be measuring signals in the range of 10˜100 mV (fetal ECGs may be as low as 1˜10 μV), while electrogastrograms (EGGs) that measure stomach activity would be measuring signals in the range of 1˜10 mV, and electromyograms (EMGs) that measure muscle activity would be measuring signals in the range of 10˜100 mV.
The first amplification stage 110-1 receives a DC bias from an input DC bias circuit 120, and receives an AC input signal through an input capacitor, CIN. In one or more embodiments, the AC input signal is a biological signal obtained by capacitive coupling to a biological medium through the input capacitor, CIN. The input DC bias circuit 120 may include a passive resistor, RIN, as in the embodiment of
In the n-channel embodiment of
In the embodiment of
In one or more embodiments, the amplifying transistors 130 and active loads 140 of each stage 110 are biased in a sub-threshold regime at a VGS equal to approximately the pinch-off voltage (or threshold voltage) of the transistors, as discussed further below in conjunction with
Exemplary values for the drain supply voltage, Vdd, and number of stages, N, in the multi-stage amplifier 100 are discussed further below in conjunction with
Consider the following example that employs n-channel HJFET devices with sub-threshold DC bias:
V
bi
≈E
g/2q+(kT/q)ln(ND/ni)
V
p
≈V
bi−(qND/2εSi)tSi2
I
D
≈I
D0 exp[q(VGS−Vp)/nkT][1−exp(−qVDS/kT)]
where:
Vbi: built-in potential of gate heterojunction;
Vp: pinch-off voltage of HJFET;
Eg: bandgap of crystalline silicon (c-Si) (e.g., LTPS (low-temperature polycrystalline silicon));
ND: c-Si doping;
ni: intrinsic carrier density in c-Si;
tSi: c-Si thickness;
k: Boltzmann Constant;
T: absolute temperature;
q: electron charge;
ID0: HJFET drain current at VGS=Vp and VDS>>kT/q (i.e., the thermal voltage, which is 26 mV at room temperature); and
n: ideality factor of gate heterojunction (1≤n≤2).
The transconductance, gin, can be expressed as follows:
g
m
=∂I
D
/∂V
GS
=qI
D
/nkT
The output resistance, rout, can be expressed as follows:
r
out=(∂ID/∂VDS)−1=(kT/qID)exp(qVDS/kT)
This example demonstrates a moderately high transconductance, gm, despite a low HJFET drain current, ID. For instance, if ID=50 nA and n=1.3, then gm≈1.5 μA/V at room-temperature. In addition, the example demonstrates a high output resistance, rout, so far as VDS>>kT/q. For instance, if ID=50 nA and VDS=0.25V, then rout≈8 GΩ, at room-temperature.
Note the above expressions and the derived conclusions are also applicable to MOSFET devices; except that the expression for the HJFET pinch-off voltage (Vp) must be replaced with the well-known expression for the MOSFET threshold voltage.
The first amplification stage 210-1 receives a DC bias from an input DC bias circuit 220, and receives an AC input signal through an input capacitor, CIN, in a similar manner as
In the p-channel embodiment of
In the embodiment of
In one or more embodiments, the amplifying transistors 230 and active loads 240 of each stage 210 are biased in a sub-threshold regime at a VGS approximately equal to the pinch-off voltage or the threshold voltage, as discussed further below in conjunction with
In some embodiments, the amplifying transistors 130, 230 and active loads 140, 240 of each stage 110, 210 (of
As shown in
It is noted that the term “pinch-off” voltage is commonly used for (hetero) junction field effect transistors and the term “threshold voltage” is commonly used for metal oxide field effect transistors. From a circuit design perspective, a pinch-off voltage is essentially the same as threshold voltage.
It is further noted that the HJFET equations provided herein can also be applied for MOSFET devices by replacing the HJFET pinch-off voltage with the MOSFET threshold voltage, as would be apparent to a person of ordinary skill in the art. Moreover, the equations provided for n-channel devices are readily applicable to p-channel devices with minor adjustments to account for the opposite carrier types and voltage polarities, as would be again apparent to a person of ordinary skill in the art.
As noted above, in one or more embodiments, the amplifying transistors 130, 230 and active loads 140, 240 of each stage 110, 210 (of
In one example, a plurality of HJFETs having the same dimensions are biased in the sub-threshold regime and the bias levels of the amplifier stages increase in equal voltage steps, as illustrated in the embodiment of
I
D1
=I
D2
=I
D0 exp[q(VGS−VP)/nkT]=ID
g
m1
=qI
D
/nkT
r
out1
=r
out2=(kT/qID)exp[qVdd/(N+1)kT]
Therefore, the voltage gain of the m-th stage (AV,m) is given by:
The voltage gain of the multi-stage amplifier (AV) is the product of the voltage gains of the N stages and given by:
A
V
=V
out,N
/V
in=(AV,m)N=(½n)N exp[qVddN/(N+1)kT]
The optimum N (which results in maximum AV) may be obtained by calculating the derivate of AV (or equivalently the derivative of the natural logarithm of AV) with respect to N, and equating the result to zero, as follows:
ln AV=−N ln(2n)+N/(N+1)(qVdd/kT)
θ(ln AV)/N=−ln(2n)+(qV/kT)/(N+1)2=0
The optimum N obtained from solving the above equation is given by:
therefore the optimum number of stages is an integer close to Nopt.
The first amplification stage 610-1 receives a DC bias from an input DC bias circuit 620, and receives an AC input signal through an input capacitor, CIN. In one or more embodiments, the AC input signal is a biological signal obtained by capacitive coupling to a biological medium through the input capacitor, CIN. In the illustrated embodiment, the input DC bias circuit 620 comprises an active load.
In the example of
It is noted that if 7 stages are used (N=7), VDS=Vdd/(N+1)=0.188V which is ˜7kT/q at room temperature. Typically, ˜5kT/q is sufficient to ensure saturation in the subthreshold regime; however, to increase the design margin, N=5 was used and VDS=0.25V≈10kT/q at room-temperature. It is further noted that at 125° C., 0.188V≈5kT/q, whereas 0.25V≈7kT/q, which provides a wider voltage margin for saturation.
It is also noted that an HJFET was used as the input resistor (e.g., in the form of an active load). If the amplitude of the input signal is much lower than kT/q (amp(Vin)=1 μV in this example), ID=ID0[1−exp(−qVds/kT)]≈ID0qVds/kT for this HJFET; equivalent to a linear resistor. Alternatively, ohmic resistors (elements) comprised of a-Si, poly-Si, etc. may be used.
For an input signal having an amplitude of 1 μV; the amplitude of the output signal is approximately 100 mV, as determined by circuit simulation using HJFET device parameters extracted from the measurement of the fabricated devices. Thus, the gain of this exemplary amplifier is approximately 100,000. Each stage consumes less than 50 nA of standby current.
In the previous example of
In one or more embodiments, the resistance of the input bias network, Rin, must be small enough to generate thermal noise (4kTRin)1/2 sufficiently smaller than that of the input signal (e.g., ˜0.1 μV for 500 KΩ at room temperature). The product of the input resistance and the input capacitance of the input bias network, Rin×Cin, must be large enough to allow sufficiently low frequencies of interest (e.g., note cut-off frequency≈½πRinCin).
In some embodiments, the HJFETs may be biased in saturation above pinch-off; however, these embodiments may exhibit lower gain and/or higher power consumption compared to embodiments using subthreshold operation. Similarly, MOSFETs may be biased in saturation above threshold, in some embodiments.
In one or more embodiments, the HJFET pinch-off voltage may be negative and in order to bias the HJFET in the sub-threshold regime without requiring additional negative bias supply for the gate, an HJFET pair may be used as shown in
where μn is the electron mobility and the remaining parameters were defined above. In the case of MOSFET devices, the same approach may be used to determine the operation regime of M3 using the well-known MOSFET equations for the linear and saturation regimes above threshold.
It is to be understood that the terms “about,” “approximately,” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error is present such as, by way of example only, 2% or less than the stated amount.
Embodiments of the disclosure as shown in
A multi-stage amplifier, such as shown in
In this regard, although embodiments of the disclosure have been described herein with reference to the accompanying drawings, it is to be understood that embodiments of the disclosure are not limited to the described embodiments, and that various changes and modifications may be made by one skilled in the art resulting in other embodiments of the disclosure within the scope of the following claims.
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
