Patent Application
20160181983
I. Field
The present disclosure relates generally to electronics, and more specifically to low power amplifiers.
II. Background
A wireless device (e.g., a cellular phone or a smartphone) in a wireless communication system may transmit and receive data for two-way communication. For example, the wireless device may operate in a frequency division duplexing (FDD) system or in a time division duplexing system (TDD). The wireless device may include a transmitter for data transmission and a receiver for data reception. Thus, the wireless device may process both analog and digital signals in order to provide communication and/or data services.
Operational Transconductance Amplifiers (OTAs) are common components in many analog/mixed-signal systems. OTAs are used in mixed signal systems like Delta Sigma analog to digital converters (ADC) and Pipelined ADCs, which are popular ways to realize robust ADCs that are relatively immune to transistor parameter variations. Unfortunately, due to shrinking supply voltages in deep submicron technologies, it has become increasingly difficult to provide amplification with acceptable DC gain. While it is possible to use multi-stage architectures like Miller compensated amplifiers and feed forward amplifiers to get around this issue, they are either not very power efficient and/or do not possess good settling behavior important in many switched capacitor circuits and usually have a noise penalty. Furthermore, in systems like MASH delta sigma ADCs, DC gain and settling are the very important parameters that decide the overall ADC performance and a significant portion of the power budget is spent in achieving these.
It is therefore desirable to have a low power operational transconductance amplifier that overcomes the disadvantages of conventional circuits.
The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.
Wireless device 110 may also be referred to as a user equipment (UE), a mobile station, a terminal, an access terminal, a subscriber unit, or a station. Wireless device 110 may be a cellular phone, a smartphone, a tablet, a wireless modem, a personal digital assistant (PDA), a handheld device, a laptop computer, a smartbook, a netbook, a cordless phone, a wireless local loop (WLL) station, a Bluetooth device, or other communicating device. Wireless device 110 may communicate with devices in the wireless system 120. Wireless device 110 may also receive signals from broadcast stations (e.g., a broadcast station 134), or signals from satellites (e.g., a satellite 150) in one or more global navigation satellite systems (GNSS). Wireless device 110 may support one or more radio technologies for wireless communication such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11. In an exemplary embodiment, the wireless device 110 comprises the operational transconductance amplifier 112 to provide amplification for use with various circuitries in the wireless device 110. For example, the operational transconductance amplifier may be used to provide amplification in switched capacitor circuits, analog to digital converters, and/or other circuitry within the wireless device 110. The OTA 112 is designed to utilize less power and provide improved DC gain and unity gain bandwidth over conventional amplifier circuits.
In general, any number of band groups may be defined. Each band group may cover any range of frequencies, which may or may not match any of the frequency ranges shown in
The transconductance stage 402 includes transconductance circuit 408 that has a transconductance value of Gm1 and transconductance circuit 410 that has a transconductance value of Gm2. The transconductance circuits 408 and 410 receive the first differential input voltage Vii and convert this voltage signal to generate a first current signal 422 and a second current signal 416. The first current signal 422 is input to the current summation stage 406 and the second current signal 416 is input to a first current amplifier 418 of the current amplification stage 404. The first current amplifier 418 amplifies (or multiplies) the second current signal 416 by a selected factor (K1) to generate a first amplified (or multiplied) current signal 420 that is also input to the current summation stage 406. The factor (K1) is typically a small integer value but may have any desired value.
The transconductance stage 402 also includes transconductance circuit 412 that has a transconductance value of Gm1 and transconductance circuit 414 that has a transconductance value of Gm2. The transconductance circuits 412 and 414 receive the second differential input voltage Vi2 and convert this voltage signal to generate a third current signal 430 and a fourth current signal 424. The third current signal 430 is input to current summation stage 406 and the fourth current signal 424 is input to a second current amplifier 426 (or multiplier) of the current amplification stage 404. The current amplifier 426 amplifies (or multiplies) the fourth current signal 424 by a selected factor (K2) to generate a second amplified (or multiplied) current signal 428 that is also input to the current summation stage 406. The factor (K2) is typically a small integer value but may have any desired value. In an exemplary embodiment, the factors K1 and K2 are substantially the same value. In an exemplary embodiment, Gm1 is substantially the same value as Gm2; however, in other embodiments Gm1 and Gm2 have different values.
The current summation stage 406 sums together selected current signals that it receives at its inputs and generates a first summed current signal (IS1) that is converted by a first impedance 434 at the terminal 432 to the first differential output voltage (VO1) that appears at terminal 432. The current summation stage 406 also sums together selected current signals that it receives at its inputs and generates a second summed current signal (IS2) that is converted by a second impedance 438 at the terminal 436 to the second differential output voltage signal (VO2) that appears at the terminal 436.
Thus, the OTA 302 operates to convert input voltages to current signals, amplify and selectively sum the current signals to generate summed current signals that are converted to output voltages. The exemplary embodiments of the OTA consume significantly lower power compared to a conventional OTA, while achieving similar or better performance in terms of DC gain and unity gain bandwidth.
The OTA 500 comprises the first Gm circuit 408 that includes transistors 514 and 516 in a cascode configuration. The transistor 514 has a source terminal connected to an output terminal of the current source 508 and a drain terminal connected to a source terminal of transistor 516. A drain terminal of the transistor 516 outputs the first current signal 422. A gate terminal of the transistor 514 is connected to receive the differential input voltage Vi1.
The OTA 500 comprises the second Gm circuit 410 that includes transistors 504 and 506 in a cascode configuration. The transistor 504 has a source terminal connected to the output terminal of the current source 508 and a drain terminal connected to a source terminal of the transistor 506. A drain terminal of the transistor 506 outputs the second current signal 416. A gate terminal of the transistor 504 is connected to receive the differential input voltage Vi1. A gate terminal of the transistor 506 is connected to a gate terminal of the transistor 516.
The OTA 500 comprises the third Gm circuit 412 that includes transistors 530 and 532 in a cascode configuration. The transistor 530 has a source terminal connected to the output terminal of the current source 508 and a drain terminal connected to a source terminal of the transistor 532. A drain terminal of the transistor 532 outputs the third current signal 430. A gate terminal of the transistor 530 is connected to receive the differential input voltage Vi2.
The OTA 500 comprises the fourth Gm circuit 414 that includes transistors 522 and 524 in a cascode configuration. The transistor 522 has a source terminal connected to the output terminal of the current source 508 and a drain terminal connected to a source terminal of the transistor 524. A drain terminal of the transistor 524 outputs the fourth current signal 424. A gate terminal of the transistor 522 is connected to receive the differential input voltage Vi2.
A gate terminal of the transistor 524 is connected to a gate terminal of the transistor 532. The gate terminal of the transistor 524 also is connected to the gate terminal of the transistor 506. In an exemplary embodiment, the Gm circuits 408, 410, 412 and 414 have transistors that are sized (e.g., channel lengths and widths) to provide the appropriate Gm values.
The gate terminals of transistors 516, 506, 524 and 532 are connected to receive a first voltage bias signal (vb1). The first voltage bias signal (vb1) is generated using a bias circuit or any suitable circuitry (not shown) that is known to those with skill in the art. The value of vb1 is chosen such that it is low enough to keep the transistors 514, 504, 522 and 530 in saturation. The value of vb1 is also chosen such that it is high enough so that the transistors 516, 506, 524 and 532 are in the saturation region during the highest voltage swings at the OTA outputs.
The first current amplifier 418 comprises common source transistors 538 and 540. The gate terminals of the transistors 538 and 540 are connected together and also connected to the drain terminal of the transistor 506 to receive the second current signal 416. The drain terminal of the transistor 540 is connected to its gate terminal and the drain terminal of the transistor 538 outputs the first amplified current 420. The first current amplifier 418 amplifies the first current signal 416 by a factor of (K) to generate the first amplified current signal 420.
The second current amplifier 426 comprises common source transistors 546 and 548. The gate terminals of the transistors 546 and 548 are connected together and also connected to the drain terminal of the transistor 524 to receive the fourth current signal 424. The drain terminal of the transistor 548 is connected to its gate terminal and the drain terminal of the transistor 546 outputs the second amplified current signal 428. The second current amplifier 426 amplifies the fourth current signal 424 by a factor of (K) to generate the second amplified current signal 428. It should be noted that the currents 422, 416, 424, 430, 420, and 428 are incremental small signal currents that flow through the circuit as indicated. These currents may not be the same as the DC current which flows generally from Vdd to the circuit (signal) ground.
The summation stage 406 includes a first summing circuit 552 and a second summing circuit 558. The first summing circuit 552 comprises transistor 554 that has a source terminal connected to the drain terminal of the transistor 538 to receive the first amplified current 420. The transistor 554 also has a drain terminal connected to the drain terminal of the transistor 532 at node 432 to receive the third current 430. The gate terminals of transistors 560 and 554 are connected to receive a second voltage bias signal (vb2). The second voltage bias signal (vb2) is generated using a bias circuit or any suitable circuitry (not shown) that is known to those with skill in the art. The value of vb2 is chosen such that it is high enough to keep the transistors 538, 540, 548 and 546 in saturation. The value of vb2 also is chosen to be low enough so that the transistors 560 and 554 are in the saturation region during the highest voltage swings at the OTA outputs.
The first summing circuit 552 sums the current 420 with the current 430 to generate a summed current that is converted to the differential output voltage Vo1 at the node 432 based on a first impedance that is formed by the output impedance (Rout1) looking into the node 432. For example, the output impedance (Rout1) looking into the node 432 is a parallel combination of the impedances Rup1 and Rdn1, so that the output impedance (Rout1) is determined from the expression [(Rup1×Rdn1)/(Rup1+Rdn1)].
The second summing circuit 558 comprises transistor 560 that has a source terminal connected to the drain terminal of the transistor 546 to receive the second amplified current 428. The transistor 560 also has a drain terminal connected to the drain terminal of the transistor 516 at node 436 to receive the first current 422. The transistor 560 has a gate terminal that is connected to a gate terminal of the transistor 554. The second summing circuit 558 sums the current 428 with the current 422 to generate a summed current that is converted to the second differential output voltage Vo2 at the node 436 based on a second impedance that is formed by the output impedance (Rout2) looking into the node 436. For example, the output impedance (Rout2) looking into the node 436 is a parallel combination of the impedances Rup2 and Rdn2, so that the output impedance (Rout2) is determined from the expression [(Rup2×Rdn2)/(Rup2+Rdn2)].
In various exemplary embodiments, the current amplification stage 404 increases the effective transconductance (Gm) of the transconductance stage 402 while not reducing the output impedances. This increases the DC gain, which is the product of Gm and Rout. There is also an increase in the unity gain bandwidth (UGBW), which is directly proportional to Gm for a given load capacitor and feedback factor. Thus, if the current gain is K, the effective Gm for the example shown in
It should also be noted that the transistor devices shown in
During operation 602, currents are generated from differential input voltage signals. For example, the Gm circuits 408, 410, 412, and 414 generate the currents 422, 416, 430, and 424 from the first input voltage Vi1 and the second input voltage Vi2. In an exemplary embodiment, the Gm circuits 408 and 412 have the same transconductance values and the Gm circuits 410 and 414 have the same transconductance values, which may also be equal to the Gm circuits 408 and 412.
During operation 604, one current associated with each input voltage signal is amplified. For example, the current amplifier 418 amplifies the current 416 to generate the first amplified current 420. The current amplifier 426 amplifies the current 424 to generate the second amplified current 428.
During operation 606, the amplified and non-amplified currents are selectively summed together. For example, the first summing circuit 552 sums the current 420 and the current 430 and the second summing circuit 558 sums the current 428 and the current 422.
During operation 608, output voltages are generated from the summed currents.
For example, the first summing circuit 552 generates the output voltage Vo1 at node 432 based on its summed current and the output impedance (Rout1) and the second summing circuit 558 generates the output voltage Vo2 at the node 436 based on its summed current and the output impedance (Rout2).
Accordingly, the OTA 500 performs the operations described above to amplify differential voltages in a device to provide improved DC gain and unity gain bandwidth over conventional amplifier circuits. It should be noted that the operations 600 are exemplary and that minor changes, modifications, rearrangements and other changes to the operations 600 are within the scope of the exemplary embodiments.
The apparatus 700 includes a first means (702) for converting a first voltage signal to first and second current signals, which in an exemplary embodiment comprises the first 408 and second 410 Gm circuits. The apparatus 700 also comprises a second means (704) for converting a second voltage signal to third and fourth current signals, which in an exemplary embodiment comprises the third 412 and fourth 414 Gm circuits. The apparatus 700 also comprises a third means (706) for amplifying the second and fourth current signals to generate first and second amplified current signals, respectively, which in an exemplary embodiment comprises the first 418 and second 426 current amplifiers. The apparatus 700 also comprises a fourth means (708) for summing the third current signal and the first amplified current signal to generate a first output voltage signal, which in an exemplary embodiment comprises the first summing circuit 552. The apparatus 700 also comprises a fifth means (710) for summing the first current signal and the second amplified current signal to generate a second output voltage signal, which in an exemplary embodiment comprises the second summing circuit 558.
The exemplary embodiments of an OTA described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronic device, etc. The exemplary embodiments of the OTA may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.
An apparatus implementing an exemplary embodiment of an OTA described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.
The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but the disclose is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
