Patent Application
20140177764
This disclosure relates generally to the field of wireless communication systems.
By virtue of design, modern wireless communication devices employ receiver elements that are active and processing, even when the devices are not engaged in actual communications. In particular, communications based on wireless technologies, such as, for example, Wi-Fi, WiMax, WWAN, WLAN, WPAN, BlueTooth, BlueTooth Low Energy, etc. often require wireless communications devices to operate in “listening mode,” namely, detect, receive, and process signals that may include relevant packet data while the devices are not actively communicating.
Given the significant amount of time a wireless communication device may spend in listening mode as well as the energy used to maintain receiver elements active during such a mode, it will be appreciated that a substantial amount of power may be consumed by communication devices that are not actively communicating.
In the description that follows, like components have been given the same reference numerals, regardless of whether they are shown in different embodiments. To illustrate an embodiment(s) of the present disclosure in a clear and concise manner, the drawings may not necessarily be to scale and certain features may be shown in somewhat schematic form. Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments and/or in combination with or instead of the features of the other embodiments.
In accordance with various embodiments of this disclosure, what is disclosed are wireless systems, devices, and methods in which a communications interface unit is configured to receive a wireless signal and includes a first channel path having a first down-converter to generate a first analog baseband signal and a first ADC to generate first digital samples as well as second channel path having a second down-converter that operates at a frequency orthogonal to the first down-converter and generates a second analog baseband signal and a second ADC to generate second digital samples. In addition, a packet detector unit is used to detect a beginning frame of packet data, wherein the second channel path is deactivated until the beginning frame of the packet data is detected and the packet detector detects the beginning frame of the packet data based on only the first digital samples provided by the first channel path.
These and other features and characteristics, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, will become more apparent upon consideration of the following description and the appended claims with reference to the accompanying drawings, all of which form a part of this specification, wherein like reference numerals designate corresponding parts in the various figures. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended as a definition of the limits of claims. As used in the specification and in the claims, the singular form of “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise.
By way of review, the inventor has observed that a substantial amount of power may be consumed by wireless communication devices during the listening modes specified by various wireless technologies/standards. Such power consumption may be due, in part, to elements of the receiver chain, such as, for example, radio-frequency (RF)/intermediate-frequency (IF) down-converters, analog/digital converters (ADCs), packet detection modules, etc. that are actively receiving and processing signals in an effort to detect relevant packet data. Generally, many wireless communication devices maintain both, in-phase (I-channel) and quadrature-phase (Q-channel) ADCs and detection elements energized during the listening mode period.
In view of the above, what is proposed is a wireless configuration and methodology that effectively detects packet data by only using one of the ADC channels (i.e., I-channel OR Q-channel) elements while keeping the other ADC channel deactivated until a packet is detected. Upon detecting a packet, the previously deactivated ADC channel and associated elements are turned on, to enable the proper performance of the packet decoding process. The deactivation of one of the ADC channels during listening modes may result in significant power savings.
With this said,
In the illustrative example, wireless communication device 200 includes a variety of peripherals, such as, for example, display screen 204, speaker 206, microphone 208, camera 210, input devices 212, etc. wireless as well as an operating system (OS) 203 to manage the software applications as well as the hardware devices and resources.
Moreover, wireless communication device 200 includes memory 214 and a system-on-chip (SoC) chipset 220. The wireless communication device 200 may also include a bus infrastructure and/or other interconnection means to connect and communicate information between the various components of communication device 200.
In some embodiments, SoC 220 may be part of a core processing or computing unit of wireless communication device 200, and is configured to receive and process input data and instructions, provide output and/or control other components of communication device 200 in accordance with embodiments of the present disclosure. SoC 220 may include a microprocessor, a memory controller, a memory and other components. The microprocessor may further include a cache memory (e.g., SRAM), which along with the memory of SoC 220 may be part of a memory hierarchy to store instructions and data. The microprocessor may also include one or more logic modules such as a field programmable gate array (FPGA) or other logic array. Communication between the SoC 220's microprocessor and memory may be facilitated by the memory controller (or chipset), which may also facilitate communication with the peripheral components.
Memory 214 of wireless communication device 200 may be a dynamic storage device coupled to the bus infrastructure and configured to store information, instructions, and programs to be executed by processors of SoC 220 and/or other processors (or controllers) associated with communication device 200. Some of all of memory 214 may be implemented as Dual In-line Memory Modules (DIMMs), and may be one or more of the following types of memory: Static random access memory (SRAM), Burst SRAM or SynchBurst SRAM (BSRAM), Dynamic random access memory (DRAM), Fast Page Mode DRAM (FPM DRAM), Enhanced DRAM (EDRAM), Extended Data Output RAM (EDO RAM), Extended Data Output DRAM (EDO DRAM), Burst Extended Data Output DRAM (BEDO DRAM), Enhanced DRAM (EDRAM), synchronous DRAM (SDRAM), JEDECSRAM, PCIOO SDRAM, Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), SyncLink DRAM (SLDRAM), Direct Rambus DRAM (DRDRAM), Ferroelectric RAM (FRAM), or any other type of memory device. Wireless communication device 200 may also include read only memory (ROM) and/or other static storage devices coupled to the bus infrastructure and configured to store static information and instructions for processors of SoC 220 and/or other processors (or controllers) associated with communication device 200.
Returning to
During listening mode (i.e., while wireless communication device 200 is not in active communications), system 100 is configured to detect relevant packet data by only employing one of the two ADC channel paths and deactivating the other channel path. In the non-limiting embodiment of
It should be appreciated that, for the sake of tractability and clarity, various standard receiver chain elements and details regarding those elements as well as the communication interface unit and packet decoder unit, such as, for example, antennae, low noise amplifiers, tuners, attenuators, filters, equalizer, forward error correction (FEC) decoders, timing and carrier recovery circuitry, phase-locked loops, etc. have been omitted, as such elements are not necessary for the understanding of the principles disclosed herein.
As shown in
It will be appreciated that reference signals cos(ωCt), sin(ωCt), may be outputted from a local oscillator, voltage controlled oscillator, numerically-controlled oscillator etc. (not shown). After down-converting, two orthogonally-shifted, analog, baseband, component signals are generated, namely an analog, baseband, I-component signal and an analog, baseband, Q-component signal, respectively.
The analog, baseband, I-component signal is inputted to ADC 104I, which is configured to sample the analog signal to generate digital I-component samples. Similarly, baseband, Q-component signal is inputted to ADC 104Q, which samples the analog signal to generate digital Q-component samples.
As noted above, during listening mode, the packet detection process is performed by one of the ADC channel paths while the other ADC channel path is deactivated. As depicted in
Focusing on the activated I-channel path elements, received signal R is mixed with reference signal, cos(ωCt), operating at carrier frequency ωC by down-converter 102I to produce an analog, baseband, I-component signal which, in turn, is inputted to ADC 104I that samples the analog signal to generate digital I-component samples. These I-component samples are then forwarded to packet detection and carrier frequency ωC offset estimator unit 106.
Unit 106 is configured to detect a relevant packet by looking for the start of an actual packet frame, namely looking for a preamble and/or a sync pattern. Unit 106 achieves the detection by analyzing cross-correlation peaks in the digital I-component samples and also provides an estimate of the carrier frequency ωC offset.
In particular, unit 106 cross-correlates the I-component samples with a complex-valued reference pattern for consecutive, predetermined time intervals (e.g., every 0.4 μsec, 0.8 μsec, etc.). The reference pattern contains information similar to an actual packet frame preamble/sync pattern. The cross-correlation process generates values, in which the absolute values (i.e., magnitude of cross-correlation values) may be taken and compared to a predetermined threshold. When the magnitude of the cross-correlation values exceed the predetermined threshold, it is indicative of cross-correlation peaks and, consequently, the start of an actual packet frame. At such time, switch mechanism 110 is actuated to activate the Q-channel path components and couple those components to the received signal R in order for both digital I-component and Q-component samples to be processed by packet decoder unit 108.
As noted above, unit 106 is also configured to provide an estimate of the carrier frequency ωC offset. That is, the cross-correlation values that exceed the predetermined threshold (i.e., representing cross-correlation peaks) also contain complex angle information due to the complex-valued reference pattern used to cross-correlate the digital I-component samples. In subsequent cross-correlation time intervals, the complex angle information is examined again and unit 106 determines how the complex angle information has changed during the time intervals. Unit 106 then estimates what the carrier frequency ωC offset is and commensurately provides an offset correction value to compensate for the estimated carrier frequency ωC offset. As such, how the complex angle information changes within the cross-correlation predetermined time intervals provides a measure of how the carrier frequency ωC offset should be adjusted.
In particular, upon the cross-correlation values exceeding the predetermined threshold, the complex angle information is examined. Because of the deactivation of Q-component samples, the sign of the angle of the cross-correlation value may be either positive or negative, so initially it is unknown if the carrier frequency ωC offset is positive or negative. Unit 106 may, therefore, guess at or assume a sign, and apply this guessed-at correction value to compensate for the carrier frequency ωC offset. The cross-correlation values are recomputed. If the complex angle information indicates a residual carrier frequency offset of zero, the correct assumption was made. If the complex angle information indicates a residual carrier frequency offset of approximately twice the initial estimate, the incorrect assumption was made and the other sign for the carrier frequency estimate is chosen.
As an illustrative example, suppose that upon detecting a cross-correlation peak, the complex angle information indicates +0.2°, at which point, unit 106 introduces an initial carrier frequency ωC offset correction value of −0.2° to packet decoder unit 108. In subsequent 0.8 μsec cross-correlation intervals, the complex angle information may indicate a rotation of +0.4°. Unit 106 then reverses the sign of the initial guess and provides to packet decoder unit 108 an offset correction value of +0.2° to compensate for the carrier frequency ωC offset. In this example, had the initial correction value been selected as +0.2 degrees, then the subsequent measurement would have been approximately zero (e.g., exactly zero in the absence of noise).
It will be appreciated that the described embodiments are by way of example and are not intended to be limiting. As such, various modifications to the described embodiments may be implemented without departing from the principles of the disclosed subject matter. For example, IEEE 802.11b standards specify packet preamble comprising a time-domain BPSK-based signal as the packet preamble. It will be appreciated that the demodulation/decoding of BPSK signals only employ one ADC channel, either the I-channel or Q-channel—but not both, as the signal energy only exists in one of the channels.
However, the non-limiting embodiment of
In addition, with this configuration, when switching to full decode mode upon determining the beginning of a packet frame, the artificial frequency offset is also applied to the local oscillator of down-converter 102Q i.e., mixing the received signal R with sin(ωCt+φart. By using this technique, the sign ambiguity described above is avoided.
In other embodiments, process 250 may be implemented machine readable instructions for executing the various operations noted above. The machine readable instructions may be implemented in software stored on tangible computer readable media such as, for example, a flash memory, a CD-ROM, a floppy disk, a hard drive, a digital video (versatile) disk (DVD), or other memory devices, but persons of ordinary skill in the art will readily appreciate that the entire algorithm and/or parts thereof could alternatively be executed by a device other than a processor and/or implemented in firmware or dedicated hardware in a well known manner (e.g., it may be implemented by an application specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable logic device (FPLD), a field programmable gate array (FPGA), discrete logic, or the like).
Returning to
At block 254, received signal R is mixed with reference signal, cos(ωCt), operating at carrier frequency ωC to produce an analog, baseband, I-component signal. The analog, baseband, I-component signal is then sampled, at block 256, to generate digital I-component samples.
At block 258, process 250 performs cross-correlation of the digital I-component samples with a reference pattern for consecutive, predetermined time intervals (e.g., cross-correlation time intervals of 0.4 μsec, 0.8 μsec, etc.). The cross-correlation process generates cross-correlation value in which, at block 260, the magnitude of cross-correlation values are compared to a predetermined threshold. If the of the cross-correlation values do not exceed the predetermined threshold, then at block 262, process 250 moves to the next consecutive cross-correlation time interval and performs cross-correlation of the digital I-component samples associated with that time interval.
If the magnitude of the cross-correlation values exceed the predetermined threshold, it is indicative of cross-correlation peaks and, consequently, the start of an actual packet frame. At such time, process 250 commences the activation of Q-channel elements as well as the determination of carrier frequency ωC offset estimate. These two operations may be executed concurrently or in close timing to each other.
As such, at block 264, the Q-channel elements are activated and coupled to the received signal R and, at block 266, received signal R is mixed with reference signal, sin(ωCt), operating at carrier frequency ωC to produce an analog, baseband, Q-component signal. The analog, baseband, Q-component signal is then sampled, at block 268, to generate digital Q-component samples.
Concurrent with, or in close succession to, the Q-channel activation operation, process 250 executes the determination of carrier frequency ωC offset estimate at block 270. As noted above, because the carrier frequency ωC offset is initially unknown, an assumed carrier frequency ωC offset correction sign is introduced to the packet decoding procedures. In subsequent cross-correlation time intervals, the complex angle information is examined again and process 250 determines how the complex angle information has changed during the corresponding time intervals to estimate what the carrier frequency ωC offset is. Then, at block 272, process 250 provides an estimated carrier frequency ωC offset correction.
Finally, at block 274, process 250 forwards the I-channel samples, Q-channel samples, and estimated carrier frequency ωC offset correction to the packet decoding procedures.
Having thus described the novel concepts and principles of the optimization of carrier recovery performance, it will be apparent to those skilled in the art after reading this detailed disclosure that the foregoing detailed disclosure is intended to be presented by way of example only and is not limiting. Various alterations, improvements, and modifications will occur and are intended to those skilled in the art, though not expressly stated herein. The alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary aspects of this disclosure. Additionally, the recited order of processing elements or sequences, or the use of numbers, letters, or other designations therefore, is not intended to limit the claimed processes and methods to any order except as can be specified in the claims. Although the above disclosure discusses through various examples what is currently considered to be a variety of useful aspects of the disclosure, it is to be understood that such detail is solely for that purpose, and that the appended claims are not limited to the disclosed aspects, but, on the contrary, are intended to cover modifications and equivalent arrangements that are within the spirit and scope of the disclosed aspects.
