Low-power power-on reset circuit

Abstract

The low-power power-on reset circuit includes a NOT gate device, a time delay device, a wave shaping device and a NOR gate device, with which the present invention can provide a low power power-on reset circuit that can be formed by a complementary metal oxide semiconductor (CMOS), such that a lower power consumption and a higher noise margin can both be provided.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a prior power-on reset circuit;

FIG. 2 is a characteristic curve diagram illustrating the prior art in FIG. 1;

FIG. 3 is a schematic diagram of another prior power-on reset circuit;

FIG. 4 is a characteristic curve diagram illustrating the prior art in FIG. 3;

FIG. 5 is a schematic diagram depicting one embodiment of the present invention;

FIG. 6 is a circuit diagram depicting the embodiment of the present invention;

FIG. 7 shows a set of partially magnified waveforms in accordance with the embodiment of the present invention;

FIG. 8 shows a set of waveforms in accordance with the embodiment of the present invention; and

FIG. 9 is a schematic diagram depicting another embodiment of the present invention.

Claims

1. A low-power power-on reset circuit comprising: a NOT gate device having an input and an output, the input of the NOT gate device being configured to input a power voltage;at least one time delay device having an input and an output, the input of the time delay device being electrically connected to the output of the NOT gate device;a wave shaping device having an input and an output, the input of the wave shaping device being electrically connected to the output of the time delay device; anda NOR gate device having a first input, a second input and an output, the first input of NOR gate device being electrically connected to the output of the wave shaping device, and a power-on-reset signal being outputted by the output of the NOR gate device.

2. The low-power power-on reset circuit as claimed in claim 1, wherein the time delay device further comprises a first NOT gate device, a second NOT gate device and a first capacitor device, the input of the first NOT gate device is electrically connected to the input of the time delay device, the output of the first NOT gate device is electrically connected to one end of the first capacitor device and the input of the second NOT gate device respectively, while the other end of the first capacitor device is electrically connected to GND, the output of the second NOT gate device is electrically connected to the output of the time delay device.

3. The low-power power-on reset circuit as claimed in claim 1, wherein the NOT gate device further comprises an N type MOSFET and a P type MOSFET.

4. The low-power power-on reset circuit as claimed in claim 3, wherein the N type MOSFET comprises a gate, a source and a drain, the P type MOSFET has a gate, a source and a drain.

5. The low-power power-on reset circuit as claimed in claim 4, wherein the input of the NOT gate device is coupled to the gate of the N type MOSFET and the gate of the P type MOSFET.

6. The low-power power-on reset circuit as claimed in claim 4, wherein the output of the NOT gate device is coupled to the drain of the N type MOSFET and the drain of the P type MOSFET.

7. The low-power power-on reset circuit as claimed in claim 4, wherein the source of the N type MOSFET is coupled to GND, the P type MOSFET is coupled to the power voltage.

8. The low-power power-on reset circuit as claimed in claim 1, wherein the NOR gate device further comprises a first N type MOSFET, a second N type MOSFET, a first P type MOSFET and a second P type MOSFET.

9. The low-power power-on reset circuit as claimed in claim 8, wherein the first N type MOSFET has a gate, a source and a drain, and the first P type MOSFET has a gate, a source and a drain.

10. The low-power power-on reset circuit as claimed in claim 9, wherein the first input of the NOR gate device is coupled to the gate of the first N type MOSFET and the gate of the first P type MOSFET.

11. The low-power power-on reset circuit as claimed in claim 9, wherein the second input of the NOR gate device is coupled to the gate of the second N type MOSFET and the gate of the second P type MOSFET.

12. The low-power power-on reset circuit as claimed in claim 9, wherein the output of the NOR gate device is coupled to the drain of the first N type MOSFET and the drain of the second N type MOSFET.

13. The low-power power-on reset circuit as claimed in claim 9, wherein the source of the first N type MOSFET and the source of the second N type MOSFET are both coupled to GND.

14. The low-power power-on reset circuit as claimed in claim 9, wherein the source of the P type MOSFET is coupled to the power voltage.

15. The low-power power-on reset circuit as claimed in claim 9, wherein the drain of the first P type MOSFET is coupled to the source of the second P type MOSFET.

16. The low-power power-on reset circuit as claimed in claim 9, wherein the drain of the second P type MOSFET is coupled to the output of the NOR gate device.

17. The low-power power-on reset circuit as claimed in claim 1, wherein the time delay device further comprises a first NOT gate device, a second NOT gate device, a first capacitor device and a second capacitor device, the input of the first NOT gate device is electrically connected to the input of the time delay device, the output of the first NOT gate device is electrically connected to one end of the first capacitor and the input of the second NOT gate device respectively, the output of the second NOT gate device is electrically to the output of the time delay device and one end of the second capacitor respectively, while the other end of the first capacitor device and the other end of the second capacitor device are electrically connected to GND.

18. The low-power power-on reset circuit as claimed in claim 1, wherein the wave shaping device is a NOT gate device.

19. The low-power power-on reset circuit as claimed in claim 18, wherein the wave shaping device includes an odd numbered NOT gate devices connected in series.