The present invention relates to I/O devices generally and, more particularly, to a method and/or apparatus for implementing a low power receiver for a high voltage interface implemented with low voltage devices.
Conventional circuits use thin gate oxide IO devices to operate reliably on a 1.8V supply. Conventional circuits sometimes implement a comparator-based architecture for a receiver used in high voltage interfaces implemented with low voltage devices. Since such a comparator consumes DC power, this solution has the drawback of having constant power consumption.
It would be desirable to implement a receiver architecture that operates reliably under normal operation where I/O devices operating at one voltage (e.g., in the range of 2.5V/3.3V) may be used to interface with core devices operating at a second voltage (e.g., in the range of 1.8V) to meet LVCMOS JEDEC specifications.
The present invention concerns an apparatus comprising a first stage and a second stage. The first stage may be configured to generate an intermediate signal having a first voltage in response to an input signal having a second voltage received from a pad. The second stage may be configured to generate a core voltage in response to the first voltage. The voltage received from the pad may operate at a voltage compliant with one or more published interface specifications.
The objects, features and advantages of the present invention include providing an I/O device that may (i) reduce DC power consumption, (ii) be implemented using 1.8v I/O devices, (iii) interface with 2.5v/3.5v core supplies, (iv) meet LVCMOS JDEC Specifications, and/or (v) provide a high voltage interface to protect one or more circuits on an Integrated Circuit.
These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:
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The circuit 100 (or 100′) may provide an architecture to implement a receiver that may avoid skewing of the inverter 116. A signal from the PAD 70a may be passed through pass gate 110 as the signal PAD_MOD. The pass gate 110 may have a gate that may be connected to the signal BIAS. The signal BIAS may be implemented as a voltage that is generally designed to be less than 2 Volts across process, voltage and temperature (PVT) variations. 2 Volts may be the approximate reliability limit for a 1.8V IO device. While a 2 volt target for the signal BIAS is provided as an example, the particular voltage for the signal BIAS may be varied to meet the design criteria of a particular implementation.
The pass gate 110 may be implemented as a native device. The pass gate 110 may limit the voltage on the signal PAD_MOD to the value of the voltage of the signal BIAS. The devices in the stages following the circuit 100 may be protected from voltage stress (e.g., voltages that are larger than an operating voltage of the other devices). The signal PAD_MOD may be passed through a diode connected device 112. The device MDIO (112) may present a signal (e.g., PAD-VT) that may operate at the voltage received from the PAD minus Vt, where Vt is a threshold drop from the device MDIO. The voltage threshold Vt may be adjusted by around 0.3 to 0.4V by adjusting the current source IPAD. The signal PAD-VT presented to the inverter 116 may be designed to lag by the voltage threshold Vt from the pad 70a.
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The circuit 100 may be used to clamp a signal received from one of the pads 70a-70n to known voltage if the signal received is floating. The signals received from the pads 70a-70n may be processed to operate as a core level signal to meet JEDEC specifications. The circuit 100 may generate the signal PAD-Vt to help achieve a JEDEC compliant signal. The device 110 may be implemented as a native device. The device may be used to clamp the signal PAD_MOD to be the same as gate voltage (e.g., BIAS) even if input voltage (e.g., PAD) is higher than the gate voltage. The output of the native device 110 will normally be limited to voltage of the signal BIAS.
The various signals of the present invention are generally “on” (e.g., a digital HIGH, or 1) or “off” (e.g., a digital LOW, or 0). However, the particular polarities of the on (e.g., asserted) and off (e.g., de-asserted) states of the signals may be adjusted (e.g., reversed) accordingly to meet the design criteria of a particular implementation.
The terms “may” and “generally” when used herein in conjunction with “is(are)” and verbs are meant to communicate the intention that the description is exemplary and believed to be broad enough to encompass both the specific examples presented in the disclosure as well as alternative examples that could be derived based on the disclosure. The terms “may” and “generally” as used herein should not be construed to necessarily imply the desirability or possibility of omitting a corresponding element.
The present invention may also be implemented by the preparation of ASICs (application specific integrated circuits), Platform ASICs, FPGAs (field programmable gate arrays), PLDs (programmable logic devices), CPLDs (complex programmable logic device), sea-of-gates, RFICs (radio frequency integrated circuits), ASSPs (application specific standard products), one or more integrated circuits, one or more chips or die arranged as flip-chip modules and/or multi-chip modules or by interconnecting an appropriate network of conventional component circuits, as is described herein, modifications of which will be readily apparent to those skilled in the art(s).
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the invention.