The present disclosure relates to analog-to-digital converters (ADCs) and, more particularly, to low-power sigma-delta converters for detection of seismic signals.
Sigma-delta converters are widely used in audio, medical, automotive and transport, entertainment (video gaming), earth-Science (Seismic Signal Detection), and telecommunications applications. Sigma-delta converters are used to quantize an analog input signal to be converted by displacing the quantization noise to a frequency-band spaced away from the band of the signal, such as to be easily filtered out. This results in improvement of the signal-to-noise (SNR) of the digital signal.
The following references include a description on Sigma Delta ADC: “Understanding Delta Sigma Data Converters,” Shreier and Temes, by IEEE Publication, John Wiley 2005; “Design of Multi-bit Delta-Sigma A/D Converters” Y. Geerts, M. Steyaert and Willy Sansen; Kluwer Intl Series in Engineering, May 1, 2002; and “On the implementation of Input-feed forward Delta-Sigma Modulators,” Amed Gharbiya and D. A. Johns, Univ Toronto, IEEE Transactions CAS II Vol. 53 No. 6, June 2006, IEEE.
A typical second-order architecture of a sigma-delta modulator, shown in
In the feed forward architecture of a typical sigma-delta modulator shown in
The second-order single-loop feed forward sigma-delta modulator disclosed by Silva et al. (J. Silva, U. Moon, J. Steensgaard and G. C. Temes, “Wideband low-Fig distortion delta-sigma ADC topology,” El. Letters, 7 Jun. 2001) is shown in
P=Q·(−1+z−1)·z−1;R=Q·z−2;Y=X+Q·(−1+z−1)2.
It should be noted that the useful signal X is not present in nodes P and R, thus the integrators are processing only the quantization-noise (εQ) whose maximum amplitude is about 1.5 times the least significant bit (LSB). This structure may be efficient for multi-bit quantizers, in which the LSB is particularly small.
An alternative feed forward architecture for a sigma-delta converter has been proposed by Nys et al. (O. Nys, K. Henderson, “A 19-Bit Low-Power Multi-bit Sigma-Delta ADC Based on Data Weighted Averaging,” JSSC 1997) and is shown in
P=Q·(−1+z−1)·z−1;R=Q·(2+z−1)·z−1;Y=X+Q·(1−z−1)2.
The advantages of the architecture of
An analog adder may be implemented by way of a passive switched capacitor just upstream to the quantizer, as shown in
According to an alternative approach, an active analog adder is used just upstream the quantizer (L. Picolli, et al., “A 1.0 mW, 71 dB SNDR, −1.8 dBFS Input Swing, Fourth-Order SD Interface Circuit for MEMS Microphones,” ESSCIRC2009), as shown in
It may be desirable for an architecture of a second order switched-capacitor sigma-delta converter to have: a low impedance at the quantizer input; a reduced number of branches; a single DAC; and at most two operational amplifiers. An architecture of a second order switched-capacitor sigma-delta converter that may have all the above characteristics is now disclosed.
The above problems may be addressed by the second switched capacitor stage immediately upstream the quantization stage such to be capable of adding the input signal to be converted with the signal generated by the first stage in the cascade and at the same time of amplifying this sum.
This architecture, while exploiting the benefits of maintaining the second switched capacitor stage immediately upstream of the quantization stage, may implement an analog adder function and an amplification, thus avoiding the presence of a load between the output of the second stage in the cascade and the input of the quantization stage.
In this description, reference will be made to a single-bit converter, though the same considerations apply similarly for multi-bit configurations, as will be appreciated by those skilled in the art. A block diagram of the architecture of a second order sigma-delta converter in the domain of the Z-transform is depicted in
Another embodiment of the block diagram of
Compared to the typical architectures described above, in the disclosed architecture, the capacitors upstream the second integration stage are connected in order to add together and integrate at the same time the signals provided to the second stage. The architecture does not require extra active components (e.g., operational amplifier), thus it is not affected by the drawbacks of the typical architecture of
The feed forward signal may be either directly input to the virtual ground input of the second stage H2, as shown in the figure, or through a switch (not shown) controlled by the control signal 1. The capacitors shown in
In order to have the following Noise Transfer Function (NTF)
NTF=1+T(z)=(1−z−1)2 (2)
it may be necessary that
from which
and thus
The Signal Transfer Function (STF) is
thus it is possible to make the ratio constant between the STF and the NTF by imposing:
This condition is satisfied when the second term has an opposite sign of the first, which in practice is obtained by applying a (−1) gain to the incoming signal. The previous condition is a matching condition between the capacitance ratio input to the first stage and the capacitance ratio input to the second stage.
According to an embodiment, the capacitances C1 and C2 are obtained with a single input capacitor alternatively switched from an input line (in which it plays the role of C1) to a feedback line (in which it plays the role of C2) of the regulator and vice-versa.
In the embodiment of
CA=CB=C1=C;
C11=−C;
C12=−2C;
C3=C.
For correct phasing, the −2C path, the feed forward path with a weight −C, and the switched capacitor C all are connected to the integrator H2 when the control phase 1 is asserted. This forces a stable loop configuration by complying with loop delay when connecting the capacitor C at the input of the first stage.
According to yet another embodiment, the capacitors are dimensioned as follows:
C3=CA=C;
C1=C/4;
C11/CB=− 1/4;
C12/C3=−2.
In this case, the gain ¼ of the first stage may be compensated either by imposing
CB=4C;
C11=−C;
or by using the following values
CB=C;
C11=−C;
and at the same time by imposing that the ADC have a gain GAIN equal to 4. In the latter case, equation (5) becomes
The circuit may achieve the typical resolution and linearity requirements, and due to the reduced number of capacitors, may minimize power consumption.
According to another aspect, the multi-level quantizer of the ADC may be realized using parallel (flash) comparators with equally spaced threshold levels across the signals dynamic range (DR). ADC and DAC capacitors mismatches may be minimized by trimming the value of the capacitors with a bit scrambling Dynamic Element Matching (DEM).
Number | Date | Country | Kind |
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VA2010A0071 | Sep 2010 | IT | national |
Number | Name | Date | Kind |
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7119608 | Doerrer | Oct 2006 | B2 |
7554474 | Le Guillou | Jun 2009 | B2 |
7796071 | Doerrer | Sep 2010 | B2 |
8217815 | Chen et al. | Jul 2012 | B2 |
20070018865 | Chang et al. | Jan 2007 | A1 |
20080062022 | Melanson | Mar 2008 | A1 |
Entry |
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Gharbiya, A. et al; On the Implementation of Input-Feedforward Delta-Sigma Modulators; IEEE Transactions on Circuits and Systems—II: Express Briefs, vol. 53, No. 6, Jun. 2006. |
Lee, K. et al.; Improved Low-Distortion ΔΣADC Topology; IEEE International Symposium on Circuits and Systems, 2009. ISCAS 2009, May 2009. |
San et al., “Second-Order ΔΣAD Modulator with Novel Feedforward Architecture,” IEEE Midwest Symposium on Circuits and System, Aug. 2007, pp. 148-151. |
Picolli et al., “A 1.0 mW, 71 dB SNDR,—1.8dBFS Input Swing, Fourth-Order ΣΔ Interface Circuit for MEMS Microphones”, Sep. 2009, pp. 324-327. |
Number | Date | Country | |
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20140028483 A1 | Jan 2014 | US |
Number | Date | Country | |
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Parent | 13240227 | Sep 2011 | US |
Child | 14038427 | US |