LOW-POWER VOLTAGE REFERENCE

Abstract

A circuit provides a voltage reference using very low power. It can also be used as a shut regulator for a quiescent current as low as 1.5μA. It includes a transconductance amplifier, a gain stage, and a power transistor. One embodiment of this invention utilizes a work function difference between p+ gate and n+ gate to generate a predetermined reference voltage. In another embodiment of this invention, the predetermined reference voltage can be pre-adjusted using gate materials with different work functions.

Description

FIELD OF INVENTION

The invention relates to a voltage reference circuit consuming very low power, and more particularly, relates to a reference voltage generator that can operate under very low current supply and simultaneously keep its output voltage constant over variable temperatures.

BACKGROUND INFORMATION

Nowadays, many electronic devices are built by connecting together electrical components, ranging from a few electrical components in simple circuits to millions of them in complex circuits. Low power consumption has become one of the main issues in the electronics industry for many product areas such as cellular phones, biomedical implants, digital watches, calculators, tape players, portable computers, LCD driver circuits, in short, all types of portable and battery powered electronic devices.

For example, along with the recent increase in the popularity of portable equipment, the requests for large-scale integrated (LSI) devices performing battery operations are increasingly varied. Lowering the operating current (power supply current) to dramatically extend the operating time of battery operated systems is desirable.

Migrating to low operating voltages, denoted commonly as V_cc or V_dd, such as lower than 0.9 V is widely desired. Many traditional reference voltage circuits cannot meet this low voltage reference requirement. In some other reference circuits, such as the bandgap reference voltage generator shown in U.S. Pat. No. 4,628,248 by Birrittella et al, the current needed to activate the reference voltage generator results in high power consumption, due to use of bipolar transistors, e.g., I_B and V_BE. The quiescent current I_Q may reach a very high value, i.e., the value of the current supply that is necessary to operate the shunt regulator may be too big. Typically, the value of the quiescent current used to correctly bias the reference voltage generator is at least several decades, such as 50-60 μA.

The bandgap reference voltage generator has the disadvantage of high power consumption. Thus, developing a type of shunt regulator other than the bandgap reference voltage generator is desired.

SUMMARY

The present invention provides a reference voltage generator (shunt regulator) that is able to generate very low voltage on its output terminal with very low quiescent current, such as 1.5 μA or less. The output reference voltage equal to a bandgap voltage, thus enabling the circuit to consume little power. The magnitude of the quiescent current and reference voltage is only an example and those values can be modified by the designer of the reference voltage generator.

The present invention utilizes the work function difference between gate terminals of an input terminal transistor pair, to generate a predetermined reference voltage, which can be adjustable. The bulk of the reference circuit consists of a transconductance amplifier where its input offset is set to be the same as the magnitude of the reference voltage. This can be done, for example, by using a pair of MOS transistors as the input terminal transistor pair. The gate terminals are made of different types of polysilicon materials. In particular, one of the gate-terminals of the pair of MOS transistors is made of p⁺ polysilicon material, and the other gate-terminal of the pair of MOS transistors is made of n⁺ polysilicon material. Transistors with different kinds of gate materials with the same size (aspect ratio) will have different work function values. The circuit according to the present invention amplifies the work function difference between gate terminals of the input terminal transistor pair. Due to the characteristic of work function, the output reference voltage of the circuit in the present invention can maintain a very stable value.

BRIEF DESCRIPTION OF THE DRAWINGS

The following figures illustrate embodiments of the invention. These figures and embodiments provide examples of the invention and they are non-limiting and non-exhaustive.

FIG. 1 is a schematic view of the block diagram of a reference voltage generator (shunt regulator) in one embodiment of this invention;

FIG. 2 schematically illustrates the circuit diagram according to one embodiment of this invention, in which a reference voltage generator (shunt regulator) utilizes a PMOS input terminal transistor pair (gate terminals respectively made of p⁺ and n⁺ polysilicon materials) as a part of a transconductance amplifier in the reference voltage generator's input stage;

FIG. 3 depicts one of the typical applications of a shunt regulator, in which a compensating capacitor and a load are connected to the shunt regulator, and resistors R1 and R2, which can be internal or external, set the desired voltage;

FIG. 4 schematically illustrates the plot of reference current (I_ref) versus input voltage (V_in) of the reference voltage generator illustrated in FIG. 3; and

FIG. 5 schematically illustrates a circuit diagram according to another embodiment of this invention, in which a reference voltage generator (shunt regulator) utilizes a NMOS input terminal transistor pair (gate terminals respectively made of p⁺ and n⁺ polysilicon materials) as a part of a transconductance amplifier in the reference voltage generator's input stage.

DETAILED DESCRIPTION

Embodiments of a system and method that uses a reference voltage generator as a shunt regulator are described in detail herein. In the following description, some specific details, such as example circuits are included to provide a thorough understanding of embodiments of the invention. One skilled in relevant art will recognize, however, that the invention can be practiced without one or more specific details, or with other methods, components, materials, etc.

The invention discloses the configuration of a circuit of a shunt regulator, which is a very low-power reference voltage generator mainly utilizing MOSFETs. The reference circuit includes a transconductance amplifier, where its input offset is set to be the same as the magnitude of the reference voltage. This is done by using a pair of MOS transistors with their gate terminals formed from different kinds of polysilicon materials. The gate-terminal of one transistor of the pair of MOS transistors is made of p⁺ poly, and the gate terminal of the other transistor of the pair of MOS transistors is made of n⁺ poly. Transistors with the same gate size, but different kinds of gate material, will have different work functions. Accordingly, this invention takes advantage of this configuration to generates a stable reference voltage by amplifying the work function difference to set V_ref.

In FIG. 1, the work function difference (V_WFD) can be expressed as the following equation:

$\begin{array}{cc}{V}_{WFD}=\left(\begin{array}{c}\begin{array}{c}\mathrm{work}\mathrm{function}\\ \mathrm{of}\mathrm{PMOS}\mathrm{with}\end{array}\\ p^{+}\mathrm{poly}\mathrm{gate}\end{array}\right)-\left(\begin{array}{c}\begin{array}{c}\mathrm{work}\mathrm{function}\mathrm{of}\\ \mathrm{of}\mathrm{PMOS}\mathrm{with}\end{array}\\ n^{+}\mathrm{poly}\mathrm{gate}\end{array}\right)& \left(1\right)\end{array}$

FIG. 1 schematically illustrates a circuit diagram of a reference voltage generator 2 according to one embodiment of this invention, in which the work function difference V_WFD is applied across a resistor R1 coupled to the input terminals of a transconductance amplifier. Thus, a first terminal of the resistor R1 is connected to the negative input of the transconductance amplifier and the second terminal of the resistor R1 (along with the positive input of the transconductance amplifier) is connected to ground. In other embodiments, ground can be replaced with a different common voltage level.

The transconductance amplifier is a part of the reference voltage generator 2 with transconductance value Gm. The output voltage of the transconductance amplifier is input to a gain stage Av, and the output voltage of the gain stage Av drives a power transistor Q_p. The power transistor Q_p regulates the shunt current and also sets the final output voltage V_ref. The drain terminal of the power transistor is connected to the negative input terminal of the transconductance amplifier Gm through a resistor R2. Thus, a first terminal of the resistor R2 is connected to the drain terminal of the power transistor Q_p and a second terminal of the resistor R2 is connected to the negative input of the transconductance amplifier.

Accordingly, the desired reference voltage V_ref can be obtained from the following equation:

V _ref =V _WFD[1+(R2/R1)]  (2)

FIG. 2 depicts the detail schematic view of one embodiment of this invention, in which MP1 and MP2 represent the input terminal transistor pair. Particularly, to implement the feature of this invention, in this embodiment, the transistor MP1's gate terminal is made of n⁺ poly, and transistor MP2's gate terminal is made of p⁺ poly. The tail current (I₀) of the input terminal transistor pair is set by the cascode current source (including a transistor MP3 and a transistor MP4). The tail current I₀ is divided to I₁ and I₂, which flow through the transistor MN1 and the transistor MN2, respectively. The transistors MN1 and MN2 have the same size (aspect ratio) and form a simple current mirror (MN1, MN2). Since I₁ and I₂ are forced through a balanced current mirror, the magnitude of I₁ and I₂ should be the same: I₀/2. By examining the circuit, I₀=I₁+I₂, and I₁=I₂=(½)I₀. The action of current mirror MN1 and MN2 balances the currents in the input terminal transistor pair. Furthermore, both transistors MN1 and MN2 operate in the saturation region. The gate-to-source voltage of a transistor in saturation region can be obtained from the following equation:

V _GS =V _T+(I_D/K)^(1/2)  (3)

In equation (3), V_T is the magnitude of threshold voltage, I_D is the drain current, and K is the conduction factor of the device which can be written as K=(½)(W/L) μC_ox, where μ is the mobility of carrier in the device, C_ox is equal to [(gate oxide capacitance)/(unit area)], W is the width of the device, and L is the length of the device. In view of equation (3), the gate-to-source voltage of MP1 and MP2 will be obtained and expressed as following equations:

V _GSMP1 =V _TMP1+[(½)I₀/(K_p)]^(1/2)  (4)

V _GSMP2 =V _TMP2+[(½)I₀/(K_p)]^(1/2)  (5)

By subtracting the gate-to-source voltage of transistor MP1 from transistor MP2, the result named as V_GSMP1−MP2 can be derived from the following equation:

$\begin{array}{cc}\begin{array}{c}\Delta V_{\mathrm{GSMP}1-\mathrm{MP}2}=\left\{V_{\mathrm{TMP}2}+{\left[\left(1/2\right)I_0/\left(K_p\right)\right]}^{\left(1/2\right)}\right\}-\\ \left\{V_{\mathrm{TMP}1}+{\left[\left(1/2\right)I_0/\left(K_p\right)\right]}^{\left(1/2\right)}\right\}\\ =V_{\mathrm{TMP}2}-V_{\mathrm{TMP}1}\end{array}& \left(6\right)\end{array}$

Equation (6) shows that the gate-to-source voltage difference between the input terminal transistor pair is the same as the threshold voltage difference between the transistors MP2 and MP1 if neglecting the secondary effects. In addition, if the foregoing transistors are made of identical transistors with the same gate material, then the resulted voltage from equation (6) would be equal to the difference of threshold voltages or threshold voltage matching, and in normal case will be in the millivolt range, which is called the input offset voltage of the input terminal transistor pair.

However, since the gate material of the transistor MP2 is different from that of the transistor MP1, the gate-to-source voltage difference between MP1 and MP2 is much higher than the millivolt range and will be determined by the work function difference of p⁺ gate terminal (of MP2) and n⁺ gate terminal (of MP1). The equation for the threshold voltage of a regular MOS transistor can be expressed as the following equation:

V _T=Φ_WF+(Q_B/C_ox)−2Φ_B+(Q′_eff/C_ox)  (7)

In equation (7), Φ_WF is the work function difference between gate and silicon material (body), Q_B is total bulk charge, ΦB is the body's potential, Q′_eff is the total charge in oxide-silicon and insulator interface. If only the gate material changes while all other parameters in equation (7) remain unchanged, threshold voltage V_T varies by the amount of work function change of gate material. By definition, work function is the amount of energy needed to move an electron from its Fermi level to its free state level. For a p type material, work function is Φ_p:

Φ_p=4.59+(KT/q)[ln(N_a/n_i)]  (8)

For a n type material, work function is Φ_N:

Φ_N=4.59−(KT/q)[ln(N_d/n_i)]  (9)

So the work function difference between a p and a n type material will be:

Φ_PN=(KT/q)[ln(N_aN_d/n_i²)]  (10)

In equation (10), if both n and p become degenerated materials, i.e., doping density in the semiconductor material becomes very high, then the work function difference between p and n type material, i.e., Φ_PN, becomes the bandgap voltage.

This voltage is fixed over a wide range of temperatures. In the present invention, it is desired to design a voltage reference by taking advantage of this concept, using a MOS transistor with its gate terminal made of p⁺ poly and the other MOS transistor with its gate terminal made of n⁺ poly. As previously described, if the two transistor are forced to have the same current and V_DS voltage (drain-source voltage), then their gate-to-source voltage difference, denoted as ΔV_gs, will be equal to the difference between their threshold voltage ΔV_T which can be expressed in the following equation:

ΔV_T=V_Tp+gate−V_Tn+gate  (11)

From equation (11), if V_Tp+gate and V_Tn+gate are replaced with its expression according to equation (7), then ΔV_T can also be expressed as the following equation:

$\begin{array}{cc}\Delta V_T={\left[\begin{array}{c}\begin{array}{c}{\Phi }_{WF\left(p^{+}\mathrm{Silicon}\right)}+\\ \begin{array}{c}{Q}_B/C_{\mathrm{ox}}-\\ 2{\Phi }_B+\end{array}\end{array}\\ Q_{\mathrm{eff}}^{\prime }/C_{\mathrm{ox}}\end{array}\right]}_{p^{+}\mathrm{gate}}-{\left[\begin{array}{c}\begin{array}{c}{\Phi }_{WF\left(n^{+}\mathrm{Silicon}\right)}+\\ Q_B/C_{\mathrm{ox}}-\end{array}\\ 2{\Phi }_B+\\ Q_{\mathrm{eff}}^{\prime }/C_{\mathrm{ox}}\end{array}\right]}_{n^{+}\mathrm{gate}}& \left(12\right)\end{array}$

Because the parameters are the same for both the p⁺ silicon or n⁺ silicon, equation (12) can be reduced to the following equation:

$\begin{array}{cc}\Delta V_T= {\Phi }_{{\mathrm{WFp}}^{+}\mathrm{Sililicon}}-{\Phi }_{{\mathrm{WFn}}^{+}\mathrm{Silicon}}& \left(13\right)\\ =\left({\Phi }_{{\mathrm{WFp}}^{+}}-{\Phi }_{\mathrm{WFSilicon}}\right)-\left({\Phi }_{{\mathrm{WFn}}^{+}}-{\Phi }_{\mathrm{WFSilicon}}\right)& \left(14\right)\\ ={\Phi }_{{\mathrm{WFp}}^{+}}-{\Phi }_{{\mathrm{WFn}}^{+}}& \left(15\right)\end{array}$

Turning back to equation (13), the parameter Φ_WFp+Silicon is the work function difference between p+ poly and bulk silicon, and the parameter Φ_WFn+Silicon is the work function difference between n+ poly and bulk silicon. Subsequently, from the previous explanation of equation (13) through equation (15), the threshold voltage difference is equal to the work function difference between the p⁺ poly and n⁺ poly, which are respectively used to form the gate terminals of the input terminal transistor pair 20 of the transconductance amplifier.

In FIG. 2, as previously explained, the input terminal transistor pair 20 (including transistors MP1 and MP2) forces the difference of threshold voltages (ΔV_T), which was previously named as V_WFD earlier, across resistor R1. If for any reason, this voltage tends to deviate from its original value, the transconductance amplifier, which consists of transistors MP1, MP2, MP3, MP4, MN1, and MN2, will servo the gate of transistor MN3. In FIG. 2, a transistor MN3 together with transistors MP5 and MP6 (which act as current source for MN3) forms a gain stage (Av in FIG. 1) gaining up the error. This in turn will servo the gate of a power transistor MN4 (Q_p in FIG. 1). This servo action will change the total current from the main supply source in such a way that the generated reference voltage V_ref stays constant, and the constant value of the voltage V_ref can be shown as the following equation:

V _ref=[1+(R2/R1)]V_WFD  (16)

In FIG. 2, transistors MP7 and MP8 together with a resistor R3 set the bias current for the overall circuit. Capacitor C2 bypasses the gates of those transistors, which act as a current mirror. In addition, a resistor R5, together with capacitors C3 and C4, create a pole-zero for the stability of the part. Capacitor C1 and a resistor R4 are used to perform feed forward compensation.

FIG. 3 depicts a typical application of this reference. The gain setting resistors R1 and R2 can be manufactured internally or externally to the integrated circuit of the reference voltage generator 2. The reference voltage generator 2 can be either a two-terminal or a three-terminal device, which depends on whether the resistors R1 and R2 are placed internally or externally.

FIG. 4. shows the current versus voltage behavior of one embodiment of this invention. As the voltage generator 2 starts to regulate current, its impendence is very low. The impedance can be lower than one ohm. The value of the impedance of the shunt regulator depends on the size of the power transistor MN4 (FIG. 2). The circuit can be designed such that the power transistor MN4 is capable of sinking more than hundreds of mA of current while still maintaining very good load regulation.

FIG. 5 shows another embodiment of a low-power reference voltage generator (shunt regulator) 2, in which a transconductance amplifier includes NMOS transistors NM1 and NM2, whose gate terminals are made of p⁺ poly and n⁺ poly materials, respectively. The work function difference between the gate materials is applied across resistor R1, which is referenced to an output voltage. In addition, the reference voltage is set proportional to the work function difference of the input terminal transistor pair identified as an input offset voltage.

Turning back to FIG. 2, the circuit according to one embodiment of the present invention can be used to generate a reference voltage consuming very low power. The circuit can maintain the generated reference voltage at a very stable value. The circuit according to one embodiment of this invention at least includes the following elements: a resistor set, a transconductance amplifier (an input terminal transistor pair 20 with an accompanied current mirror and a pair of loading transistors), a gain stage (MN3 with another accompanied current mirror), and a power transistor MN4. The resistor set at least includes a first resistor R1 and a second R2.

The input terminal transistor pair applies a work function difference across the first resistor R1. The second end of the first resistor R1, being connected to the first end of the second resistor R2, is electrically coupled to the negative input terminal of the transconductance amplifier, which is the gate terminal of the transistor MP2. According to one embodiment of this invention, the input terminal transistor pair at least includes a transistor MP1 and a transistor MP2, the transistor MP1 has the same size as the transistor MP2. The gate terminals of the transistor MP1 and the transistor MP2 are made of polysilicon materials heavily doped with n type dopant and p type dopant, respectively. In addition, the gate terminals of the transistor MP1 and the transistor MP2 are respectively coupled to both ends of the resistor R1, and the body of the transistor MP1 is electrically coupled to the body of the transistor MP2. The gate terminal of the transistor MP2 is the negative input terminal of the transconductance amplifier. Transistors MP4 and MP3 provide bias current to transistor pair MP1 and MP2 in the transconductance amplifier. The drain terminal of the transistor MP3 is coupled to the source terminal of the transistor MP1 and the source terminal of the transistor MP2, the source terminal of the transistor MP3 is coupled to the drain terminal of the transistor MP4, in addition, the body of the transistor MP3 is coupled to the body of the transistor MP4. The transconductance amplifier also includes a pair of loading transistors (including a first loading transistor MN1 and a second loading transistor MN2). The gate terminals of the transistor MN1 and the transistor MN2 are electrically coupled to the drain terminal of the transistor MN1.

According to one embodiment of this invention, the gain stage amplifies the output voltage of the transconductance amplifier. The gain stage comprises a third current source (including transistors MP5 and MP6) and a gain stage transistor MN3. The drain terminal of the transistor MP5 is coupled to the source terminal of the transistor MP6, the body of the transistor MP5 is coupled to the body of the transistor MP6. In addition, the gate terminal of the transistor MN3 is coupled to the drain terminal of the transistor MN2 and to the drain terminal of the transistor MP2, furthermore, the drain terminal of the transistor MN3 is coupled to the drain terminal of the transistor MP6. According to one embodiment of this invention, the reference voltage generator also includes a power transistor, MN4, which is used to send feedback from the drain terminal of the power transistor MN4 to the negative input terminal of the transconductance amplifier through the second resistor R2 connected in shunt with a compensating circuit. The compensating circuit (including a compensating capacitor C1 cascaded with a compensating resistor R4) is used to perform feed forward compensation. The gate terminal of the power transistor MN4 is electrically coupled to the drain terminal of the transistor MN3. Its drain terminal is connected to the second end of the second resistor. The source terminals of the transistors MN1, MN2, MN3, and the power transistor MN4 are all coupled to the first end of the first resistor R1 and R3.

The description of the invention and its applications as set forth herein is illustrative and is not intended to limit the scope of the invention. Variations and modifications of the embodiments disclosed herein are possible, and practical alternatives to and equivalents of the various elements of the embodiments are known to those of ordinary skill in the art. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims

1. A high voltage integrated circuit (HVIC) comprising: means for driving a gate of a high voltage transistor;means for controlling the gate driving means;means for shifting up a signal voltage when the signal is transmitted from the control means to the gate driving means; andmeans for shifting down a signal voltage when the signal is transmitted from the gate driving means to the control means, wherein: the gate driving means is substantially enclosed by a high voltage junction terminating (HVJT) loop structure, the HVJT loop structure configured as a single loop geometry;the shifting up means is located outside and mutually exclusive with the HVJT loop and other HVJT loops of neighboring gate driving means;the shifting down means is located inside and mutually exclusive with the HVJT loop structure and outside other HVJT loops of the neighboring gate driving means;the shifting up means is performed by an N-channel FET and the shifting down means is performed by a P-channel FET;the N-channel FET is formed on a first region of an n-type semiconductor material;the first region of the n-type semiconductor material is formed on a semiconductor substrate of a p-type semiconductor material;a signal interconnect line transmits the shifted-up signal from a drain of the N-channel FET to within the HVJT loop and over a second region of the n-type semiconductor material, the second region of the n-type semiconductor material is directly covered by an insulating layer;the first region of the n-type semiconductor material is separated from the second region of the n-type semiconductor material by a gap of the p-type semiconductor material with a predetermined distance;the P-channel FET is formed on a third region of the n-type semiconductor material;the third region of the n-type semiconductor material is formed on the semiconductor substrate of the p-type semiconductor material;a signal interconnect line transfers the shifted-down signal from a drain of the P-channel FET to the LSU;the third region of the n-type semiconductor material does not extend beyond the drain of the P-channel FET; andno region of n-type semiconductor material exits under the signal interconnect line area from the drain of the P-channel FET to the LSU.

2. A high voltage integrated circuit (HVIC) comprising: at least one high-side gate drive (HSGD) unit for driving a gate of a high voltage transistor;a control unit (CU) for controlling the at least one HSGD unit based on I/O signals to the HVIC; anda plurality of level shifter units (LSU), each acting as an interface between the CU and the HSGD for shifting up a signal voltage when the signal is transmitted from the CU to the HSGD, and for shifting down a signal voltage when the signal is transmitted from the HSGD to the CU, wherein: the HSGD is surrounded by a high voltage junction terminating (HVJT) loop structure, the HVJT loop structure configured as a single loop;the shifting up of the signal voltage is performed by a MOS (metal-oxide semiconductor) or a MIS (metal-insulator semiconductor) of a first channel type that is located outside and mutually exclusive with the HVJT loop structure and other HVJT structures of neighboring LSUs; andthe shifting down of the signal voltage is performed by a MOS or a MIS of a second channel type that is located inside and mutually exclusive with the HVJT loop structure.the shifting up of the signal voltage is performed by an N-channel FET and the shifting down of the signal voltage is performed by a P-channel FET;the N-channel FET is formed on a first region of an n-type semiconductor material;the first region of the n-type semiconductor material is formed on a semiconductor substrate of a p-type semiconductor material;a signal interconnect line transmits the shifted-up signal from a drain of the N-channel FET to within the HVJT loop and over a second region of the n-type semiconductor material, the second region of the n-type semiconductor material is directly covered by an insulating layer;the first region of the n-type semiconductor material is separated from the second region of the n-type semiconductor material by a gap of a p-type semiconductor material with a predetermined distance;the P-channel FET is formed on a third region of the n-type semiconductor material;the third region of the n-type semiconductor material is formed on the semiconductor substrate of the P-type semiconductor material;a signal interconnect line transfers the shifted-down signal from a drain of the P-channel FET to the LSU;the third region of the n-type semiconductor material does not extend beyond the drain of the P-channel FET; andno region of n-type semiconductor material exits under the signal interconnect line area from the drain of the P-channel FET to the LSU.

3. The HVIC of claim 2, wherein the HSGD drives the gate of a pull-up part of an insulated gate bipolar transistor (IGBT) half-bridge.

4. The HVIC of claim 2, further comprising at least one Low-side gate drive (LSGD) unit for driving a gate of a pull-down part of the IGBT half-bridge.

5-8. (canceled)

9. A high voltage gate driving apparatus comprising: at least one high voltage gate drive unit for driving a gate of a high voltage transistor;a high voltage junction terminating (HVJT) loop structure surrounding the high voltage gate drive unit, the HVJT loop having single loop geometry;a MOS (metal-oxide semiconductor) or a MIS (metal-insulator semiconductor) FET transistor of a first channel type for shifting up a signal voltage that enters into the HVJT loop, wherein the transistor is located outside and mutually exclusive with the HVJT loop structure and other HVJT loops of the neighboring high voltage gate drive unit, wherein the transistor is formed on a first region of an n-type semiconductor material, the first region of the n-type semiconductor material is formed on a semiconductor substrate of a p-type semiconductor material, a signal interconnect line transfers the shifted up signal from a drain of the shifting up transistor to within the HVJT loop over a second region of the n-type semiconductor material, the second region of the n-type semiconductor material is directly covered by an insulating layer, the first region of the n-type semiconductor material is separated from the second region of the n-type semiconductor material by a gap of a p-type semiconductor material with a predetermined size to create electrical resistance between the two regions; a MOS or MIS FET transistor of a second channel type for shifting down a signal voltage that exits out of the HVJT loop, wherein the transistor is located inside and mutually exclusive with the HVJT loop structure;the transistor is formed on a third region of the n-type semiconductor material;the third region of the n-type semiconductor material is formed on the semiconductor substrate of the p-type semiconductor material;a signal interconnect line transfers the shifted-down signal from a drain of the shifting down transistor to the LSU;the third region of the n-type semiconductor material does not extend beyond the drain of the shifting down transistor; andno region of n-type semiconductor material exits under the signal interconnect line area from the drain of the shifting down transistor to the LSU.

10. The apparatus of claim 9, wherein the high voltage gate drive unit drives a transistor gate of an insulated gate bipolar transistor (IGBT) half-bridge.

11. The apparatus of claim 9, further comprising a low voltage gate drive unit which drives another transistor gate of the IGBT half-bridge.

12. The apparatus of claim 9, wherein the shifting up transistor is an N-channel FET and the shifting down transistor is a P-channel FET.

13. (canceled)

14. (canceled)

15. The apparatus of claim 12, wherein the gap size is about 3-8 μm.

16. (canceled)

17. The apparatus of claim 12, wherein at least in a segment of the HVJT loop the HVJT structure comprises a region of the first conductivity type formed over the semiconductor substrate of the second conductivity type, and wherein the region of the first conductivity type is directly covered by an insulating layer.

18. The apparatus of claim 17, wherein the first conductivity type is N− type and the second conductivity type is P type.

19. A method of driving a gate of a high voltage transistor, the method comprising: electrically isolating a semiconductor area for generating gate driving signals, wherein the area is isolated by a single loop configured high voltage junction terminating (HVJT) structure that surrounds the area;transmitting gate driving control signals into the isolated area from a first voltage level shifter situated outside the isolated area, wherein the first voltage level shifter increases the signal voltage; andtransmitting gate drive control signals out of the isolated area from a second voltage level shifter situated inside the isolated area, wherein the second voltage level shifter decreases the signal voltage, and wherein: the shifting up of the signal voltage is performed by a MOS (metal-oxide semiconductor) or a MIS (metal-insulator semiconductor) of a first channel type that is located outside and mutually exclusive with the HVJT loop structure and other HVJT structures of neighboring voltage level shifters;the shifting down of the signal voltage is performed by a MOS or a MIS of a second channel type that is located inside and mutually exclusive with the HVJT loop structure;the shifting up of the signal voltage is performed by an N-channel FET and the shifting down of the signal voltage is performed by a P-channel FET;the N-channel FET is formed on a first region of an n-type semiconductor material;the first region of the n-type semiconductor material is formed on a semiconductor substrate of a p-type semiconductor material;a signal interconnect line transmits the shifted-up signal from a drain of the N-channel FET to within the HVJT loop and over a second region of an n-type semiconductor material, the second region of the n-type semiconductor material is directly covered by an insulating layer;the first region of the n-type semiconductor material is separated from the second region of the n-type semiconductor material by a gap of a p-type semiconductor material with a predetermined distance;the P-channel FET is formed on a third region of the n-type semiconductor material;the third region of the n-type semiconductor material is formed on the semiconductor substrate of the p-type semiconductor material;a signal interconnect line transfers the shifted-down signal from a drain of the P-channel FET to the LSU;the third region of the n-type semiconductor material does not extend beyond the drain of the P-channel FET; andno region of n-type semiconductor material exits under the signal interconnect line area from the drain of the P-channel FET to the LSU.

20. (canceled)