Low resolution graphics mode support using window descriptors

Information

  • Patent Grant
  • 8199154
  • Patent Number
    8,199,154
  • Date Filed
    Tuesday, July 12, 2011
    12 years ago
  • Date Issued
    Tuesday, June 12, 2012
    12 years ago
Abstract
Herein described is a method and system of displaying low resolution graphics onto a high resolution display. The low resolution graphics may be displayed using one or more displayable maps or surfaces, each of which is defined by way of one or more parameters. The display may comprise a monitor, television set, or set top box, capable of displaying at a particular resolution. In one or more representative embodiments, the various aspects of the invention permit scaling the low resolution graphics onto the high resolution display by way of using the one or more displayable maps or surfaces such that the graphics data is properly displayed on the higher resolution display.
Description
FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable


MICROFICHE/COPYRIGHT REFERENCE

Not Applicable


BACKGROUND OF THE INVENTION

When a standard definition (SD) television or monitor displays graphics, it may typically display the graphics at a resolution of 640×480 (horizontal×vertical) pixels. In certain circumstances, the graphics may be designed for displaying using a low resolution television or monitor. However, when the television or monitor has a higher resolution compared to the graphics to be displayed, the graphics may not be displayed correctly. For example, when the graphics comprises a resolution of 320×240 pixels and the monitor used to display the graphics comprises a resolution of 640×480 pixels, the image viewed while using the monitor may be unacceptable.


The limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.


BRIEF SUMMARY OF THE INVENTION

Various aspects of the invention provide a system and/or method of displaying graphics data onto a display, substantially as shown in and/or described in connection with at least one of the following figures, as set forth more completely in the claims.


These and other advantages, aspects, and novel features of the present invention, as well as details of illustrated embodiments, thereof, will be more fully understood from the following description and drawings.





BRIEF DESCRIPTION OF THE DRAWINGS


FIG. 1 is a system block diagram of the graphics support circuitry using window descriptors (GSCWD), in accordance with an embodiment of the invention.



FIG. 2 is a system block diagram of a graphics engine in accordance with an embodiment of the invention.



FIG. 3 is a spatial representation of a typical N line display area that is specified using a single window descriptor.



FIG. 4 is a spatial representation of N window descriptors used to specify a 2N line pixel display in accordance with an embodiment of the invention.



FIG. 5 is an operational flow diagram describing how low resolution graphics data may be displayed on a high resolution display, in accordance with an embodiment of the invention.





DETAILED DESCRIPTION OF THE INVENTION

Various aspects of the present invention provide at least a system and method for displaying low resolution graphics data onto a display. The low resolution graphics data may be displayed using one or more graphics pixel maps or graphics pixel surfaces. Alternatively, each of the one or more graphics pixel maps or graphics pixel surfaces may be referred to as a window. The display may comprise a monitor, television set, or set top box, capable of displaying at a particular resolution, for example. In one or more representative embodiments, the display has a native pixel resolution that is higher than the pixel resolution of the one or more graphics pixel maps. In one or more representative embodiments, the various aspects of the invention permit scaling the one or more graphics pixel maps or graphics pixel surfaces such that it is properly displayed on the higher resolution display.


In a representative embodiment, the graphics pixel maps are designed for displaying at a resolution that is lower compared to the native resolution provided by the display. For example, a particular graphics pixel map or surface may be designed such that its pixel resolution is 320×240 pixels. However, the display may comprise a resolution of 640×480 pixels. The system that processes the 320×240 graphics pixel map such that it is properly displayed using a 640×480 pixel resolution display will be referred to as a “graphics support circuitry using window descriptors” (GSCWD). Vertical and horizontal scaling may be appropriately performed by the GSCWD such that the graphics pixel surface or graphics pixel map is properly scaled and displayed over the entire display.



FIG. 1 is a system block diagram of the graphics support circuitry using window descriptors (GSCWD), in accordance with an embodiment of the invention. The GSCWD comprises a processor 104, a memory 108, a graphics engine 112, and a video engine and display 116. As shown, the data bus acts as a medium for data communication between the components 104, 108, 112, 116 of the GSCWD. The processor 104 may comprise a central processing unit (CPU) used for executing one or more sets of instructions stored in the memory 108. The memory 108 may comprise a random access memory such as a DRAM, for example. The graphics engine 112 functions to process graphics data by processing one or more window descriptors that are stored in the memory 108. The one or more sets of instructions as well as the one or more window descriptors may be stored in the memory 108. Further the graphics engine 112 may perform sorting and blending of one or more graphics surfaces or graphics pixel maps prior to presenting the graphics data onto a video engine and display. The processor 104 executes one or more sets of instructions resident in the memory 108 that allow the graphics engine 112 to fetch one or more parameters of the one or more window descriptors. The graphics engine 112 may convert the graphics data into a common internal format such as YUV444, for example. It may utilize the common internal format to easily sort and blend one or more graphics pixel maps or surfaces together. The graphics engine 112 may provide scaling, anti-flutter filtering, and/or aspect ratio conversion functions. The graphics engine 112 utilizes the one or more parameters to properly process the graphics pixel maps such that it is properly presented to the video engine and display 116. The processing may include horizontal and vertical scaling of the graphics pixel data. Various aspects of the invention utilize the one or more window descriptors for performing the vertical scaling. The horizontal scaling may be performed using the on-chip circuitry of the graphics engine 112. The on-chip circuitry may comprise one or more line buffers. In a representative embodiment, the graphics engine 112 processes a graphics pixel map having a resolution of 320×240 pixels, such that it is properly displayed on a display having a resolution of 640×480 pixels. Because the invention is not so limited, the various aspects of the invention may be adapted for processing a graphics pixel map of a first resolution, such that the graphics pixel map is properly displayed on a display having second resolution. The second resolution may be greater than that of the first resolution, for example.


Processing of the graphics data may be accomplished using “window descriptors” that completely describe how the one or more graphics surfaces or graphics pixels maps or windows are presented on a display. A window descriptor comprises one or more parameters used to construct, compose, and/or describe (hence the term “descriptor” in “window descriptor”) each of the one or more graphics surfaces (hence the term “windows” in “window descriptor”). A parameter of a window descriptor may indicate the location of a pixel within a particular display, for example. A parameter of a window descriptor may indicate a starting location or an ending location of a pixel, for example. A parameter of a window descriptor may indicate the layer number of a particular surface when one or more surfaces are used to formulate the video image to be displayed, for example. A parameter may specify one or more weighting factors that are used when one or more surfaces are blended together. More importantly, a parameter may determine the memory spacing between consecutive horizontal scan lines of a displayed graphics pixel map. The memory spacing between horizontal scan lines may be defined as “pitch”. The pitch may be defined as the memory address difference between the first pixel of one horizontal scan line and the first pixel of the next horizontal scan line of a graphics pixel map or surface.



FIG. 2 is a system block diagram of a graphics engine 200 in accordance with an embodiment of the invention. The graphics engine 200 may comprise a window descriptor controller 208, a first in/first out buffer (FIFO) 212, a graphics processor and converter 216, a graphics layer sorter 220, and a graphics blender 224. As shown, the graphics engine 200 interfaces with other components (memory and processor) of the GSCWD by way of a data bus, The window descriptor controller 208 appropriately receives instructions from the processor of the GSCWD. The window descriptor controller 208 may fetch one or more parameters of a window descriptor by accessing the memory of the GSCWD. The one or more parameters of a window descriptor may be used to specify or map a displayable area on a monitor or display. Graphics data (i.e. a graphics pixel map or surface) that is associated with the window descriptor may be displayed in the specified displayable area. The window descriptor controller 208 performs all graphics display controlling functions. The window descriptor controller 208 may load the one or more parameters into storage registers within the graphics engine 200. The window descriptor controller 208 may parse and sort the one or more parameters prior to transmitting them to the FIFO 212. The FIFO 212 is used for properly buffer the data prior to transmission to the graphics processor and converter 216. The graphics processor and converter 216 performs horizontal scaling and aspect ratio conversion, for example. The graphics layer sorter 220 may properly position or layer one or more graphics pixel maps or surfaces such that one or more graphics pixel maps may overlap each other. The graphics blender 224 may blend the one or more graphics pixel maps or surfaces by weighting each surface using a weight or coefficient, and may subsequently add the weighted surfaces together to create a composite surface. The graphics blender 224 outputs the blended surfaces into a video engine and display. The video engine and display may further blend the output with a background and may incorporate video data prior to displaying onto the display. As illustrated in FIG. 2, the graphics engine 200 communicates to a processor and a memory using the data bus 204. The data bus may comprise a 128 bit data bus that utilizes four 32 bit words.



FIG. 3 is a spatial representation of a typical N line display area or display field that is specified using a single window descriptor. The value of N may correspond to 240, for example, when a television displays a resolution of 320×240 pixels. A single window descriptor may be used to specify the display of all horizontal scan lines during a display period. A window descriptor stores one or more parameters (i.e., one set of parameters) used to effectuate the proper display of a window onto the display during the display period. The one or more parameters may comprise what is referred to as a “pitch”. The value represented by the pitch is equal to the difference in memory addresses between the first pixels of consecutive horizontal scan lines. For example, the pitch may be computed by taking the difference between the address of the first pixel in a horizontal scan line and the memory address of the first pixel in the next consecutive horizontal scan line for a particular display period. The pitch may be represented by a data word that is represented using one or more bits. The pitch may Itself be stored in memory and may be retrieved by way of one or more instructions executed by a processor. The one or more parameters may comprise memory start and end addresses of a window descriptor. A memory start or end address may refer to a pixel in a horizontal display line, for example. The memory start address may signify the beginning of a horizontal display line while the memory end address may signify the end of a horizontal display line. The one or more parameters may comprise a layer number of a window, when two or more windows (using one or more window descriptors) are overlapped or superimposed to create a displayed image. Additionally, the one or more parameters may comprise values that are used as weighting factors for determining the transparency or opaqueness for each window when two or more windows are overlapped to form a displayed image.



FIG. 4 is a spatial representation of N window descriptors used to specify a 2N line pixel display in accordance with an embodiment of the invention. As illustrated in FIG. 4, the single window descriptor represented in FIG. 3 is represented using N window descriptors. Each horizontal display line of the window in FIG. 3 is used to represent two horizontal lines by way of specifying a parameter of each of the N window descriptors. The parameter may be referred to as the pitch. The pitch may be set to a value such that the same line is displayed twice for each of the N window descriptors. The value of the pitch may be set to zero, for example. Effectively, this line doubling technique doubles the number of horizontal lines displayed. When N=240 for example, each of the 240 lines are repeated such that a total of 480 lines are displayed, resulting in a doubling of the number of horizontal scan lines. As a result, a 2× vertical scaling is performed. Hence, when displaying a field comprising 240 horizontal display lines, a single window descriptor (i.e., one graphics pixel map or surface) may be used. However, when displaying a field comprising 480 horizontal display lines, the various aspects of the invention employ the use of N=240 window descriptors (i.e., in this representative embodiment, 240 graphics pixel maps or surfaces are used). Each of the 240 window descriptors represents a successive horizontal display line of the previously mentioned 240-line single window descriptor.



FIG. 5 is an operational flow diagram describing how low resolution graphics data may be displayed on a high resolution display, in accordance with an embodiment of the invention. In a representative embodiment, a 320×240 graphics pixel map is vertically and horizontally scaled up in order to display 640×480 pixels on a display having a native resolution of 640×480 pixels. At step 504, the number of window descriptors, N, is determined by the GSCWD such that an appropriate vertical scaling of the 320×240 graphics pixel map may occur. In a representative embodiment, the graphics pixel map may be vertically scaled upwards such that it is properly displayed on a display having 640×480 pixels of resolution. In this representative embodiment, the vertical scaling or line doubling technique is accomplished using N=240 window descriptors (i.e., 240 graphics pixel maps or surfaces). At step 508, the GSCWD determines the values of one or more parameters associated with each of the one or more window descriptors. For example, the one or more parameters are configured such that each window descriptor has its pitch parameter set to zero. Because the pitch is set to zero, each horizontal line is read twice such that the number of horizontal scan lines are doubled, effectively doubling the vertical resolution. In this representative embodiment, the number of lines displayed is doubled from 240 to 480. At step 512, the one or more parameters are stored into a memory (such as that indicated by element 108 in FIG. 1). Next, at step 516, the one or more parameters, for each of the exemplary 240 window descriptors, are read and processed by the graphics engine (as described in relation to FIG. 1) using the processor (as described in relation to FIG. 1) and memory. At step 520, horizontal scaling is accomplished using the graphics engine by way of its internal graphics processor and converter (as described in relation to FIG. 2). Additionally, vertical scaling is accomplished by way of the line doubling technique as previously described. Thereafter, at step 524, the processed graphics pixel maps are transmitted to the video engine and display such that the maps or surfaces may be further combined with background color and video data.


While the invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the Invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims
  • 1. A method comprising: generating one or more window descriptors for representing a graphics pixel map, the one or more window descriptors including a parameter that determines a memory spacing between scan lines of the graphics pixel map; andprocessing said one or more window descriptors to generate a processed output that conforms to a native resolution of a display.
  • 2. The method of claim 1 wherein said one or more window descriptors is received from a memory through a data bus.
  • 3. The method of claim 1 wherein said graphics pixel map defines a surface having said resolution that is lower than that of said native resolution of said display.
  • 4. The method of claim 1 wherein said processing comprises vertical scaling.
  • 5. The method of claim 1 wherein said resolution of said graphics pixel map is equal to 320×240 pixels and said native resolution of said display is equal to 640×480 pixels, and said one or more window descriptors comprises a total of 240 window descriptors.
  • 6. The method of claim 5 wherein the parameter corresponds to a pitch, said pitch equal to a difference in memory addresses between the first pixels of two consecutive horizontal scan lines.
  • 7. The method of claim 6 wherein said pitch is set to value equal to zero such that a line doubling mechanism is implemented resulting in 2× vertical scaling with half the vertical resolution.
  • 8. The method of claim 5 wherein each of said 240 window descriptors defines two consecutive horizontal scan lines of said 640×480 native resolution display.
  • 9. The method of claim 5 wherein a window descriptor of said one or more window descriptors comprises a layer number of a window.
  • 10. A system comprising: a circuitry for performing horizontal and vertical scaling of pixel data;a data bus;a memory; anda processor used to execute one or more instructions stored in said memory, said memory storing one or more window descriptors used by said circuitry for displaying a graphics surface having a first resolution onto a display having a second resolution, the one or more window descriptors including a parameter that determines a memory spacing between scan lines of the graphics surface, wherein said circuitry, said memory, and said processor are communicatively coupled by way of said data bus.
  • 11. The system of claim 10 wherein said second resolution is higher than that of said first resolution.
  • 12. The system of claim 10 wherein said first resolution comprises 320×240 pixels while said second resolution comprises 640×480 pixels.
  • 13. The system of claim 10 wherein said circuitry comprises: a controller used for fetching one or more window descriptors from said memory; anda graphics processor and converter used for scaling said graphics pixel map.
  • 14. The system of claim 13 wherein said vertical scaling scales said graphics pixel map from 240 horizontal lines to 480 horizontal lines.
  • 15. The system of claim 10 wherein said one or more window descriptors comprises a parameter that indicates a layer number of a particular surface of one or more surfaces, said particular surface used to formulate a video image to be displayed on said display.
  • 16. The system of claim 15 wherein said one or more window descriptors comprises a parameter that specifies a weighting factor of said particular surface.
  • 17. The system of claim 10 wherein the parameter that specifies a difference between the first pixel of a first horizontal scan line and a first pixel of a second horizontal scan line of said graphics surface.
  • 18. A system comprising: means for generating one or more window descriptors for representing a graphics pixel map, the one or more window descriptors including a parameter that determines a memory spacing between scan lines of the graphics pixel map; andmeans for processing said one or more window descriptors to generate a processed output that conforms to a native resolution of said display.
  • 19. The system of claim 18 wherein said one or more window descriptors is received from a memory through a data bus.
  • 20. The system of claim 18 wherein said graphics pixel map defines a surface having said resolution that is lower than that of said native resolution of said display.
  • 21. The system of claim 18 wherein said processing comprises vertical scaling.
  • 22. The system of claim 18 wherein said resolution of said graphics pixel map is equal to 320×240 pixels and said native resolution of said display is equal to 640×480 pixels, and said one or more window descriptors comprises a total of 240 window descriptors.
  • 23. The system of claim 18 wherein the parameter corresponds to a pitch, said pitch equal to a difference in memory addresses between the first pixels of two consecutive horizontal scan lines.
  • 24. The system of claim 12 wherein said pitch is set to value equal to zero such that a line doubling mechanism is implemented resulting in 2× vertical scaling with half the vertical resolution.
  • 25. The system of claim 22 wherein each of said 240 window descriptors defines two consecutive horizontal scan lines of said 640×480 native resolution display.
  • 26. The system of claim 18 wherein a window descriptor of said one or more window descriptors comprises a layer number of a window.
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

The present application is a continuation of U.S. application Ser. No. 11/072,201, filed on Mar. 4, 2005, now U.S. Pat. No. 7,982,740, which is a continuation-in-part of U.S. application Ser. No. 10/712,809, filed Nov. 13, 2003, now U.S. Pat. No. 7,002,602, which itself is a continuation of U.S. application Ser. No. 09/437,348, filed on Nov. 9, 1999, now U.S. Pat. No. 6,700,588. U.S. application Ser. No. 09/437,348 makes reference to and claims priority to U.S. Provisional Patent Application Ser. No. 60/107,875 filed on Nov. 9, 1998.

US Referenced Citations (293)
Number Name Date Kind
4020332 Crochiere et al. Apr 1977 A
4367466 Takeda et al. Jan 1983 A
4412294 Watts et al. Oct 1983 A
4481594 Staggs et al. Nov 1984 A
4532547 Bennett Jul 1985 A
4679040 Yan Jul 1987 A
4688033 Carini et al. Aug 1987 A
4727365 Bunker et al. Feb 1988 A
4751446 Pineda et al. Jun 1988 A
4799053 Van Aken et al. Jan 1989 A
4908780 Priem et al. Mar 1990 A
4959718 Bennett Sep 1990 A
5003299 Batson et al. Mar 1991 A
5039983 Yoon Aug 1991 A
5043714 Perlman Aug 1991 A
5065231 Greaves et al. Nov 1991 A
5097257 Clough et al. Mar 1992 A
5142273 Wobermin Aug 1992 A
5146592 Pfeiffer et al. Sep 1992 A
5148417 Wong et al. Sep 1992 A
5155816 Kohn Oct 1992 A
5200738 Fumoto et al. Apr 1993 A
5243447 Bodenkamp et al. Sep 1993 A
5250928 Kuriki Oct 1993 A
5254981 Disanto et al. Oct 1993 A
5258747 Oda et al. Nov 1993 A
5262854 Ng Nov 1993 A
5287178 Acampora et al. Feb 1994 A
5301332 Dukes Apr 1994 A
5307177 Shibata et al. Apr 1994 A
5319742 Edgar Jun 1994 A
5327125 Iwase et al. Jul 1994 A
5335074 Stec Aug 1994 A
5371547 Siracusa et al. Dec 1994 A
5371877 Drako et al. Dec 1994 A
5384912 Ogrinc et al. Jan 1995 A
5396567 Jass Mar 1995 A
5398211 Willenz et al. Mar 1995 A
5402181 Jenison Mar 1995 A
5418535 Masucci et al. May 1995 A
5422858 Mizukami et al. Jun 1995 A
5430465 Sabella et al. Jul 1995 A
5432769 Honjo Jul 1995 A
5432900 Rhodes et al. Jul 1995 A
5434683 Sekine et al. Jul 1995 A
5434957 Moller Jul 1995 A
5467144 Saeger et al. Nov 1995 A
5469223 Kimura Nov 1995 A
5471411 Adams et al. Nov 1995 A
5475400 Sellers et al. Dec 1995 A
5479606 Gray Dec 1995 A
5488385 Singhal et al. Jan 1996 A
5515077 Tateyama May 1996 A
5526054 Greenfield et al. Jun 1996 A
5532749 Hong Jul 1996 A
5533182 Bates et al. Jul 1996 A
5539891 Childers et al. Jul 1996 A
5546103 Rhodes et al. Aug 1996 A
5550594 Cooper et al. Aug 1996 A
5570296 Heyl et al. Oct 1996 A
5574572 Malinowski et al. Nov 1996 A
5577187 Mariani Nov 1996 A
5583575 Arita et al. Dec 1996 A
5592601 Kelley et al. Jan 1997 A
5598525 Nally et al. Jan 1997 A
5598545 Childers et al. Jan 1997 A
5600364 Hendricks et al. Feb 1997 A
5600379 Wagner Feb 1997 A
5604514 Hancock Feb 1997 A
5610983 Stewart Mar 1997 A
5614952 Boyce et al. Mar 1997 A
5615376 Ranganathan Mar 1997 A
5619270 Demmer Apr 1997 A
5619337 Naimpally Apr 1997 A
5621478 Demmer Apr 1997 A
5621869 Drews Apr 1997 A
5621906 O'Neill et al. Apr 1997 A
5623311 Phillips et al. Apr 1997 A
5625611 Yokota et al. Apr 1997 A
5625764 Tsujimoto et al. Apr 1997 A
5635985 Boyce et al. Jun 1997 A
5638499 O'Connor et al. Jun 1997 A
5638501 Gough et al. Jun 1997 A
5640543 Farrell et al. Jun 1997 A
5664162 Dye Sep 1997 A
5687306 Blank Nov 1997 A
5694143 Fielder et al. Dec 1997 A
5696527 King et al. Dec 1997 A
5701365 Harrington et al. Dec 1997 A
5706415 Kelley et al. Jan 1998 A
5706482 Matsushima et al. Jan 1998 A
5708457 Otake et al. Jan 1998 A
5708764 Borrel et al. Jan 1998 A
5719593 De Lange Feb 1998 A
5727192 Baldwin Mar 1998 A
5737455 Harrington et al. Apr 1998 A
5742779 Steele et al. Apr 1998 A
5742796 Huxley Apr 1998 A
5745095 Parchem et al. Apr 1998 A
5748178 Drewry May 1998 A
5751979 McCrory May 1998 A
5754186 Tam et al. May 1998 A
5758177 Gulick et al. May 1998 A
5761516 Rostoker et al. Jun 1998 A
5764238 Lum et al. Jun 1998 A
5764243 Baldwin Jun 1998 A
5765010 Chung et al. Jun 1998 A
5774110 Edelson Jun 1998 A
5790134 Lentz Aug 1998 A
5790136 Hoffert et al. Aug 1998 A
5790795 Hough Aug 1998 A
5790842 Charles et al. Aug 1998 A
5793384 Okitsu Aug 1998 A
5793445 Lum et al. Aug 1998 A
5802579 Crary Sep 1998 A
5812210 Arai et al. Sep 1998 A
5815137 Weatherford et al. Sep 1998 A
5818533 Auld et al. Oct 1998 A
5828383 May et al. Oct 1998 A
5831615 Drews et al. Nov 1998 A
5838296 Butler et al. Nov 1998 A
5838389 Mical et al. Nov 1998 A
5844608 Yu et al. Dec 1998 A
5847717 Berry Dec 1998 A
5854761 Patel et al. Dec 1998 A
5864345 Wickstrom et al. Jan 1999 A
5867166 Myhrvold et al. Feb 1999 A
5874967 West et al. Feb 1999 A
5877754 Keith et al. Mar 1999 A
5877817 Moon Mar 1999 A
5883670 Sporer et al. Mar 1999 A
5889949 Charles Mar 1999 A
5894300 Takizawa Apr 1999 A
5894526 Watanabe et al. Apr 1999 A
5896136 Augustine et al. Apr 1999 A
5903261 Walsh et al. May 1999 A
5903281 Chen et al. May 1999 A
5907295 Lin May 1999 A
5907635 Numata May 1999 A
5909559 So Jun 1999 A
5914725 MacInnis et al. Jun 1999 A
5914728 Yamagishi et al. Jun 1999 A
5920572 Washington et al. Jul 1999 A
5920842 Cooper et al. Jul 1999 A
5923316 Kitamura et al. Jul 1999 A
5923385 Mills et al. Jul 1999 A
5926647 Adams et al. Jul 1999 A
5929872 Greene Jul 1999 A
5940080 Ruehle et al. Aug 1999 A
5940089 Dilliplane et al. Aug 1999 A
5948082 Ichikawa Sep 1999 A
5949432 Gough et al. Sep 1999 A
5949439 Ben-Yoseph et al. Sep 1999 A
5951664 Lambrecht et al. Sep 1999 A
5953691 Mills Sep 1999 A
5956041 Koyamada et al. Sep 1999 A
5959626 Garrison et al. Sep 1999 A
5959637 Mills et al. Sep 1999 A
5961603 Kunkel et al. Oct 1999 A
5963201 McGreggor et al. Oct 1999 A
5963222 Cheney et al. Oct 1999 A
5963262 Ke et al. Oct 1999 A
5973955 Nogle et al. Oct 1999 A
5977933 Wicher et al. Nov 1999 A
5977989 Lee et al. Nov 1999 A
5982305 Taylor Nov 1999 A
5982425 Allen et al. Nov 1999 A
5982459 Fandrianto et al. Nov 1999 A
5987555 Alzien et al. Nov 1999 A
6002411 Dye Dec 1999 A
6006286 Baker et al. Dec 1999 A
6006303 Barnaby et al. Dec 1999 A
6018803 Kardach Jan 2000 A
6023302 MacInnis et al. Feb 2000 A
6028583 Hamburg Feb 2000 A
6038031 Murphy Mar 2000 A
6046740 LaRoche et al. Apr 2000 A
6057850 Kuchury May 2000 A
6061094 Maietta May 2000 A
6061402 Boyce et al. May 2000 A
6064676 Slattery et al. May 2000 A
6067071 Kotha et al. May 2000 A
6067322 Wang May 2000 A
6077084 Mino et al. Jun 2000 A
6078305 Mizutani Jun 2000 A
6081297 Lee Jun 2000 A
6085273 Ball et al. Jul 2000 A
6088045 Lumelsky et al. Jul 2000 A
6088355 Mills et al. Jul 2000 A
6094226 Ke et al. Jul 2000 A
6098046 Cooper et al. Aug 2000 A
6100826 Jeon et al. Aug 2000 A
6100899 Ameline et al. Aug 2000 A
6105048 He Aug 2000 A
6108014 Dye Aug 2000 A
6111896 Slattery et al. Aug 2000 A
6115422 Anderson et al. Sep 2000 A
6121978 Miler Sep 2000 A
6124878 Adams et al. Sep 2000 A
6130660 Imsand Oct 2000 A
6133901 Law Oct 2000 A
6134378 Abe et al. Oct 2000 A
6144392 Rogers Nov 2000 A
6151030 DeLeeuw et al. Nov 2000 A
6151074 Werner Nov 2000 A
6157415 Glen Dec 2000 A
6157978 Ng et al. Dec 2000 A
6160989 Hendricks et al. Dec 2000 A
6169843 Lenihan et al. Jan 2001 B1
6178486 Gill et al. Jan 2001 B1
6184908 Chan et al. Feb 2001 B1
6189064 MacInnis et al. Feb 2001 B1
6189073 Pawlowski Feb 2001 B1
6199131 Melo et al. Mar 2001 B1
6204859 Jouppi et al. Mar 2001 B1
6205260 Crinon et al. Mar 2001 B1
6208354 Porter Mar 2001 B1
6208671 Paulos et al. Mar 2001 B1
6208691 Balakrishnan et al. Mar 2001 B1
6212590 Melo et al. Apr 2001 B1
6215703 Bogin et al. Apr 2001 B1
6226794 Anderson, Jr. et al. May 2001 B1
6229550 Gloudemans et al. May 2001 B1
6233634 Clark et al. May 2001 B1
6236727 Ciacelli et al. May 2001 B1
6239810 Van Hook et al. May 2001 B1
6252608 Snyder et al. Jun 2001 B1
6256348 Laczko et al. Jul 2001 B1
6263019 Ryan Jul 2001 B1
6263023 Ngai Jul 2001 B1
6263396 Cottle et al. Jul 2001 B1
6269107 Jong Jul 2001 B1
6271847 Shum et al. Aug 2001 B1
6275507 Anderson et al. Aug 2001 B1
6281873 Oakley Aug 2001 B1
6286103 Maillard et al. Sep 2001 B1
6301299 Sita et al. Oct 2001 B1
6311204 Mills Oct 2001 B1
6313822 McKay et al. Nov 2001 B1
6320619 Jiang Nov 2001 B1
6326963 Meehan Dec 2001 B1
6326984 Chow et al. Dec 2001 B1
6327000 Auld et al. Dec 2001 B1
6327002 Rinaldi et al. Dec 2001 B1
6327005 Han Dec 2001 B1
6335746 Enokida et al. Jan 2002 B1
6337703 Konar et al. Jan 2002 B1
6339434 West et al. Jan 2002 B1
6351471 Robinett et al. Feb 2002 B1
6351474 Robinett et al. Feb 2002 B1
6353460 Sokawa et al. Mar 2002 B1
6357045 Devaney Mar 2002 B1
6362827 Ohba Mar 2002 B1
6369826 Shimotono et al. Apr 2002 B1
6369855 Chauvel et al. Apr 2002 B1
6373497 McKnight et al. Apr 2002 B1
6374244 Shibata Apr 2002 B1
6380945 MacInnis et al. Apr 2002 B1
6384831 Nakamura et al. May 2002 B1
6384840 Frank et al. May 2002 B1
6393021 Chow et al. May 2002 B1
6408436 de Haas Jun 2002 B1
6411333 Auld et al. Jun 2002 B1
6421460 Hamburg Jul 2002 B1
6426755 Deering Jul 2002 B1
6434319 Wine Aug 2002 B1
6442201 Choi Aug 2002 B2
6456335 Miura et al. Sep 2002 B1
6459456 Oh Oct 2002 B1
6466206 Deering Oct 2002 B1
6466210 Carlsen et al. Oct 2002 B1
6466220 Cesana et al. Oct 2002 B1
6466581 Yee et al. Oct 2002 B1
6466624 Fogg Oct 2002 B1
6467093 Inoue et al. Oct 2002 B1
6470100 Horiuchi Oct 2002 B2
6496186 Deering Dec 2002 B1
6496228 McGee et al. Dec 2002 B1
6510554 Gordon et al. Jan 2003 B1
6529284 Ganapathy et al. Mar 2003 B1
6570579 MacInnis et al. May 2003 B1
6570922 Wang et al. May 2003 B1
6662329 Foster et al. Dec 2003 B1
6670964 Ward et al. Dec 2003 B1
6687302 Nakaya Feb 2004 B2
6700588 MacInnis et al. Mar 2004 B1
6720976 Shimizu et al. Apr 2004 B1
6853385 MacInnis et al. Feb 2005 B1
6894706 Ward et al. May 2005 B1
7002602 MacInnis et al. Feb 2006 B2
7071939 Suen et al. Jul 2006 B2
7982740 Tang et al. Jul 2011 B2
20020176506 Florencio et al. Nov 2002 A1
Foreign Referenced Citations (9)
Number Date Country
0746116 Dec 1996 EP
0752695 Jan 1997 EP
0840276 May 1998 EP
0840277 May 1998 EP
0840505 May 1998 EP
2287627 Sep 1995 GB
2000196586 Jul 2000 JP
9410641 May 1994 WO
0028518 May 2000 WO
Related Publications (1)
Number Date Country
20110273476 A1 Nov 2011 US
Provisional Applications (1)
Number Date Country
60107875 Nov 1998 US
Continuations (2)
Number Date Country
Parent 11072201 Mar 2005 US
Child 13181258 US
Parent 09437348 Nov 1999 US
Child 10712809 US
Continuation in Parts (1)
Number Date Country
Parent 10712809 Nov 2003 US
Child 11072201 US