Low spur phase-locked loop architecture

Abstract

A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below −80 dBc.

Description

FIELD OF THE INVENTION

The present invention relates generally to phase-locked loops. More particularly, the invention is directed to a low spur PLL using differential architecture.

SUMMARY AND DETAILED DESCRIPTION

Details of various embodiments of the present invention are disclosed in the following appendix:

APPENDIX A

A 10-Page Document by the Inventors

As one of ordinary skill in the art will appreciate, various changes, substitutions, and alterations could be made or otherwise implemented without departing from the principles of the present invention. Accordingly, the examples and drawings disclosed herein including the appendix are for purposes of illustrating the preferred embodiments of the present invention and are not to be construed as limiting the invention.

Claims

1. A phase-locked loop, comprising: (a) a phase detector;(b) a charge pump;(c) a loop filter;(d) a voltage-controlled oscillator (VCO); and(e) a differential Kvco gain linearization circuit, wherein said differential Kvco gain linearization circuit includes an adjustable DC offset.

2. The phase-locked loop as set forth in claim 1, wherein a free-running oscillation frequency of said VCO is centered near a desired frequency using a programmable load to minimize a required control voltage range.