Patent Application
20080061837
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.
Systems and methods for low supply voltage, large output swing, source-terminated output driver for high speed ac-coupled double-termination serial links are disclosed. The following description is presented to enable any person skilled in the art to make and use the invention. Descriptions of specific embodiments and applications are provided only as examples and various modifications will be readily apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is to be accorded the widest scope encompassing numerous alternatives, modifications and equivalents consistent with the principles and features disclosed herein. For purpose of clarity, details relating to technical material that is known in the technical fields related to the invention have not been described in detail so as not to unnecessarily obscure the present invention.
Particular circuit layouts and circuit components may be given for illustrative purposes. This is done for illustrative purposes to facilitate understanding only and one of ordinary skill in the art may vary the design and implementation parameters and still remain within the scope of the invention.
Generally this description relates to the design and manufacture of integrated semiconductor circuits. In particular, circuits that provide low supply voltage, large output swing, source-terminated output drivers for high speed ac-coupled double-termination serial links are discussed. The systems and methods described herein can be applied to any high speed current mode logic (CML) design to allow decreased supply voltage while maintaining large output swing. Typical applications include, but are not limited to, PCI Express, Fibre Channel, HDMI/DVI, DisplayPort, Serial ATA, SONET, Rapid IO, and XAUI. The systems and methods can be used in AC-coupled double-termination serial links.
In one example, the circuits and methods boost the common mode supply voltage while maintaining the same source termination impedance values. Active components in the form of additional DC current sources are added to a CML driver circuit to boost the common mode voltage. The additional DC current sources drawn from a power supply provides a DC path for the output driver, and a high impedance of the DC current sources maintain the desired output termination resistor values.
In one example of the invention, a current mode logic circuit includes a current mode logic driver circuit and a transistor biasing improvement circuit. The current mode logic driver circuit includes a first transistor and a second transistor in a differential pair configuration. A first source termination resistor is coupled to a first transistor drain at a first output node and a second source termination resistor is coupled to a second transistor drain at a second output node. The transistor biasing improvement circuit is coupled to the current mode logic circuit and includes a first current source coupled to the first output node and a second current source coupled to the second output node. The first current source and the second current source raise a common mode voltage at the first output node and the second output node.
In one example of the invention, a current mode logic circuit includes a first transistor having a first transistor gate, a first transistor source, and a first transistor drain. A second transistor includes a second transistor gate, a second transistor source, and a second transistor drain. A first data input terminal is coupled to the first transistor gate and a second data input terminal is coupled to the second transistor gate. A first source termination resistor having a first terminal is coupled to the first transistor drain and a second terminal coupled to a supply voltage. A second source termination resistor having a third terminal is coupled to the second transistor drain and a fourth terminal coupled to the supply voltage. The circuit further includes a first output node coupled to the first transistor drain and a second output node coupled to the second transistor drain. A first current source is coupled to the first output node and is operable to raise a first common mode voltage at the first output node. A second current source is coupled to the second output node and is operable to raise a second common mode voltage at the second output node.
Referring to
The CML driver circuit 100 utilizes NMOS transistors M1110 and M2112 as a differential logic pair. The gate electrode of NMOS transistor M1110 is connected to an input line DIP 114, the source electrode is connected to constant-current source Isink 138, and the drain electrode is connected to an output node 117 connected to chip pad DON 120 and source termination resistor R1104. The gate electrode of NMOS transistor M2112 is connected to input line DIN 116, the source electrode is connected to constant current source Isink 138, and the drain electrode is connected to an output node 119 connected to chip pad DOP 118 and source termination resistor R2106. A supply voltage VDD 108 is coupled to R1104 and R2106.
A current source Idc1 142 is coupled to output node 117. A current source Idc2 144 is coupled to output node 119. Current source Idc1 142 and current source Idc2 144 may be driven by a supply voltage VDDx 140. Current source Idc1 142 and current source Idc2 operate to improve biasing of NMOS transistor M1110 and M2112 for a given values of supply voltage VDD 108, resistor R1104, and resistor R2106 by raising the common mode voltage at node 117 and node 119. Current sources Idc1 142 and Idc2 144 act to increase the drain voltages of transistors M1110 and M2112 higher than in the prior art CML driver circuit shown in
The operation of the CML driver circuit 100 will next be explained with reference to
Capacitor C1122 and capacitor C2124 operate to decouple the DC voltages of VDD 108 and Vterm 130. This decoupling allows different voltages at the source and end terminals being applied, which is an important feature for advanced semiconductor technology since the devices manufactured by different process technologies from different vendors can inter-operate easily.
In operation, CML driver circuit 100 allows for a low supply voltage, large output swing, source terminated output driver. Idc1 142 and Idc2 144 are sinking currents from VDDx 140 towards M1110 and M2112. Since the AC coupling capacitors block the DC current flowing towards the end termination resistors R3126 and R4128, all Idc1 142 and Idc2 144 currents are forced into M1110 and M2112. In one example, supply voltage VDDx 140 can be equal to supply voltage VDD 108 for a simplified driver power rail design. In a further example, VDDx 140 can be another I/O supply voltage. Typically, VDDx 140 is greater than or equal to VDD 108. In one example, the current sources Idc1 142 and Idc2 144 are also implemented by transistors, requiring a VDDx 140 sufficiently high to allow effective implementation of Idc1 142 and Idc2 144. The current sources Idc1 142 and Idc2 144 should have a very large effective impedance over the operation frequency range of the CML driver to ensure that the desired source termination resistor values are determined solely by R1104 and R2106.
The added current sources Idc1 142 and Idc2 144 increase the common mode voltage seen at driver output pads DOP 118 and DON 120, and to keep the output termination resistances un-altered, where the output termination resistance is the output resistance seen into the output pad. By these two current sources Idc1 142 and Idc2 144, the common mode voltage at output node 119 (output pad DOP 118) and output node 117 (output pad DON 120) is raised by Idc1*Rterm, where Rterm is the single-ended source termination resistor (R1104 or R2106), and Idc1 142 equals to Idc2 144. Thus, the common mode voltage Vcm at output node 117 and output node 119 is as follows:
V
cm
=V
DD
−R1*Isink/2+Idc1*Rterm
Compared to the prior art circuit illustrated in
In one example application, where the supply voltage VDD 108 is equal to 1.2 V, the desired differential output swing is 1200 mV, and the resistors R1104, R2106, R3126, and R4128 are all 50 Ohms, if the current sources Idc1 142 and Idc2 144 are set to 6 mA, the common mode voltage of the driver is raised to 900 mV. The extra 300 mV voltage is allocated to the switch transistors M1110 and M2112, and the current source Isink 138. As such, there will be a 600 mV headroom voltage for NMOS transistors M1110 and M2112 and the current source Isink 138. The biasing condition of transistors M1110 and M2112 is thus improved by a factor of two this example relative to the prior art circuit of
In a further example, the current sources Idc1 142 and Idc2 144 have a value equal to half the value of the current source Isink 138. In this manner, all DC biasing current of the CML driver is through the current sources Idc1 142 and Idc2 144. VDD 108 is now only used to set the common mode voltage of the CML driver. To extend the concept further, VDD 108 can be floating (no connection) by using a common mode feedback circuit to set the DOP 118 and DON 120 DC voltages. The major benefit from such an implementation is associated with processing technology advancement. High speed and high data throughput are always in demand and technology scaling pushes semiconductor speeds higher. Generally, for reliable operation, transistors with reduced feature sizes have to operate under low voltage. The circuit 100 invention solves the contradictive requirements from manufacturing (lower voltage) and signal quality (large swing). For dual gate oxide CMOS process technology, thick oxide transistors can operate under high supply voltage while thin oxide transistors need low supply voltage. Idc1 142 and Idc2 144 can be implemented by thick oxide transistors, which means VDDx 140 can be much higher than VDD 8.
To achieve a high speed operation, the output driving transistors M1110 and M2112 are implemented by thin oxide transistors. The R1104 and R2106 tied to VDD 108 together with the Idc1 142 and Idc2 144 set the common mode voltage. The only basic limitation is that the specific technology reliability requires no over-stressing of the M1110 and M2112 at the drain side. In other words, Idc1 142 and Idc2 144 operate to overcome the lower supply voltage, and M1110 and M2112 are used to achieve high speed operation.
In a further example, Idc1 142 is replaced with a resistor and inductor in series and Idc2 144 is replaced with a resistor and inductor in series. The resistors have a value equal to R1104 and R2106 respectively. At the targeted operation frequency, the two inductors have large impedance values which operate to block the AC current into this AC current choking branch. The equivalent termination resistances are held at the desired values set by R1104 and R2106.
The CML driver circuit 200 utilizes PMOS transistors M1210 and M2212 as a differential logic pair. The gate electrode of PMOS transistor M1210 is connected to an input line DIP 214, the source electrode is connected to constant-current source Isource 238, and the drain electrode is connected to an output node 217 connected to chip pad DON 220 and source termination resistor R1204. The gate electrode of PMOS transistor M2212 is connected to input line DIN 216, the source electrode is connected to constant current source Isource 238, and the drain electrode is connected to an output node 219 connected to chip pad DOP 218 and source termination resistor R2206. A supply voltage VDD 208 is coupled to current source Isource 238. A supply voltage Vss 250 is coupled to R1204 and R2206.
A current source Idc1 242 is coupled to output node 217. A current source Idc2 244 is coupled to output node 219. Current source Idc1 242 and current source Idc2 244 may be driven by a supply voltage Vssx 240. Current source Idc1 242 and current source Idc2 operate to improve biasing of PMOS transistor M1210 and M2212 for a given values of supply voltage VDD 208, resistor R1204, and resistor R2206 by raising the common mode voltage at node 217 and node 219. The added current sources Idc1 242 and Idc2 244 help to increase the transistors M1210 and M2212 drain voltages higher than in the conventional structure. Source termination resistance values are set by R1204 and R2206. The added current sources Idc1 242 and Idc2 244 operate as a transistor biasing improvement circuit coupled to a traditional CML driver circuit to solve the above mentioned headroom issue with the conventional CML driver for low supply voltage and large output swing applications. In one example, current sources Idc1 242 and Idc2 244 are implemented using transistors. Referring to
In one example where the CML driver circuit 200 is used in an AC-coupled double termination data transmission link, CML driver circuit 200 is coupled to components illustrated in
Although example circuit configurations have been described in certain example of the invention, one of ordinary skill in the art will recognize that except as otherwise described herein other configurations and components may be used to perform similar functions. While the exemplary embodiments of the present invention are described and illustrated herein, it will be appreciated that they are merely illustrative and that modifications can be made to these embodiments without departing from the spirit and scope of the invention. Thus, the scope of the invention is intended to be defined only in terms of the following claims as may be amended, with each claim being expressly incorporated into this Description of Specific Embodiments as an embodiment of the invention.
