BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the presented technology of low systematic offset, temperature independent voltage buffering and, together with the description, serve to explain the principles of the technology:
FIG. 1 is a schematic of a differential input single ended output amplifier used as a voltage buffer.
FIG. 2 is a schematic of a low systematic offset, temperature independent voltage buffer, according to an embodiment of the present technology.
FIG. 3 is a flow diagram of a method for buffering a voltage, according to an embodiment of the present technology.
The drawings referred to in this description should not be understood as being drawn to scale unless specifically noted.
DETAILED DESCRIPTION
Reference will now be made in detail to embodiments of the present technology of low systematic offset, temperature independent voltage buffering, examples of which are illustrated in the accompanying drawings. While the present technology will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the described technology to these embodiments. On the contrary, the present technology is intended to cover alternatives, modifications, and equivalent, which may be included within the spirit and scope of the technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. However, it will be recognized by one skilled in the art that the present technology may be practiced without these specific details or with equivalents thereof. In other instances, well-known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the present technology.
Overview of Discussion
The present technology for low systematic offset, temperature independent voltage buffering provides a circuit and methodology and circuit architecture usable to ensure low systematic offset in a differential buffer. The voltage buffering circuit generates a bias current from the voltage that it is buffering. The bias current is such that an active current mirror node and an output node remain at the same voltage, thus causing the input devices of the differential buffer to see correspondingly equivalent voltages on all of their terminals. This causes the input devices to experience channel length modulation error which is substantially equal. As such systematic offset error is minimized and does not vary with temperature.
With respect to this Detailed Description, an exemplary embodiment of a low systematic offset, temperature independent voltage buffer circuit will be described. The discussion will start with an overview of this circuit and then move on to describe the structure and operation of blocks and components of this circuit. An exemplary method for buffering a voltage in accordance with the present technology will then be described, and will be facilitated by the discussion of the operation of the exemplary low systematic offset, temperature independent voltage buffer circuit.
Exemplary Low Systematic Offset, Temperature Independent Voltage Buffer
FIG. 2 shows a schematic of a low systematic offset, temperature independent voltage buffer 200, according to an embodiment of the present technology. Voltage buffer 200 is comprised of: a bias current generator 207; a differential input stage 205; a first current mirror 210; and a second current mirror 220.
Differential input stage 205 is configured with a non-inverting input (Vin+) coupled with an input voltage (VBUFF). The input voltage is buffered to the output of buffer 200, where it appears as an output voltage. Differential input stage 205 is comprised of two transistors, 202 and 203. In FIG. 2, transistors 202 and 203 are shown as n-type metal oxide semiconductor field effect transistors (MOSFETs). However it is appreciated that in a complementary metal oxide semiconductor (CMOS) process, the supply and ground potentials can be reversed, and the n-type MOSFETs 202 and 203 can be replaced by p-type MOSFETs. The sources of transistors 202 and 203 are coupled together to ensure that they see the same voltage potential. The gate of transistor 202 provides the non-inverting input of buffer 200. The output of buffer 200 (VOUT) is taken from the drain of transistor 203. The gate of transistor 203 provides the inverting input (Vin−) of differential input stage 205. The gate of transistor 203 is coupled to its drain, such that the inverting input of differential input stage 205 is coupled to the output of buffer 200 in a unity gain, negative feedback configuration. This configuration along with the action of current mirror 210 sets up a condition where the drain of transistor 203 and the gates of transistors 202 and 203 should see equivalent voltages that are equal to the voltage of the input voltage VBUFF. Additionally, as will be seen, the configuration of buffer circuit 200 also ensures that the drain voltage (VMIRROR) of transistor 202 is an equivalent voltage to the drain voltage (VOUT) of transistor 203.
Current mirror 210 is coupled with the supply voltage (VSUPPLY) and to differential input stage 205. Current mirror 210 sets the branch currents equal in differential input stage 205 while biasing the drain node of input device 202. Thus, current mirror 210 sets voltage (VMIRROR) on the drain of transistor 202 in differential input stage 205. As shown in FIG. 2, current mirror 210 is comprised of two transistors 211 and 212. In FIG. 2, transistors 211 and 212 are shown as p-type MOSFETs. However it is appreciated that in a CMOS process, the supply and ground potentials can be reversed, and the p-type MOSFETs 211 and 212 can be replaced by n-type MOSFETs. In FIG. 2, the sources of transistors 211 and 212 are coupled with the supply voltage and are therefore also coupled with the source of transistor 201. The gates of transistors 211 and 212 are coupled with one another, and additionally the gate of transistor 211 is coupled with the drain of transistor 211 in a diode connection configuration. The drain of transistor 211 is coupled with the drain of transistor 202, while the drain of transistor 212 is coupled with the drain of transistor 203. Current mirror 210 functions to ensure that each branch of buffer 200 sees an equivalent current, i.e., current mirror 210 ensures that the equivalent currents flow through input transistors 202 and 203.
Bias current generator 207 is coupled with a supply voltage and to the input voltage (VBUFF). The input voltage is used by bias current generator 207 to control generation of a bias current which is used to create a tail current for voltage buffer 200. As shown in FIG. 2, bias current generator is comprised of a single transistor 201. In FIG. 2, transistor 201 is shown as a p-type MOSFET. However it is appreciated that in a CMOS process, the supply and ground potentials can be reversed, and the p-type MOSFET 201 can be replaced by an n-type MOSFET. The source of transistor 201 is coupled with the supply voltage and to current mirror 210. The drain of transistor 201 is coupled with current mirror 220. The gate of transistor 201 is coupled with the input voltage (VBUFF). In this manner, transistor 201 generates a bias current under the control of the input voltage. Thus fluctuations in the input voltage due to temperature changes or other reasons will cause proportional fluctuations in the bias current generated by transistor 201. The drain of transistor 201 is coupled with current mirror 220, this allows the bias current generated in transistor 201 to be mirrored to form the tail current coupled with the source junction of transistors 202 and 203 of differential input stage 205.
Current mirror 220 is coupled with bias current generator 207 and to differential input stage 205. Current mirror 220 mirrors the bias current generated by bias current generator 207 to create a tail current for differential input stage 205. Current mirror 220 is configured in low voltage cascode configuration which is well known in the art. As shown in FIG. 2, current mirror 220 is comprised of four transistors: 221, 222, 223, and 224 which are in a cascoded arrangement. In FIG. 2, transistors 221, 222, 223, and 224 are shown as n-type MOSFETs. However, it is appreciated that in a CMOS process, the supply and ground potentials can be reversed, and the n-type MOSFETs 221, 222, 223, and 224 can be replaced by p-type MOSFETs. Transistor 221 receives the bias current from bias current generator 207. As shown, the drain of transistor 221 is coupled with the drain of transistor 201 and also to the gate of transistors 222 and 224. The source of transistor 221 is coupled with the drain of transistor 222. The gate of transistor 221 is coupled with the gate of transistor 223 and both gates are biased with a bias voltage (VCASCODE). The sources of transistors 222 and 224 are coupled with ground. The source of transistor 223 is coupled with the drain of transistor 224. Finally, the drain of transistor 224 is coupled with the common source junction of transistors 202 and 203.
In current mirror 220, transistors 221 and 222 provide a path to ground for bias current generator 207, while transistors 223 and 224 provide a path to ground for differential input stage 205 and current mirror 210. Additionally, it should be noted that in the present embodiment, transistors 223 and 224 are twice the size of transistors 221 and 222. This allows current mirror 220 to create a tail current that is twice the size of the bias current supplied as an input. It is appreciated that in other configurations, more or less transistors may be used in current mirror 220, and that transistors may be of different sizes depending on the size of the bias current received by current mirror 220 and the desired size of the tail current which current mirror 220 supplies. In the displayed embodiment of FIG. 2, doubling the bias current creates a tail current, which is split equally between input devices 202 and 203 (due to current mirror 210 causing each input device to have an equivalent current). Thus current mirror 220 supplies each input transistor (202 and 203) with a component of the tail current (namely one half of the tail current) which is equal to the bias current generated by bias current generator 207. Similarly, each branch of current mirror 210 also sees a current equivalent to the bias current. It is important to note that this tail current varies up and down in proportion to changes in the bias current.
By providing a tail current that results in branch currents in current mirror 210 and differential input stage 205 that are equivalent to the bias current, device 211 is forced to supply a mirror voltage that is equivalent to the input voltage (VBUFF). This is because transistors 201 and 211 see the same source voltage and are sourcing the same current. By definition then, when these devices are in saturation, they will also have equivalent gate voltages, which are equal to the input voltage (VBUFF). Since the drain and gate of transistor 211 are coupled, the voltage (VMIRROR) on the drain of transistor 211 will also be equivalent to (VBUFF). As the input voltage (VBUFF) fluctuates, for instance with temperature, VMIRROR will track it in synchronization since the current in device 211 will fluctuate in synchronization with and be equivalent to the bias current generated under control of the input voltage. Thus, the particular tail current supplied by current mirror 220 causes VMIRROR, to be an equivalent voltage to the input voltage and output voltage of voltage buffer 220.
By supplying a tail current that sets circuit conditions which assure that VMIRROR is equivalent to both the input voltage and output voltage of differential input stage 205, conditions on the sources, gates, and drains of input devices 202 and 203 will always see correspondingly equivalent voltages in addition to the equivalent currents that run through each input device (202 and 203). As a consequence, the drain to source voltages of input devices 202 and 203 will always be equal or substantially equal. This ensures a minimization of systematic offset error of voltage buffer 200 by minimizing differences in channel length modulation between input transistors 202 and 203. When the channel length modulation errors are substantially equivalent or exactly equivalent, related offset error will be minimized or completely eliminated. Additionally, the tail current supplied to differential input stage 205 varies in synchronization with temperature variations in the input voltage, rather than in proportion to temperature or in some other way that differs from the variations of the input voltage. This ensures that the minimized systematic offset error related to channel length modulation is temperature invariant, by causing the substantially equivalent channel length modulation errors of input devices 202 and 203 to vary in synchronization with one another.
Exemplary Method for Buffering a Voltage
The following discussion sets forth in detail the operation of an exemplary method of the present technology for low systematic offset, temperature independent voltage buffering. With reference to FIG. 3, flow diagram 300 illustrates exemplary steps used by an embodiment of the present technology. Although specific steps are disclosed in flow diagram 300, such steps are exemplary. That is, embodiments are well suited to performing various other steps or variations of the steps recited in flow diagram 300. It is appreciated that the steps in flow diagram 300 may be performed in an order different than presented and that not all of the steps may be performed.
FIG. 3 is a flow diagram 300 of a method for buffering a voltage, according to an embodiment of the present technology. Flow diagram 300 is described in conjunction with references to exemplary voltage buffer circuit 200 of FIG. 2. In the exemplary embodiment of FIG. 2, transistors 202, 203, 221, 222, 223 and 224 are shown as n-type MOSFETs and transistors 201, 211 and 212 are shown as p-type MOSFETs. However it is appreciated that in a CMOS process, the supply and ground potentials can be reversed and the n-type MOSFETs (202, 203, 221, 222, 223, and 224) can be replaced by p-type MOSFETs while the p-type MOSFETs (201, 211, and 212) are replaced by n-type MOSFETs.
In 305 of flow diagram 300, in one embodiment, a voltage buffer receives an input voltage to buffer. For example, in one embodiment illustrated in FIG. 2, this comprises receiving the input voltage on gate of input transistor 202 of differential input stage 205, and simultaneously receiving the input voltage at current generator 207 that is used for generating a bias current which is used to create a tail current for differential input stage 205. For instance, as shown in FIG. 2, current generator 207 utilizes the input voltage as a gate voltage on transistor 201.
In 315 of flow diagram 300, in one embodiment, generation of a bias current is controlled with the input voltage. For example, in FIG. 2, transistor 201, a MOSFET, functions as a current generator to generate the bias current. This bias current varies in proportion to the input voltage which is coupled with the gate of transistor 201.
In 325 of flow diagram 300, in one embodiment, drain to source voltages on input transistors of a differential input stage are ensured to be substantially equal. The substantially equal drain to source voltages ensure minimization of systematic offset error by minimizing differences in channel length modulation between the input transistors. As shown, and previously described, in conjunction with FIG. 2, in one such embodiment, current mirror 220 receives a bias current from bias current generator 207, mirrors it, and supplies the mirrored current as a tail current to differential input stage 205. For example, in FIG. 2, tail current is supplied at the junction of the source nodes of input transistors 202 and 203. Additionally, as shown in the embodiment of FIG. 2, current mirror 220 multiplies the bias current during the mirroring such that each input transistor (202 and 203) of differential input stage 205 receives a component of the tail current which is equal to the bias current.
As shown in the embodiment of FIG. 2, this tail current creates circuit conditions which ensure that voltages on the sources of transistors 202 and 203 will be equivalent, voltages on the drains of transistors 202 and 203 will be equivalent, and voltages on the gates of transistors 202 and 203 will be equivalent. Additionally, in the exemplary embodiment of FIG. 2, the currents through transistors 202 and 203 will be equivalent to one another and to the bias current. This ensures that the drain to source voltage on input transistor 202 will be substantially equivalent (or equal) to the drain to source voltage on transistor 203. When the drain to source voltages on input devices 202 and 203 are substantially equivalent, the channel length modulation error on transistor 202 will also be substantially equivalent to the channel length modulation error on transistor 203. In such conditions, offset error due to channel length modulation error differences will be minimized (or eliminated if the channel length modulation errors are exactly equal).
Moreover, the tail current is set with the bias current such that a mirror voltage supplied to the differential input stage is always equal to the input voltage. This is the same input voltage which is received at the input of the voltage buffer and is also used to create the tail current. This advantageously causes the mirror voltage to fluctuate up and down in synchronization with both the input and output voltages of the voltage buffer. Similarly, the mirror voltage experiences the same temperature fluctuations as the input voltage. A process for setting such a tail current was previously shown and described in conjunction with the embodiment of FIG. 2. In the exemplary embodiment shown in FIG. 2, an advantage that results from this is that the gate source voltages of input devices 202 and 203 will be substantially equivalent across temperature, thus ensuring that the systematic offset error related to channel length modulation is temperature invariant.
Embodiments of the present technology for low systematic offset, temperature independent voltage buffering are thus described. While the present technology has been described in particular embodiments, it should be appreciated that the present technology should not be construed as limited by such embodiments, but rather construed according to the below claims.
Patent Application
20080030240
