Patent Application
20120309269
The present disclosure relates to semiconductor device manufacturing, and more particularly, to methods for controlling the removal of a surface layer from a base substrate utilizing low-temperature spontaneous spalling.
Devices that can be produced in thin-film form have three clear advantages over their bulk counterparts. First, by virtue of less material used, thin-film devices ameliorate the materials cost associated with device production. Second, low device weight is a definite advantage that motivates industrial-level effort for a wide range of thin-film applications. Third, if dimensions are small enough, devices can exhibit mechanical flexibility in their thin-film form. Furthermore, if a device layer is removed from a substrate that can be reused, additional fabrication cost reduction can be achieved.
Efforts to (i) create thin-film substrates from bulk materials (i.e., semiconductors) and (ii) form thin-film device layers by removing device layers from the underlying bulk substrates on which they were formed are ongoing. The controlled surface layer removal required for such applications has been successfully demonstrated using a process known as spalling; see U.S. Patent Application Publication No. 2010/0311250 to Bedell et al. Spalling includes depositing a stressor layer on a substrate, placing an optional handle substrate on the stressor layer, and inducing a crack and its propagation below the substrate/stressor interface. This process, which is performed at room temperature, removes a thin layer of the base substrate below the stressor layer. By thin, it is meant that the layer thickness is typically less than 100 microns, with a layer thickness of less than 50 microns being more typical.
The depth of at which the crack propagates is dictated by the thickness of the stressor layer, the inherent tensile stress of the stressor layer, and the fracture toughness of the base substrate being exfoliated (spalled). However, control of the initiation of the release layer process (crack initiation and propagation) and uniformity in the thickness of the spalled material are difficult to achieve utilizing prior art spalling processes.
The present disclosure provides methods to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths. The methods of the present disclosure are spontaneous spalling processes which are performed below room temperature, not mechanical spalling processes which are performed at room temperature as disclosed, for example, in U.S. Patent Application Publication No. 2010/0311250 to Bedell et al.
By “spontaneous,” it is meant that the removal of a thin material layer from a base substrate occurs without the need to employ any manual means to initiate crack formation and propagation for breaking apart the thin material layer from the base substrate. By “room temperature,” it is meant a temperature from 15° C. to 40° C. By “low-temperature spalling,” it is meant the removal of a material layer from a base substrate at a temperature below room temperature.
In one embodiment, the method of the present disclosure includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature; bringing the base substrate including the stressor layer to a second temperature which is less than room temperature; spalling the base substrate at the second temperature to form a spalled material layer; and returning the spalled material layer to room temperature.
In another embodiment, the method includes providing a stressor layer on a surface of a base substrate at a first temperature which is room temperature; bringing the base substrate including the stressor layer to a second temperature of less than 206 Kelvin (K); spalling the base substrate at the second temperature to form a spalled material layer; and returning the spalled material layer to room temperature.
In yet another embodiment, the method includes providing a spall inducing tape layer on a surface of a base substrate at a first temperature which at approximately room temperature or slightly above (e.g., from 15° C. to 60° C.); bringing the base substrate including the spall inducing tape layer to a second temperature which is less than room temperature; spalling the base substrate at the second temperature to form a spalled material layer; and returning the spalled material layer to room temperature.
In yet a further embodiment, the method of the present disclosure includes providing a two-part stressor layer on a surface of a base substrate, wherein a lower part of the two-part stressor layer is formed at a first temperature which at approximately room temperature or slightly above (e.g., from 15° C. to 60° C.), wherein an upper part of the two-part stressor layer comprises a spall inducing tape layer at an auxiliary temperature which is room temperature; bringing the base substrate including the two-part stressor layer to a second temperature which is less than room temperature; spalling the base substrate at the second temperature to form a spalled material layer; and returning the spalled material layer to room temperature.
By using one of the aforementioned methods, the effective stress that induces material spalling is modified owing to differential thermal expansion, crystal structure changes at the crack front, fracture toughness value differences at lower-than-room temperatures, to reach a stress regime necessary for spalling-type fracture that would not be reached using the room temperature spalling technique disclosed in U.S. Patent Application Publication No. 2010/0311250.
One advantage of the aforementioned spalling methods of the present disclosure is that the layer release process is spontaneous at all stages of the process, from spall initiation through spall completion. Another advantage of the present methods is that the component of stressor layer stress due to thermal expansion mismatch stress is reversible and will disappear upon warming back to room temperature, thus providing a spalled stressor layer/spalled film couple that is flatter at room temperature than at the temperature at which it was spalled. Yet another advantage of the present methods is that they widen the process window for controlled, spontaneous spalling: base substrates including stressor layers having thickness/stress values lower than the threshold required for spalling at room temperature can be safely stored at room temperature until spontaneous spalling is deliberately introduced by a temperature reduction.
The present disclosure, which relates to methods to (i) introduce additional control into a material spalling process, thus improving both the crack initiation and propagation, and (ii) increase the range of selectable spalling depths, will now be described in greater detail by referring to the following discussion and drawings that accompany the present application. It is noted that the drawings of the present application are provided for illustrative purposes and, as such, they are not drawn to scale.
In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps and techniques, in order to provide a thorough understanding of the present invention. However, it will be appreciated by one of ordinary skill in the art that the present disclosure may be practiced with viable alternative process options without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the various embodiments of the present disclosure.
It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present.
Reference is now made to
Specifically,
Referring first to
Fracture toughness is a property which describes the ability of a material containing a crack to resist fracture. Fracture toughness is denoted KIc. The subscript Ic denotes mode I crack opening under a normal tensile stress perpendicular to the crack, and c signifies that it is a critical value. Mode I fracture toughness is typically the most important value because spalling mode fracture usually occurs at a location in the substrate where mode II stress (shearing) is zero, and mode III stress (tearing) is generally absent from the loading conditions. Fracture toughness is a quantitative way of expressing a material's resistance to brittle fracture when a crack is present.
When the base substrate 10 comprises a semiconductor material, the semiconductor material may include, but is not limited to, Si, Ge, SiGe, SiGeC, SiC, Ge alloys, GaSb, GaP, GaAs, InAs, InP, and all other III-V or II-VI compound semiconductors. In some embodiments, the base substrate 10 is a bulk semiconductor material. In other embodiments, the base substrate 10 may comprise a layered semiconductor material such as, for example, a semiconductor-on-insulator or a semiconductor on a polymeric substrate. Illustrated examples of semiconductor-on-insulator substrates that can be employed as base substrate 10 include silicon-on-insulators and silicon-germanium-on-insulators.
When the base substrate 10 comprises a semiconductor material, the semiconductor material can be doped, undoped or contain doped regions and undoped regions.
In one embodiment, the semiconductor material that can be employed as the base substrate 10 can be single crystalline (i.e., a material in which the crystal lattice of the entire sample is continuous and unbroken to the edges of the sample, with no grain boundaries). In another embodiment, the semiconductor material that can be employed as the base substrate 10 can be a polycrystalline (i.e., a material that is composed of many crystallites of varying size and orientation; the variation in direction can be random (called random texture) or directed, possibly due to growth and processing conditions). It is noted that when the semiconductor material is a polycrystalline material the spalling process of the present disclosure spalls certain grains, while leaving certain grains unspalled. As such, spalling of polycrystalline semiconductor material using the low-temperature spalling process of the present disclosure may produce a non-continuous spalled material layer. In yet another embodiment of the present disclosure, the semiconductor material that can be employed as the base substrate 10 can be amorphous (i.e., a non-crystalline material that lacks the long-range order characteristic of a crystal). Typically, the semiconductor material that can be employed as the base substrate 10 is a single crystalline material.
When the base substrate 10 comprises a glass, the glass can be an SiO2-based glass which may be undoped or doped with an appropriate dopant. Examples of doped SiO2-based glasses that can be employed as the base substrate 10 include undoped silicate glass, borosilicate glass, phosphosilicate glass, fluorosilicate glass, and borophosphosilicate glass.
When the base substrate 10 comprises a ceramic, the ceramic is any inorganic, non-metallic solid such as, for example, an oxide including, but not limited to, alumina, beryllia, ceria and zirconia, a non-oxide including, but not limited to, a carbide, a boride, a nitride or a silicide; or composites that include combinations of oxides and non-oxides.
In some embodiments of the present disclosure, one or more devices including, but not limited to, transistors, capacitors, diodes, BiCMOS, resistors, etc. can be processed on and/or within the upper surface 12 of the base substrate 10 utilizing techniques well known to those skilled in the art. The upper portion of the base substrate that includes the one or more devices can be removed utilizing the spalling methods of the present disclosure.
In some embodiments of the present disclosure, the upper surface 12 of the base substrate 10 can be cleaned prior to further processing to remove surface oxides and/or other contaminants therefrom. In one embodiment of the present disclosure, the base substrate 10 is cleaned by applying to the base substrate 10 a solvent such as, for example, acetone and isopropanol, which is capable of removing contaminates and/or surface oxides from the upper surface 12 of the base substrate 10.
Referring now to
The optional metal-containing adhesion layer 14 employed in the present disclosure includes any metal adhesion material such as, but not limited to, Ti/W, Ti, Cr, Ni or any combination thereof. The optional metal-containing adhesion layer 14 may comprise a single layer or it may include a multilayered structure comprising at least two layers of different metal adhesion materials.
The metal-containing adhesion layer 14 that can be optionally formed on the upper surface 12 of base substrate 12 is formed at room temperature (15° C.-40° C.) or above. In one embodiment, the optional metal-containing adhesion layer 14 is formed at a temperature which is from 20° C. to 180° C. In another embodiment, the optional metal-containing adhesion layer 14 is formed at a temperature which is from 20° C. to 60° C.
The metal-containing adhesion layer 14, which may be optionally employed, can be formed utilizing deposition techniques that are well known to those skilled in the art. For example, the optional metal-containing adhesion layer 14 can be formed by sputtering, chemical vapor deposition, plasma enhanced chemical vapor deposition, chemical solution deposition, physical vapor deposition, and plating. When sputter deposition is employed, the sputter deposition process may further include an in-situ sputter clean process before the deposition.
When employed, the optional metal-containing adhesion layer 14 typically has a thickness of from 5 nm to 200 nm, with a thickness of from 100 nm to 150 nm being more typical. Other thicknesses for the optional metal-containing adhesion layer 14 that are below and/or above the aforementioned thickness ranges can also be employed in the present disclosure.
Referring now to
The stressor layer 16 employed in the present disclosure includes any material that is under tensile stress on base substrate 10 at the spalling temperature. Illustrative examples of such materials that are under tensile stress when applied atop the base substrate 10 include, but are not limited to, a metal, a polymer, such as a spall inducing tape layer, or any combination thereof. The stressor layer 16 may comprise a single stressor layer, or a multilayered stressor structure including at least two layers of different stressor material can be employed.
In one embodiment, the stressor layer 16 is a metal, and the metal is formed on an upper surface of the optional metal-containing adhesion layer 14. In another embodiment, the stressor layer 16 is a spall inducing tape, and the spall inducing tape is applied directly to the upper surface 12 of the base substrate 10. In another embodiment, for example, the stressor layer 16 may comprise a two-part stressor layer including a lower part and an upper part. The upper part of the two-part stressor layer can be comprised of a spall inducing tape layer.
When a metal is employed as the stressor layer 16, the metal can include, for example, Ni, Cr, Fe or W. Alloys of these metals can also be employed. In one embodiment, the stressor layer 16 includes at least one layer consisting of Ni.
When a polymer is employed as the stressor layer 16, the polymer is a large macromolecule composed of repeating structural units. These subunits are typically connected by covalent chemical bonds. Illustrative examples of polymers that can be employed as the stressor layer 16 include, but are not limited to, polyimides polyesters, polyolefins, polyacrylates, polyurethane, polyvinyl acetate, and polyvinyl chloride.
When a spall inducing tape layer is employed as the stressor layer 16, the spall inducing tape layer includes any pressure sensitive tape that is flexible, soft, and stress free at the first temperature used to form the tape, yet strong, ductile and tensile at the second temperature used during removal of the upper portion of the base substrate. By “pressure sensitive tape,” it is meant an adhesive tape that will stick with application of pressure, without the need for solvent, heat, or water for activation. Tensile stress in the tape at the second temperature is primarily due to thermal expansion mismatch between the base substrate 10 (with a lower thermal coefficient of expansion) and the tape (with a higher thermal expansion coefficient).
Typically, the pressure sensitive tape that is employed in the present disclosure as stressor layer 16 includes at least an adhesive layer and a base layer. Materials for the adhesive layer and the base layer of the pressure sensitive tape include polymeric materials such as, for example, acrylics, polyesters, olefins, and vinyls, with or without suitable plasticizers. Plasticizers are additives that can increase the plasticity of the polymeric material to which they are added.
In one embodiment, the stressor layer 16 employed in the present disclosure is formed at a first temperature which is at room temperature (15° C.-40° C.). In another embodiment, when a tape layer is employed, the tape layer can be formed at a first temperature which is from 15° C. to 60° C.
When the stressor layer 16 is a metal or polymer, the stressor layer 16 can be formed utilizing deposition techniques that are well known to those skilled in the art including, for example, dip coating, spin-coating, brush coating, sputtering, chemical vapor deposition, plasma enhanced chemical vapor deposition, chemical solution deposition, physical vapor deposition, and plating.
When the stressor layer 16 is a spall inducing tape layer, the tape layer can be applied by hand or by mechanical means to the structure. The spall inducing tape can be formed utilizing techniques well known in the art or they can be commercially purchased from any well known adhesive tape manufacturer. Some examples of spall inducing tapes that can be used in the present disclosure as stressor layer 16 include, for example, Nitto Denko 3193MS thermal release tape, Kapton KPT-1, and Diversified Biotech's CLEAR-170 (acrylic adhesive, vinyl base).
In one embodiment, a two-part stressor layer can be formed on a surface of a base substrate, wherein a lower part of the two-part stressor layer is formed at a first temperature which is at room temperature or slight above (e.g., from 15° C. to 60° C.), wherein an upper part of the two-part stressor layer comprises a spall inducing tape layer at an auxiliary temperature which is at room temperature. Next, the base substrate including the two-part stressor layer is brought to a second temperature which is less than room temperature. The base substrate 10 is then spalled at the second temperature to form a spalled material layer. The spalled material layer is then returned to room temperature.
If the stressor layer 16 is of a metallic nature, it typically has a thickness of from 3 μm to 50 μm, with a thickness of from 4 μm to 7 μm being more typical. Other thicknesses for the stressor layer 16 that are below and/or above the aforementioned thickness ranges can also be employed in the present disclosure.
If the stressor layer 16 is of a polymeric nature, it typically has a thickness of from 10 μm to 200 μm, with a thickness of from 50 μm to 100 μm being more typical. Other thicknesses for the stressor layer 16 that are below and/or above the aforementioned thickness ranges can also be employed in the present disclosure.
Referring to
The optional handle substrate 18 can be used to provide better fracture control and more versatility in handling the spalled portion of the base substrate 10. Moreover, the optional handle substrate 18 can be used to guide the crack propagation during the spontaneous spalling process of the present disclosure.
The optional handle substrate 18 of the present disclosure is typically, but not necessarily, formed at a first temperature which is at room temperature (15° C.-40° C.).
The optional handle substrate 18 can be formed utilizing deposition techniques that are well known to those skilled in the art including, for example, dip coating, spin-coating, brush coating, sputtering, chemical vapor deposition, plasma enhanced chemical vapor deposition, chemical solution deposition, physical vapor deposition, and plating.
The optional handle substrate 18 typical has a thickness of from 1 μm to few mm, with a thickness of from 70 μm to 120 μm being more typical. Other thicknesses for the optional handle substrate 18 that are below and/or above the aforementioned thickness ranges can also be employed in the present disclosure.
Referring to
The spontaneous spalling process includes crack formation and propagation which are initiated at a second temperature that is less than room temperature. In one embodiment, the spontaneous spalling occurs at a second temperature of 77 K or less. In another embodiment, the spontaneous spalling occurs at a second temperature of less than 206 K. In yet further embodiment, the second temperature, e.g., the spontaneous spalling temperature, is from 175 K to 130 K.
Within the second temperature range mentioned above, a crack begins to initiate and propagate spontaneously beneath the upper surface 12 of the base substrate 10.
The second temperature used in the present disclosure for spalling can be achieved by cooling the structure shown in
The spalled material layer 10″ that is removed from the base substrate 10 by the spontaneous spalling process mentioned above typically has a thickness of from 1000 nm to tens of μm, with a thickness of from 5 μm to 50 μm being more typical. The thickness of the spalled material layer 10″ correlates to the depth of crack initiation and propagation.
After the spalling process, the spalled material layer 10″ is returned to the first temperature (i.e., room temperature). This can be performed by allowing the spalled material layer 10″ to slowly cool up to the first temperature by allowing the same to stand at room temperature. Alternatively, the spalled material layer 10″ can be heated up to room temperature utilizing any heating means.
In some embodiments of the present disclosure, the optional handle substrate 18, the stressor layer 16 and the optional metal-containing adhesion layer 14 can be removed from the spalled material layer 10″. When the optional handle substrate 18, stressor layer 16 and the optional metal-containing adhesion layer 14 are removed from the spalled material layer 10″, the removal of those layers can be achieved utilizing conventional techniques well known to those skilled in the art. For example, and in one embodiment, aqua regia (HNO3/HCl) can be used for removing the optional handle substrate 18, the stressor layer 16 and the optional metal-containing adhesion layer 14 from the spalled material layer 10″.
The present disclosure can be used in fabricating various types of thin-film devices including, but not limited to, semiconductor devices, and photovoltaic devices.
While the present disclosure has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present disclosure. It is therefore intended that the present disclosure not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
