Low voltage bipolar transistor logic circuit

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and more specifically to a semiconductor integrated circuit device suitable for use in an ECL (Emitter Coupled Logic).
2. Description of the Prior Art
FIG. 1 shows a conventional semiconductor integrated circuit device including a three-stage series-gating differential logic circuit (in which single-ended logic circuits are series-gated in three stages) and an emitter follower output circuit using an NPN transistor 10. Each stage of the logic circuit is composed of two NPN transistors Q.sub.i and Q.sub.iN (i=1, 2 and 3) whose emitters are connected to each other. In the first (uppermost) stage logic circuit, the collector of the transistor Q.sub.1 is connected to a ground supply voltage via a resistor R.sub.L1 ; the base thereof is connected to an input terminal IN1; the collector of the transistor Q.sub.1N is connected to the ground supply voltage via a resistor R.sub.L2 ; and a potential V.sub.BB1 (an intermediate value of an amplitude of a signal potential V.sub.IN1 inputted from the outside to the input terminal IN1) is applied to the base thereof. Further, the collector of the transistor Q.sub.2 of the second (intermediate) stage logic circuit is connected to an emitter junction point C1 between the pair of first stage differential transistors Q.sub.1 and Q.sub.1N ; a signal potential V.sub.IN2 is inputted to the base of the transistor Q.sub.2. The level of the signal potential V.sub.IN2 is shifted by a level shift circuit composed of an NPN transistor T.sub.1 and a constant current source 30.sub.1. Further, a potential V.sub.BB2 (an intermediate value of an amplitude of a signal potential V.sub.IN2) is applied to the base of the transistor Q.sub.2N of the pair of differential transistors Q.sub.2 and Q.sub.2N. Further, the collector of the transistor Q.sub.3 of the third (lowermost) stage logic circuit is connected to an emitter junction point C2 between the pair of the second stage differential transistors Q.sub.2 and Q.sub.2N ; a signal potential V.sub.IN3 is inputted to the base of the transistor Q.sub.3. The level of the signal potential V.sub.IN3 is shifted by another level shift circuit composed of an NPN transistor T.sub.2, a diode D.sub.1 and a constant current source 30.sub.2. Further, a potential V.sub.BB3 (an intermediate value of an amplitude of a signal potential V.sub.IN3) is applied to the base of the transistor Q.sub.3N of the pair of differential transistors Q.sub.3 and Q.sub.3N. Further, a constant current source composed of an NPN transistor Q.sub.4 and a resistor R.sub.CS is connected to a junction point C3 between the pair of differential transistors Q.sub.3 and Q.sub.3N. Further, an output V.sub.0 of the differential logic circuit is taken out of the collector of the transistor Q.sub.1N, and then transmitted to the base of an emitter follower transistor 10. A constant current source circuit composed of an NPN transistor Q.sub.5 and a resistor R.sub.EF is connected to the emitter of the transistor 10, and an output OUT of the semiconductor integrated circuit device is taken out of the emitter of the transistor 10. Further, the resistances of the resistors R.sub.L1 and R.sub.L2 are equal to each other, and a potential V.sub.CS is applied to the bases of the transistors Q.sub.4 and Q.sub.5 of the constant current source circuit. Here, it is assumed that the built-in potential .phi. of the p-n junction is .phi.=0.9 V (the potential .phi. being the base-emitter voltage of a transistor); the logical amplitude 2v of the single ended logic circuit is 2v=2.phi./3=0.6 V; and the non-saturated range of the bipolar transistor is V.sub.CE .gtoreq.V.sub.CENS =.phi./3=0.3 V. Here, V.sub.CE denotes the collector-emitter voltage of the transistor; and V.sub.CENS denotes the minimum collector-emitter voltage at which the transistor will not be saturated.
In the semiconductor integrated circuit device as shown in FIG. 1, in general, signals whose levels are shifted by diodes (not shown) are inputted to the input terminals IN1, IN2 and IN3, respectively. Therefore, the potential V.sub.IN1 applied to the base of the uppermost stage transistor Q.sub.1 varies in a range from (-.phi.) to (-.phi.-2v); the potential V.sub.IN2 applied to the base of the intermediate stage transistor Q.sub.2 is a potential obtained by shifting the potential V.sub.IN2 applied to the input terminal IN2 by .phi. by the transistor T.sub.1 and varies in a range from (-2.phi.) to (-2.phi.-2v); and the potential V.sub.IN3 applied to the base of the lowermost stage transistor Q.sub.3 is a potential obtained by shifting the potential V.sub.IN3 applied to the input terminal IN3 by 2.phi. by the transistor T.sub.2 and the diode D.sub.1 and varies in a range from (-3.phi.) to (-3.phi.-2v), as shown in FIG. 2.
Therefore, the potential at the node C1 varies in a range from (-2.phi.) to (-2.phi.-v); the potential at the node C2 varies in a range from (-3.phi.) to (-3.phi.-v); and the potential at the node C3 varies in a range from (-4.phi.) to (-4.phi.-v); and further the output V.sub.o of the differential logic stage circuit varies in a range from (0) to (-2 v), as shown in FIG. 2.
Therefore, the voltage applied to the uppermost stage logic circuit is the collector-emitter voltage V.sub.CEQ1 (.gtoreq.2(.phi.-v)=1.2 V) of the transistor Q.sub.1 ; the voltage applied to the intermediate stage logic circuit is the collector-emitter voltage V.sub.CEQ2 (.gtoreq..phi.-v=0.6 V) of the transistor Q.sub.2 ; and the voltage applied to the lowermost stage logic circuit is the collector-emitter voltage V.sub.CEQ3 (.gtoreq..phi.-v=0.6 V) of the transistor Q.sub.3, respectively.
Further, FIG. 3 shows another example of the convectional semiconductor integrated circuit device. This circuit device is formed such that three input terminals IN1N, IN2N and IN3N, two NPN transistors T.sub.1N and T.sub.2N, and two constant current sources 30.sub.1N and 30.sub.2N are additionally provided in the semiconductor integrated circuit device shown in FIG. 1. Further, the circuit device shown in FIG. 3 is formed such that the three-stage series-gating single ended logic circuit of FIG. 1 is changed into a differential logic stage circuit. Further, the levels of potential V.sub.INiN applied to the input terminals INiN (i=1, 2 and 3) are shifted by diodes (not shown) in the same way as with the case of the potential V.sub.IN1 applied to the input terminal IN1. Further, since the logical amplitude of the differential logic circuit is a half of the logical amplitude of the single ended logic circuit, the potentials V.sub.INi and V.sub.INiN applied to the input terminals INi and INiN (i=1, 2 and 3) vary in a range from (-.phi.) to (-.phi.-v), as shown in FIG. 4. In other words, the level of the potential applied to the base of the transistor Q.sub.2N is the potential from (-2.phi.) to (-2.phi.-v) shifted by .phi. by the transistor T.sub.1N, and the level of the potential applied to the base of the transistor Q.sub.3N is the potential from (-3.phi.) to (-3.phi.-v) shifted by 2.phi. by the transistor T.sub.2N and the diode D.sub.2. Therefore, the respective node potentials of the three-stage series-gating differential logic circuit shown in FIG. 3 can be shown as in FIG. 4, which can be obtained by replacing v (shown in FIG. 2) with 0.5 v.
Table 1 shows voltages applied to the transistors of differential stages of the conventional semiconductor integrated circuit devices shown in FIGS. 1 and 3.
TABLE 1______________________________________ INTER STAGE (V.sub.CEQ2) UPPER STAGE (V.sub.CEQ1) LOWER STAGE (V.sub.CEQ3)______________________________________SINGLE ENDED 2 (.phi. - v) = 1.2V .phi. - v = 0.6VTYPEDIFFERENTIAL 2 (.phi. - 0.5v) = 1.5V .phi. - 0.5v = 0.75VTYPE______________________________________ (.phi. = 0.9V; v = 0.3V
As understood in Table 1, since the collector-emitter voltage V.sub.CE applied to the respective transistors of the differential stages is higher than V.sub.CENS =.phi./3=0.3 V, the respective transistors can operate always in the non-saturated range, irrespective of the supply voltage.
In the semiconductor integrated circuits shown in FIGS. 1 and 3, however, when the supply voltage V.sub.EE applied to the lower end (in the figures) of the resistor R.sub.CS and R.sub.EF is reduced, since the transistor Q.sub.4 constituting the constant current source circuit of the differential stage enters the saturated range, the current of the constant current source circuit decreases abruptly and thereby the output amplitude decreases, so that the semiconductor integrated circuits may operate erroneously. Here, if the voltage applied across the constant current source circuit composed of the transistor Q.sub.4 and the resistor R.sub.CS is expressed as V.sub.CSmin (=V.sub.CEQ4min +V.sub.RCS4min' : about 0.7 V), the minimum operating supply voltage .vertline.V.sub.EEmin .vertline. of the ECL (Emitter Coupled Logic) circuit can be expressed as listed in Table 2.
TABLE 2______________________________________NO. OF .backslash.V.sub.EEmin .backslash.STAGES SINGLE ENDED TYPE DIFFERENTIAL TYPE______________________________________3 4.phi. + v + V.sub.CSmin = 4.6V 4.phi. + 0.5v + V.sub.CSmin = 4.45VSTAGES2 3.phi. + v + V.sub.CSmin = 3.7V 3.phi. + 0.5v + V.sub.CSmin = 3.55VSTAGES1 STAGE 2.phi. + v + V.sub.CSmin = 2.8V 2.phi. + 0.5v + V.sub.CSmin = 2.65V______________________________________ .phi. = 0.9V; v = 0.3V; V.sub.CSmin = 0.7V)
Table 2 indicates that it is effective to reduce the value .phi. when the voltage of the ECL circuit is required to be reduced. On the other hand, Table 1 indicates that even if .phi. is reduced, there still exists a margin until the respective transistors of the differential stages enter the saturation range.
However, .phi. cannot be much varied even if the impurity concentration of the p-n junction is varied. Therefore, the value .phi. is roughly constant in all the device generations, so that it has been impossible to reduce the minimum operating voltage of the ECL circuit.
SUMMARY OF THE INVENTION
With these problems in mind, therefore, it is the object of the present invention to provide a semiconductor integrated circuit device operative at a low supply voltage, without deteriorating the functions and performance thereof as much as possible.
To achieve the above-mentioned object, the first aspect of the present invention provides a semiconductor integrated circuit device, comprising: a differential logic stage circuit formed by multi-stage series-gating logic circuits each composed of a plurality of bipolar transistors whose emitters are connected in common; and a plurality of level shift circuits each for shifting each level of an input signal inputted from the outside in correspondence to each stage logic circuit of said differential logic stage circuit, and for outputting each level-shifted input signal to each of bases of the bipolar transistors of the corresponding stage logic circuit. In each of said level shift circuits, a potential difference between the level-shifted signals inputted to the bases of the bipolar transistors of the logic circuits connected to each other is determined, as a level shift rate, to be lower than a built-in potential between the base and emitter of each of the bipolar transistors.
Further, the second aspect of the present invention provides a semiconductor integrated circuit device, comprising: a differential logic circuit formed by multi-stage series-gating logic circuits each composed of a plurality of bipolar transistors whose emitters are connected in common, a first specific circuit, among the multi-stage series-connected logic circuits, being connected to a current source and a second specific circuit being connected to at least one load circuit; and a plurality of level shift circuits each for shifting each level of an input signal inputted from the outside in correspondence to each stage logic circuit of said differential logic circuit, and for outputting each level-shifted input signal to each of bases of the bipolar transistors of the corresponding stage logic circuit except the first specific circuit. In each of said level shift circuits, a potential difference between the level-shifted signals inputted to the bases of the bipolar transistors of the logic circuits connected to each other is determined, as a level shift rate, to be lower than a built-in potential between the base and emitter of each of the bipolar transistors.
Further, in the first and second aspects of the present invention, the logic circuits of said differential logic circuit are of differential type, and said level shift circuits are composed of differential current mode logic gates.
Further, in the first and second aspects of the present invention, the logic circuits of said differential logic circuit are of differential type, and said level shift circuits are composed of single ended current mode logic gates.
Further, in the first and second aspect of the present invention, the logic circuits of said differential logic circuit are of single ended type, and said level shift circuits are composed of single ended current mode logic gates.
Further, the third aspect of the present invention provides a semiconductor integrated circuit device, comprising: a plurality of first to n-th (n.gtoreq.2) differential logic circuits each formed by multi-stage series gating logic circuits each composed of a plurality of bipolar transistors whose emitters are connected in common, a first specific circuit, among the multi-stage series-gating logic circuits, being connected to a current source and a second specific circuit, among the multi-stage series-gating logic circuits, being connected to at least one load resistor; and a plurality of level shift circuits each for shifting each level of an input signal inputted from the outside in correspondence to each stage logic circuit of said first differential logic stage circuit, and for outputting each level-shifted input signal to each of the bases of the bipolar transistors of the corresponding logic circuit. In each of said level shift circuits, a potential difference between the level-shifted signals inputted to the bases of the bipolar transistors of the logic circuits of said first differential logic circuit is determined, as a level shift rate, to be lower than a built-in potential between the base and emitter of each of the bipolar transistors thereof. The first to n-th differential logic circuits are connected in cascade at n-stages, and a resistor is connected between the load resistor and a power supply, of each of said first to (n-1)-th differential logic circuits, and the supply voltage so that the input levels of the second to n-th differential logic circuits are equalized to the input level of the first differential logic stage circuit.
In the first to third aspects of the present invention, the current source may be interpreted as a resistor.
In the semiconductor integrated circuit device according to the present invention, a potential difference between the signals inputted to the bases of the bipolar transistors of the differential logic circuits is determined, as a level shift rate, to be lower than a built-in potential .phi. between the base and emitter of the bipolar transistors. Accordingly, it is possible to reduce the level of the input signal applied to each transistor to a limit at which each transistor of each differential stage enters the saturation range, with the result that the semiconductor integrated circuit device according to the present invention is operative on a lower supply voltage, without degrading the functions and performance thereof as much as possible.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram showing the first prior art semiconductor integrated circuit device;
FIG. 2 is a typical diagram showing the potential levels of the respective nodes of the first prior art circuit device shown in FIG. 1;
FIG. 3 is a circuit diagram showing the second prior art semiconductor integrated circuit device;
FIG. 4 is a typical diagram showing the potential levels of the respective nodes of the first prior art circuit device shown in FIG. 3;
FIG. 5 is a circuit diagram showing a first embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 6 is a typical diagram showing the potential levels at the respective nodes of the first embodiment thereof;
FIG. 7 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 8 is a typical diagram showing the potential levels at the respective nodes of the second embodiment thereof;
FIG. 9 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 10 is a typical diagram showing the potential levels at the respective nodes of the third embodiment thereof;
FIG. 11 is a circuit diagram showing a fourth embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 12 is a typical diagram showing the potential levels at the respective nodes of the fourth embodiment thereof;
FIG. 13 is a circuit diagram showing a fifth embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 14 is a typical diagram showing the potential levels at the respective nodes of the fifth embodiment thereof;
FIG. 15 is a circuit diagram showing a sixth embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 16 is a typical diagram showing the potential levels at the respective nodes of the sixth embodiment thereof;
FIG. 17 is a circuit diagram showing a seventh embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 18 is a typical diagram showing the potential levels at the respective nodes of the seventh embodiment thereof;
FIGS. 19A to 19C are circuit diagrams showing three reference voltage generating circuits related to the seventh embodiment, respectively;
FIG. 20 is a circuit diagram showing an eighth embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 21 is a typical diagram showing the potential levels at the respective nodes of the eighth embodiment thereof;
FIG. 22 is a circuit diagram showing an ninth embodiment of the semiconductor integrated circuit device according to the present invention;
FIG. 23 is a typical diagram showing the potential levels of the respective nodes of the ninth embodiment thereof;
FIG. 24 is a circuit diagram showing a tenth embodiment of the semiconductor integrated circuit device according to the present invention;
FIGS. 25A to 25F are circuit diagrams showing an eleventh embodiment of the semiconductor integrated circuit device according to the present invention;
FIGS. 26A to 26F are circuit diagrams showing a twelfth embodiment of the semiconductor integrated circuit device according to the present invention;
FIGS. 27A to 27E are is circuit diagrams showing a thirteenth embodiment of the semiconductor integrated circuit device according to the present invention;
FIGS. 28A to 28G are circuit diagrams showing a fourteenth embodiment of the semiconductor integrated circuit device according to the present invention;
FIGS. 29A to 29E are circuit diagrams showing a fifteenth embodiment of the semiconductor integrated circuit device according to the present invention; and
FIGS. 30A and 30B are is circuit diagrams showing a sixteenth embodiment of the semiconductor integrated circuit device according to the present invention;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 5 shows a first embodiment of the semiconductor integrated circuit device according to the present invention. This circuit device is composed of three-stage series-gating differential logic circuit, first to third level shifter circuits, and an emitter follower output circuit. Each stage of the logic circuit is composed of two NPN transistors Q.sub.i and Q.sub.iN (i=1, 2 and 3). The collector of the transistor Q.sub.1 of the first (uppermost) stage logic circuit is connected to a ground supply voltage via a load resistor R.sub.L1 ; and the collector of the transistor Q.sub.1N thereof is connected to a ground supply voltage via a load resistor R.sub.L2. Further, the collector of the transistor Q.sub.2 of the second (intermediate) stage logic circuit is connected to an emitter junction point C1 between the pair of preceding stage differential transistors Q.sub.i and Q.sub.1N. Further, the collector of the transistor Q.sub.3 of the third (lowermost) stage logic circuit is connected to an emitter junction point C2 between the pair of second stage differential transistors Q.sub.2 and Q.sub.2N. Further, an emitter junction point C3 between the pair of third stage differential transistors Q.sub.3 and Q.sub.3N is connected to a drive supply voltage via a constant current source 8. Further, the resistances of both resistors R.sub.L1 and R.sub.L2 are equal to each other.
On the other hand, the i-th (i=1, 2 and 3) level shift circuit is composed of a resistor r.sub.i, a resistor R.sub.i1, a resistor R.sub.i2, a pair of differential NPN transistors T.sub.i and T.sub.iN, and a constant current source 20.sub.i. One end of the resistor r.sub.i (i=1, 2 and 3) is connected to the ground supply voltage, and the other end thereof is connected to one end of the two resistors R.sub.i1 and R.sub.i2. The other end of the resistor R.sub.i1 (i=1, 2 and 3) is connected to the collector of the transistor T.sub.i, and the other end of the resistor R.sub.i2 (i=1, 2 and 3) is connected to the collector of the transistor T.sub.iN. The emitters of the pair of the differential transistors T.sub.i and T.sub.iN (i=1, 2 and 3) are connected in common to a drive supply voltage via the constant current source 20.sub.i. The base of transistor T.sub.i (i=1, 2 and 3) is connected to an input terminal IN.sub.i to which an external signal is inputted, and the base of transistor T.sub.iN (i=1, 2 and 3) is connected to an input terminal IN.sub.iN. Further, one output V.sub.INi of the i-th (i=1, 2 and 3) level shift circuit is outputted from the collector of the transistor T.sub.iN and then transmitted to the base of the transistor Q.sub.i of the i-th stage logic circuit, and the other output V.sub.1NiN of the i-th (i=1, 2 and 3) level shift circuit is outputted from the collector of the transistor T.sub.i and then transmitted to the base of the transistor Q.sub.iN of the i-th stage differential ECG gate. Further, the resistances of the resistors R.sub.11, R.sub.12, R.sub.21, R.sub.22, R.sub.31 and R.sub.32 are equal to each other; and the current I.sub.LS flowing through the constant current sources 20.sub.1, 20.sub.2 and 20.sub.3 are also equal to each other.
Further, the output V.sub.o of the differential logic circuit is outputted from the collector of the transistor Q.sub.1N, transmitted to the base of the transistor 10 of the output circuit, and then outputted from the emitter of the transistor 10 to the outside. Further, the transistor 10 is connected to a supply voltage via a constant current source 15.
In the first embodiment of the semiconductor integrated circuit device according to the present invention, the first to third level shift circuits of CML (Current Mode Logic) gate type are used as the level shift circuits for the input signals of the differential logic circuit, instead of the level shift circuit of diode type (See FIG. 3). In these level shift circuits, the resistances of the resistors r.sub.1, r.sub.2 and r.sub.3 and the current values I.sub.LS of the constant current sources 20.sub.1, 20.sub.2 and 20.sub.3 are so selected as to satisfy the following formula (1)
I.sub.LS .multidot.(r.sub.2 -r.sub.1)=I.sub.LS .multidot.(r.sub.3 -r.sub.2)=.phi.* (1)
Then, the potentials V.sub.IN2 and V.sub.IN2N applied to the bases of the transistors Q.sub.2 and Q.sub.2N of the intermediate stage logic circuit are level-shifted by .phi.* from the potentials V.sub.IN1 and V.sub.IN1N applied to the bases of the transistors Q.sub.1 and Q.sub.1N of the uppermost stage logic circuit; and the potentials V.sub.IN3 and V.sub.IN3N applied to the bases of the transistors Q.sub.3 and Q.sub.3N of the lowermost stage logic circuit are further level-shifted by .phi.* from the potentials V.sub.IN2 and V.sub.IN2N applied to the bases of the transistors Q.sub.2 and Q.sub.2N of the intermediate stage logic circuit.
Here, since the potentials V.sub.IN1 and V.sub.IN1N vary within a range from (-.delta.(=I.sub.LS .multidot.r.sub.1)) to (-v-.delta.), the potentials V.sub.IN2 and V.sub.IN2N vary within a range from (-.phi.*-.delta.) to (-.phi.*-v-.delta.), and the potentials V.sub.IN3 and V.sub.IN3N vary within a range from (-2.phi.*-.delta.) to (-2.phi.*-v-.delta.) (as shown in FIG. 6). As a result, the voltages V.sub.CEQ1, V.sub.CEQ2, and V.sub.CEQ3 applied to the uppermost, intermediate and lowermost differential transistors can be expressed, respectively as
V.sub.CEQ1 =2((.phi.+.delta.)/2-0.5 v)
V.sub.CEQ2 =.phi.*-0.5 v
V.sub.CEQ3 =.phi.*-0.5 v (2)
Therefore, it is possible to freely vary the operating points of the respective transistors by varying .phi.* and .delta. to a limit V.sub.CENS at which the transistor enters the saturation range.
When comparing the above formula (2) with the voltages V.sub.CE applied to the respective transistors of the conventional differential logic circuit as listed in Table 1, it can be understood that .phi.* corresponds to that obtained by reducing .phi. from the circuit standpoint.
Here, the conditions that the respective transistors of the differential stages will not enter the saturation range can be obtained as
.phi.-v+.delta..gtoreq.V.sub.CENS
.phi.*-0.5 v.gtoreq.V.sub.CENS
By substituting v=.phi./3 and V.sub.CENS =.phi./3 (explained under Description of Prior Art) into the above formula, the following formulae can be obtained
.delta..gtoreq.0
.phi.*.gtoreq.0.5 v (3)
On the other hand, since the potentials V.sub.IN3 and V.sub.IN3N inputted to the lowermost logic circuit decrease with increasing .phi.*, care must be taken so that the transistors T.sub.3 and T.sub.3N of the third level shift circuit do not saturate. The conditions that the transistors T.sub.3 and T.sub.3N of the third level shift circuit do not saturate are
(-2.phi.*-v-.delta.)-(-2.phi.).gtoreq.V.sub.CENS
Therefore,
.phi.*.ltoreq..phi.-)v+.delta.+V.sub.CENS)/2
By substituting v=.phi./3 and V.sub.CENS =.phi./3 into the above formula, the following formulae can be obtained
.phi.*.ltoreq.2.phi./3-.delta./2 (4)
The possible range of .phi.* can be obtained from the above formulae (3) and (4) as
0.5.phi..ltoreq..phi.*.ltoreq.2.phi./3-0.5.delta. (4')
As a result, .phi. can be reduced from 0.5 to 2/3 times from the circuit standpoint.
Here, the minimum operating voltage V.sub.EEmin of the first embodiment of the semiconductor integrated circuit shown in FIG. 5 can be calculated as follows:
.vertline.V.sub.EEmin .vertline.=2.phi.*+.phi.+0.5v+.delta.+V.sub.CSmin(5)
Therefore, according to the degree of reduction of .phi.,
.vertline.V.sub.EEmin .vertline..gtoreq..phi.*/2+0.5v 30 V.sub.CSmin =2.65 V
.vertline.V.sub.EEmin .vertline..gtoreq.2.phi.*/3+0.5v+V.sub.CSmin =2.95 V
That is, the operating voltage can be minimized as follows:
2.65 V.ltoreq.V.sub.EEmin .ltoreq.2.95 V
Further, FIG. 6 shows the typical potential levels at the respective nodes of the ECG circuit of the first embodiment shown in FIG. 5.
FIG. 7 shows a second embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit in this embodiment, is formed such that the resistance r.sub.1 of the first level shift circuit of the first embodiment shown in FIG. 5 is zeroed, and further the third level shift circuit is eliminated so that the input terminals IN3 and IN3N are directly connected to the bases of the lowermost stage differential transistors Q.sub.3 and Q.sub.3N of the ECG circuit.
Therefore, this second embodiment corresponds to the first embodiment of the semiconductor integrated circuit device, in which the p-n junction built-in potential .phi.* is reduced down to .phi.*=0.5.phi. and .delta.=0. FIG. 8 shows the typical potential levels at the respective nodes of the second embodiment shown in FIG. 7. The minimum operating voltage V.sub.EEmin of this second embodiment of the semiconductor integrated circuit device can be obtained in accordance with the formula (5) as follows:
.vertline.V.sub.EEmin .vertline.=2.phi.+0.5v+V.sub.CSmin
Therefore, it is possible to operate the three-stage series-gating differential logic circuit at the minimum voltage (about 2.65 V), which is the same as that of the conventional single-stage differential logic circuit (Table 2).
In general, in the case of the series-gating differential logic circuit, since the longest time needed is when the lowermost stage signal is propagated, when the external signal is directly inputted to the lowermost stage as with the case of this second embodiment, it is possible to reduce the delay time along the critical path (the path in a circuit which needs the longest time to propagate a signal).
FIG. 9 shows a third embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit in this embodiment, is formed such that the three-stage series-gating differential logic circuit of the second embodiment is reduced to the two-stage series-gating differential logic circuit, and further the second level shift circuit is eliminated so that the input terminals IN2 and IN2N are directly connected to the bases of the lowermost stage differential transistors Q.sub.2 and Q.sub.2N. FIG. 10 shows the typical potential levels at the respective nodes of the third embodiment shown in FIG. 9. The calculated minimum operating voltage V.sub.EEmin of the third embodiment is the same (about 2.65 V) as with the case of the second embodiment. This is because in the case of the reduction of .phi.*=0.5.phi., since the minimum operating voltage of the three-stage series-gating differential logic circuit is already equalized to that of the level shift circuit of the single-stage differential logic stage circuit as already shown in the second embodiment, even if the number of stages of the differential circuits is reduced down to two stages or less, it is impossible to further reduce the minimum operating voltage.
FIG. 11 shows a fourth embodiment of the semiconductor integrated circuit according to the present invention. In this embodiment, the gist of the present invention is applied to the single ended three-stage series-gating ECL (Emitter Coupled Logic) circuit; that is, the semiconductor integrated circuit of FIG. 11 is formed such that the first to third level shift circuits of the first embodiment of the semiconductor integrated circuit device shown in FIG. 5 are replaced with single ended circuits. In more detail, in the i-th (i=1, 2 and 3) level shift circuit, a predetermined potential V.sub.BB1 is applied to the base of the differential transistor T.sub.iN, without being connected to the input terminal INiN. The potential V.sub.BB1 is an intermediate value from (-.phi.) to (-.phi.-2v) of the amplitude of the potential applied to the input terminal INi (i=1, 2 and 3). Further, in this fourth embodiment of the differential logic circuit, the product of the resistor R.sub.L1 (or R.sub.L2) and the current flowing through the constant current source circuit 8 are two twice larger than in the first embodiment. Therefore, the amplitude (2v) of the output V.sub.0 of the differential logic circuit becomes two times larger than the amplitude (v) of the first embodiment, so that the voltage V.sub.CEQ1 applied to the uppermost stage transistors Q.sub.1 and Q.sub.1N of the differential logic circuit is compressed, as compared with the case of the first embodiment, as follows:
V.sub.CEQ1 =.phi.-2v-.delta.
Therefore, the following formula must be satisfied in order that the transistors Q.sub.1 and Q.sub.1N may not be saturated:
.phi.-2v+.delta..gtoreq.V.sub.CENS
When this formula is calculated by use of v=.phi./3 and V.sub.CENS .gtoreq..phi./3,
.delta..gtoreq.0
can be obtained, so that the formula (3) can be established as it is.
Further, in the fourth embodiment, since the level shift circuit is changed from the differential type to the single ended type, as understood by Table 2, the operating supply voltage of the level shift circuit itself increases from (2.phi.+0.5 v+V.sub.CSmin) to (2.phi.+v+V.sub.CSmin). As a result, the absolute value of the minimum operating supply voltage V.sub.EEmin of the semiconductor integrated circuit device is the larger value of either of (2.phi.+v+V.sub.CSmin) and (2.phi.*+.phi.+0.5 v+.delta.+V.sub.CSmin). FIG. 12 shows the typical potential levels at the respective nodes of the fourth embodiment shown in FIG. 11.
FIG. 13 shows a fifth embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit of FIG. 13 is formed such that .phi. is reduced down to .phi.*=0.5.phi.(=0.45 V); .delta.=0; and r.sub.1 =0 in the fourth embodiment shown in FIG. 11. For the same reason as with the case of the differential type (as explained in the second embodiment), the third level shift circuit is not needed so that the input signals are directly inputted to the base of the differential transistors Q.sub.3 and Q.sub.3N of the lowermost stage logic circuit.
The absolute value of the minimum operating voltage V.sub.EEmin of this fifth embodiment of the semiconductor integrated circuit device can be obtained in accordance with the formula (6) as follows:
.vertline.V.sub.EEmin .vertline.=2.phi.+v+V.sub.CSmin =2.8 V
Therefore, it is possible to operate the three-stage series-gating differential logic circuit at the minimum voltage (about 2.8 V) which is the same as with the case of the conventional single-stage differential logic circuit. FIG. 14 shows the typical potential levels at the respective nodes of the fifth embodiment shown in FIG. 13.
Further, in this fifth embodiment, since the input signals are directly inputted to the transistors of the lowermost stage single ended type logic circuit, it is possible to shorten the delay time through the critical path, as compared with the case of the fourth embodiment.
FIG. 15 shows a sixth embodiment of the semiconductor integrated circuit according to the present invention. This embodiment is a two-stage series-gating single ended ECG circuit operative by the same supply voltage as with the case of the fifth embodiment of the semiconductor integrated circuit device. The semiconductor integrated circuit of FIG. 15 is formed such that the lowermost stage single ended logic circuit and the second level shift circuit of the fifth embodiment are eliminated and further the resistance r.sub.1 (=.phi./3I.sub.LS) is connected to the first level shift circuit. FIG. 16 shows the typical potential levels at the respective nodes of the sixth embodiment shown in FIG. 15.
Further, in the above-mentioned embodiments, the case where the .phi.* is reduced down to 0.5.phi. and .delta.=0 has been explained by way of example. The values are not meant to be limited only thereto; it is of course possible to select various values of .phi.* and .delta..
FIG. 17 shows a seventh embodiment of the semiconductor integrated circuit according to the present invention. FIG. 18 shows the typical potential levels at the respective nodes of the seventh embodiment shown in FIG. 17. The semiconductor integrated circuit in this embodiment is formed such that the respective stages of the logic circuits of the fourth embodiment of the semiconductor integrated circuit device shown in FIG. 11 are changed from the differential type to the single ended type. In more detail, in the i-th (i=1, 2 and 3) level shift circuit, the single ended signal of large amplitude is outputted as it is, without being converted into a differential signal. Therefore, the potential level of the third (lowermost) level shift circuit can be lowered, so that the transistor of the third level shift circuit is saturated. Therefore, the output of the third level shift circuit is formed by an emitter follower of a transistor T.sub.4 to reduce the output level by .phi., before the output signal thereof is transmitted to the base of the transistor Q.sub.3 of the lowermost stage logic circuit.
Further, in this seventh embodiment, when r.sub.1, r.sub.2, r.sub.3 and I.sub.LS are so selected that the following formula can be established
I.sub.LS .multidot.(r.sub.2 -r.sub.1)=I.sub.LS .multidot.(r.sub.3 -r.sub.2)+.phi.=.phi.* (7)
the signals whose levels are shifted by .phi.* are inputted to the respective differential stage transistors. As a result, the voltages V.sub.CE applied to the respective stage transistors Q.sub.1, Q.sub.2, Q.sub.3 or Q.sub.1N, Q.sub.2N, Q.sub.3N are
V.sub.CEQ1 =2((.phi.+.delta.)/2-v),
where
.delta.=I.sub.LS .multidot.r.sub.1
V.sub.CEQ2 =.phi.*-v
V.sub.CEQ3 =.phi.*-v (8)
Therefore, it is possible to freely determine the operating point of each transistor by varying .phi.* and .delta. until the transistor reaches a limit of the saturation range. In comparison with the formula (8) with the voltage V.sub.CE applied to the respective transistors in the conventional ECG shown in Table 1, it is understood that .phi.* corresponds to a reduced .phi. from the circuit standpoint.
Here, the conditions that the respective differential stage transistors will not enter the saturation range can be obtained as
.phi.+.delta.-2v.gtoreq.V.sub.CENS
.phi.*-v.gtoreq.V.sub.CENS
Further, when calculated on the assumption that v=.phi./3 and V.sub.CENS =3/.phi.,
.delta..gtoreq.0
.phi.*.gtoreq.2.phi./3 (9)
On the other hand, the conditions that the third level shift circuit will not be saturated can be obtained as
{(-2.phi.*-2v-.delta.)+.phi.}-(-2.phi.).gtoreq.V.sub.CENS
Therefore,
.phi.*.ltoreq.3.phi./2-(2v+.delta.+V.sub.CENS)/2
Further, when calculated on the assumption that v=.phi./3 and V.sub.CENS =3/.phi.,
.phi.*.ltoreq..phi.-.delta./2 (10)
Further, the conditions that the second (intermediate) level shift circuit will not be saturated can be obtained as
(-.phi.*-2v-.delta.)-(-2.phi.).gtoreq.V.sub.CENS
Therefore,
.phi.*.ltoreq.2.phi.-(2v+.delta.+V.sub.CENS)
Further, when calculated on the assumption that v=.phi./3 and V.sub.CENS =3/.phi.,
.phi.*.ltoreq..phi.-.delta. (11)
Further, the allowable range of .phi.* according to the formulae (9), (10) and (11) is
2.phi./3.ltoreq..phi.*.ltoreq..phi.-.delta. (12)
so that it is possible to reduce .phi. one to 2/3 times from the circuit standpoint.
Here, the minimum operating voltage V.sub.EEmin of the ECG circuit of the seventh embodiment can be calculates as
.vertline.V.sub.EEmin .vertline.=2.phi.*+.phi.+v+.delta.+V.sub.CSmin(13)
Therefore, it is possible to reduce the voltage according to the reduction rate of .phi. as
7.phi./3+v+V.sub.CSmin .ltoreq..vertline.V.sub.EEmin .vertline..ltoreq.3.phi.*+v+V.sub.CSmin
That is, the voltage can be reduced down to a range from 3.1 to 3.7 V.
Further, in the seventh embodiment, a predetermined reference voltage V*.sub.BBi is applied to the base of the transistor Q.sub.iN of the i-th stage logic circuit of the differential logic circuit. Further, this reference voltage V*.sub.BBi is determined so as to become an intermediate value of the amplitude of the potential V.sub.1Ni applied to the base of a pair of the differential transistors Q.sub.i of a pair of the transistors Q.sub.i and Q.sub.iN.
These reference potentials V*.sub.BB1, V*.sub.BB2 and V*.sub.BB3 can be respectively generated by the circuits as shown in FIGS. 19A, 19B and 19C, for instance. In the reference potential generating circuit shown in FIG. 19A, one end of a resistor r.sub.11 is grounded; the other end of this resistor r.sub.11 is connected to one end of a pair of parallel-connected resistors R.sub.13 and R.sub.14 ; the other end of this parallel circuit is connected to a supply voltage via a constant current source 20.sub.5. Further, an output reference voltage V*.sub.BB1 is taken out of the other end of the parallel circuit.
In the reference potential generating circuit shown in FIG. 19B, one end of a resistor r.sub.21 is grounded; the other end of this resistor r.sub.21 is connected to one end of a pair of parallel-connected resistors R.sub.23 and R.sub.24 ; the other end of this parallel circuit is connected to a supply voltage via a constant current source 20.sub.6. Further, an output reference voltage V*.sub.BB2 is taken out of the other end of the parallel circuit.
Further, in the reference potential generating circuit shown in FIG. 19C, an emitter follower of a transistor T.sub.5 is additionally connected to the circuit shown in FIG. 19A or 19B, in order to further shift the output of the parallel circuit by .phi. to output an output reference voltage V*.sub.BB3.
FIG. 20 shows an eighth embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit in this embodiment is formed such that .phi. is reduced down to .phi.*=2.phi./3 (=0.6 V); .delta.=0; r.sub.1 =0; r.sub.2 =2.phi./3I.sub.LS ; and r.sub.3 =.phi./3I.sub.LS in the seventh embodiment shown in FIG. 17. FIG. 21 shows the typical potential levels at the respective nodes of the eighth embodiment shown in FIG. 20. The absolute value of the minimum operating voltage V.sub.EEmin of this eighth embodiment of the semiconductor integrated circuit device can be obtained in accordance with the formula (13) as follows:
.vertline.V.sub.EEmin .vertline.=7.phi./3+v+V.sub.CSmin =3.1 V
Therefore, it is possible to operate the three-stage series-gating single ended ECL circuit at the minimum supply voltage (about 3.1 V), which is roughly an intermediate value of the supply voltages of the conventional two-stage series-gating ECL circuit and the conventional single-stage series-gating ECL circuit.
FIG. 22 shows a ninth embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit in this embodiment is formed such that the three-stage circuit is reduced to the two-stage circuit; the second and third level shift circuits are eliminated; and a resistor r.sub.1 (=.phi./6I.sub.LS) is added to the first level shift circuit in the eighth embodiment shown in FIG. 20. FIG. 23 shows the typical potential levels at the respective nodes of the ninth embodiment shown in FIG. 22. The absolute value of the minimum operating voltage V.sub.EEmin of this ninth embodiment of the semiconductor integrated circuit device is the higher value of either of (2.phi.+v+V.sub.CSmin) and (.phi.*+.phi.+v+.delta.+V.sub.CSmin), because this voltage cannot be reduced lower than the minimum operating voltage of the single-stage level shift circuit (Table 2).
Now, if .phi.*.ltoreq..phi.-.delta., the minimum operating voltage V.sub.EEmin can be expressed as
.vertline.V.sub.EEmin .vertline.=2.phi.+v+V.sub.CSmin (14)
Therefore, the reduction of (2.phi./3.ltoreq..phi.*.ltoreq..phi.-.delta.) does not contributes to the reduction of the voltage .vertline.V.sub.EEmin .vertline., but contributes to only a reduction of voltage by increasing the level of V.sub.1n1.
In the ninth embodiment, it is possible to operate the two-stage series-gating single ended ECG circuit at the minimum supply voltage (about 2.8 V), which is the same as with the case of the conventional single-stage single ended ECG circuit.
FIG. 24 shows a tenth embodiment of the semiconductor integrated circuit according to the present invention. In this embodiment of the semiconductor integrated circuit device, a plurality (two in FIG. 24) of differential logic circuits (referred to as differential stages) are connected in cascade. Further, a resistor r.sub.0 is connected to the differential stage, except that the final-stage differential circuit is directly connected to an emitter follower output circuit 10, so that the input levels of the respective differential stages can be equalized to the input signal level of the uppermost differential stage.
FIGS. 25A to 25F show an eleventh embodiment of the semiconductor integrated circuit according to the present invention. In this embodiment, as shown in FIG. 25A, a four-input multiplexer is formed by a three-stage series-grating differential ECL circuit. This four-input multiplexer selects one of four input signals A0, A1, A2 and A3 on the basis of two select control signals S0 and S1 (inversion signals of S0N and S1N). Further, the four input signals A0, A1, A2 and A3 are all level-shifted to signals A0I, A1I, A2I and A3I by four level shift circuits as shown in FIGS. 25B, 25C, 25D and 25E, respectively. Further, the select control signal S0 is also level-shifted to a signal S0I by a level shift circuit as shown in FIG. 25F.
FIGS. 26A to 26F show a twelfth embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit in this embodiment is formed such that the level shift circuits for level-shifting the four input signals A0, A1, A2 and A3 and the select control signal S0 of the embodiment shown in FIG. 25A are changed from the differential type to the single ended type, respectively. In addition, the logic circuit for inputting the select control signal S1 is changed from the differential type to the single ended type.
FIGS. 27A to 27E show a thirteenth embodiment of the semiconductor integrated circuit according to the present invention. In this embodiment, as shown in FIG. 27A, a four-input multiplexer is formed by a two-stage series-gating single ended ECL circuit.
FIGS. 28A to 28G show a fourteenth embodiment of the semiconductor integrated circuit according to the present invention. In the circuit device of this embodiment, as shown in FIG. 28A, an adder is formed by a three-stage series-gating differential ECL circuit. The adder adds two input signals A and B and a carry input signal CIN. The input signal B and the carry input signal CIN are level-shifted to signals B1 and CIN1 by two level shift circuits as shown in FIGS. 28B and 28C, respectively. These level-shifted signals are inputted to the adder as shown in FIG. 28A. The adder outputs an addition signal S1 and an inversion signal S1N thereof and a carry signal COUT1 (indicative of the presence or absence of a carry) and an inversion signal COUTN1 thereof, as an addition result. These signals are transmitted to four emitter follower output circuits as shown in FIGS. 28D, 28E, 28F and 28G, respectively. These output circuits output the output signals S, SN, COUT and COUTN, respectively.
FIGS. 29A to 29E show a fifteenth embodiment of the semiconductor integrated circuit according to the present invention. The semiconductor integrated circuit in this embodiment is formed such that the level shift circuits of the adder as shown in FIG. 28A are changed from the differential type as shown in FIGS. 28B and 28C to the single ended type as shown in FIGS. 29B and 29C, respectively. Further, the semiconductor integrated circuit in this embodiment is formed such that the logic circuit of FIG. 28A for inputting the input signal A is changed from the differential type to the single ended type. The adder outputs an addition signal S1 and a carry single COUT1 to the emitter follower output circuits as shown in FIGS. 29D and 29E. These output circuits output the output signals S1 and COUT1, respectively.
FIGS. 30A and 30B show a sixteenth embodiment of the semiconductor integrated circuit according to the present invention. In this embodiment, as shown in FIG. 30A, an adder is formed by a two-stage series-gating single ended ECG circuit.
In the first to sixteenth embodiments, the current sources 8, 8.sub.1 and 8.sub.2, 15, 15.sub.1 to 15.sub.4 and 20.sub.0 to 20.sub.4 are not necessarily constant current sources. The current sources may be a conventional current source circuit (not constant) or a resistor.
Here, the minimum operating voltage, the operating speed and the power consumption of the four-input multiplexer of the eleventh and thirteenth embodiments as shown in FIGS. 25A to 25F and 27A to 27E have been calculated by the circuit simulator SPICE (made at the university of California, Berkeley), and listed in Tables 3, 4 and 5 below, in comparison with the prior art four-input multiplexer.
TABLE 3______________________________________(Minimum operating voltage .backslash.V.sub.EEmin .backslash.) INVENTION PRIOR ART______________________________________3-STAGE SER-GATE DIFF 2.5V 4.2V2-STAGE SER-GATE SIN ENDED 2.8V 3.6V______________________________________
TABLE 4______________________________________(Operating speed) INVENTION PRIOR ART______________________________________3-STAGE SER A0 .fwdarw. 210 ps / 250 ps 150 ps / 180 psGATE DIFF Y S0 .fwdarw. 260 ps / 300 ps 200 ps / 240 ps Y S1 .fwdarw. 210 ps / 260 ps 240 ps / 290 ps Y2-STAGE SER A0 .fwdarw. 390 ps / 460 ps 290 ps / 350 psGATE YSINGLE S0 .fwdarw. 330 ps / 410 ps 350 ps / 400 psENDED Y S1 .fwdarw. 230 ps / 290 ps 230 ps / 290 ps Y______________________________________ V.sub.EE = $V.sub.EEmin $; C.sub.L = 200 p; I.sub.CS = I.sub.EF = 280 .mu.A
TABLE 5______________________________________(Minimum power consumption) INVENTION PRIOR ART______________________________________3-STAGE DIFF 5.7 mW / gate 8.4 mW /gate2-STAGE SINGLE ENDED 6.4 mW / gate 8.2 mW /gate______________________________________
Further, the Item (A0.fwdarw.Y) in Table 4 indicates that the time from when the input signal A0 is changed from "L" to "H" to when the changed input signal A0 is outputted to the output terminal Y is 210 ps (picoseconds) in the case of the invention and 150 ps in the case of the prior art, and the time from when the input signal A0 is changed from "H" to "L" to when the changed input signal A0 is outputted to the output terminal Y is 250 ps in the case of the invention and 180 ps in the case of the prior art, on condition that the select control signals S0 and S1 are kept constant and further the input terminal for inputting the input signal A0 is connected to the output terminal Y of the multiplexer.
Further, the Item (S0.fwdarw.Y) in Table 4 indicates that the time from when the select control signal S0 is changed from "L" to "H" to when the influence thereof is outputted to the output terminal Y is 260 ps in the case of the invention and 200 ps in the case of the prior art, and the time from when the control signal S0 is changed from "H" to "L" to when the influence thereof is outputted to the output terminal Y is 300 ps in the case of the invention and 240 ps in the case of the prior art, on condition that the select control signal S1 is kept constant and further the output terminal Y of the multiplexer is switched from the input signal A0 to the input signal A1, for instance when the select control signal SO is switched from "L" to "H". Further, the same is applied to the Item S1.fwdarw.Y.
Table 4 indicates that although the operating speed of the present invention is lower than that of the prior art, the difference between (L.fwdarw.H) and (H.fwdarw.L) in the delay time of the critical path of the invention is smaller than that of the prior art, as listed in Table 6 below.
TABLE 6______________________________________ INVENTION PRIOR ART______________________________________3-STAGE DIFF 260 ps / 300 ps 240 ps / 290 ps2-STAGE SINGLE ENDED 390 ps / 460 ps 350 ps / 400 ps______________________________________
Further, on the other hand, Tables 3 and 5 indicate that the operating supply voltage can be reduced markedly and further the power consumption can be also suppressed. Further, since the operating voltage can be reduced down to 3.3 V or 2.5 V, it is possible to form the ECG circuit on the same board or the same chip on which microminiaturized CMOSs are formed, so as to be operative under a single supply voltage.
In summary, in the semiconductor integrated circuit device according to the present invention, it is possible to form the semiconductor integrated circuit device operative on a lower supply voltage, without significantly degrading the functions and performance thereof.
On the contrary, if the operating voltage of the prior art, such as 4.2 V is in use, in the semiconductor integrated circuit device according to the present invention, it is possible to form the semiconductor integrated circuit device with more stages. This can be understood from Table 3.

Number	Name	Date
4516039	Matsuzaki et al.	May 1985
4647799	Hsu et al.	Mar 1987
4737663	Varadarajan	Apr 1988
4737664	Wilheim	Apr 1988
4751404	Yuen	Jun 1988
4857771	Ovens et al.	Aug 1989
4868423	Abdi	Sep 1989
5113095	Huehne	May 1992
5250860	Chu	Oct 1993
5293083	Askin et al.	Mar 1994

Low voltage bipolar transistor logic circuit

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