Low voltage, closed loop controlled energy storage circuit

Information

  • Patent Grant
  • 9602009
  • Patent Number
    9,602,009
  • Date Filed
    Tuesday, December 8, 2015
    8 years ago
  • Date Issued
    Tuesday, March 21, 2017
    7 years ago
Abstract
An energy storage circuit for use with a power converter includes a base capacitor coupled between an input bus and a ground potential, and an adjust capacitor. A switching device is coupled in series with the adjust capacitor between the input bus and the ground potential. A voltage regulator coupled between a control terminal of the switching device and ground. The voltage regulator has an input coupled to the second internal node, wherein when the power switch is turned on a signal at the second internal node is representative of a fluctuating input voltage. The voltage regulator is activated when the fluctuating input voltage is in a crest region, thereby turning the switching device off and disengaging the adjust capacitor. The voltage regulator is deactivated when the fluctuating input voltage is in a valley region, thereby turning the switching device on and engaging the adjust capacitor.
Description
TECHNICAL FIELD

The present invention relates generally to energy storage circuits; more specifically, to circuits that utilize capacitors for storing energy in a power supply converter.


BACKGROUND

Many known AC-to-DC power converter circuits, also commonly referred to as switch mode power supplies, typically have three principal sections that perform distinct functions: input rectification, voltage reservoir (i.e., energy storage), and DC-to-DC conversion. The circuitry that performs input rectification changes the bidirectional input voltage from an AC line into rectified input voltage with current that flows only in one direction. Voltage reservoir circuitry is typically utilized to smooth out voltage fluctuations, also known as ripple voltage, of the rectified input voltage. The voltage reservoir circuitry provides a low ripple DC voltage to the input of the DC-to-DC conversion circuitry. DC-to-DC conversion is typically required to deliver a suitable output voltage needed to power electronic devices.


The energy storage function is typically performed by one or more capacitors coupled across the rectifier bridge. These capacitors are commonly referred to as a bulk capacitance. The bulk capacitance is charged by the rectified input current, thereby storing energy in the form of a voltage. The voltage on the bulk capacitance is typically too large and fluctuating to power the delicate circuitry of electronic equipment. Therefore, a DC-to-DC conversion circuit is utilized to convert the voltage across the bulk capacitance into a stable, low output voltage capable of powering electronic devices with high efficiency.


The rectified voltage on the bulk capacitance typically has a ripple that varies between a crest value and a valley value at a frequency that in a full bridge rectification is double the AC line frequency (e.g., 120 Hz). The crest value is defined by the peak voltage of the AC input voltage. The valley value is determined by the discharge rate of the bulk capacitor which is a function of the capacitance value and the amount of power demanded by the DC-to-DC converter. The ripple voltage amplitude is the difference between the crest and valley voltage levels. Persons of skill in the art understand that the DC-to-DC power converter needs a minimum rectified voltage at its input to produce the desired output power. Consequently, the ripple voltage amplitude should not exceed a certain value at the minimum AC input voltage specified for the power supply.


A power supply is typically required to provide its normally regulated output voltage for a short time (frequently referred to as the holdup time) after the AC input line voltage is removed. During the holdup time, the voltage input to the DC-to-DC power converter is provided entirely by the stored energy in the bulk capacitance, which is proportional to the bulk capacitance value and the square of the voltage on the bulk capacitance.


The individual capacitors that make up the bulk capacitance are typically selected to meet several requirements that are influenced by the intended use of the power supply. The physical size of the power supply is influenced by the value and the voltage rating (the maximum voltage that an individual capacitor can reliably withstand) of the capacitors that constitute the bulk capacitance. The cost of the bulk capacitance is also a significant part of the total cost of the power supply. For a given value of capacitance, a higher voltage rating translates to higher cost. The voltage rating is selected for reliable operation at the maximum AC input voltage of the power supply, whereas the capacitance of the individual capacitors is selected based on the minimum specified AC input voltage of the power supply.


The total bulk capacitance value is typically selected to ensure that the minimum input voltage required for proper DC-to-DC conversion is not reached when the power supply is operating with the minimum specified AC input line voltage. Typically, AC-to-DC power supplies are designed to operate from a wide range of AC input line voltages, e.g., between 85 volts AC and 265 volts AC. Consequently, the bulk capacitance usually includes a physically large capacitor, which provides a high capacitance value required by the minimum AC input voltage requirement of the DC-to-DC power convertor, as well having a high voltage rating (e.g., 400 V) that exceeds the rectified maximum AC input line voltage.





BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.



FIG. 1 is a circuit block diagram of an example switch mode power supply that includes a closed loop, low voltage controlled energy storage circuit.



FIG. 2 is a circuit schematic diagram of the switch mode power supply of FIG. 1 showing details of an example closed loop, low voltage controlled energy storage circuit.



FIG. 3 is a detailed circuit schematic diagram of another example switch mode power supply with a closed loop, low voltage controlled energy storage circuit.





Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings are not necessarily drawn to scale.


DETAILED DESCRIPTION

In the following description numerous specific details are set forth, such as device types, voltages, component values, configurations, etc., in order to provide a thorough understanding of the embodiments described. However, persons having ordinary skill in the relevant arts will appreciate that these specific details may not be needed to practice the embodiments described. It is further appreciated that well known circuit structures and elements have not been described in detail, or have been shown in block diagram form, in order to avoid obscuring the embodiments described.


Reference throughout this specification to “one embodiment”, “an embodiment”, “one example” or “an example” means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment”, “in an embodiment”, “one example” or “an example” in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures or characteristics may be combined in any suitable combinations and/or sub-combinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a combinational logic circuit, or other suitable components that provide the described functionality.


In the context of the present application, when a transistor is in an “off state” or “off” the transistor does not substantially conduct current. Conversely, when a transistor is in an “on state” or “on” the transistor is able to substantially conduct current. By way of example, in one embodiment, a transistor comprises an N-channel metal-oxide-semiconductor field-effect transistor (NMOS) with a voltage being supported between the first terminal, a drain, and the second terminal, a source. The MOSFET comprises a switch that is driven by a control circuit. For purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of an electronic circuit or Integrated circuit (IC) are defined or measured.


The present disclosure is directed to the use of capacitors to store energy in AC-to-DC power supplies. In particular, a closed loop voltage reservoir (energy storage) circuit is provided that offers lower cost and reduced physical volume of the bulk capacitor utilized as the voltage reservoir. In one embodiment, the energy storage circuit allows a power supply to operate across a specified range of AC input line voltage with increased efficiency. The energy storage circuit is controlled by a signal extracted from a low voltage source generated in a DC-to-DC power converter responsive to fluctuations in the rectified AC input line voltage. As a result of auto adjustment, the capacitance of the energy storage circuit is dynamically increased around the valley region of the rectified AC input line voltage, and dynamically reduced around the crest region of the rectified AC input line voltage. In one implementation, the control signal for the closed loop adjustment of the energy storage circuit is generated in a manner that eliminates power loss ordinarily associated with a sense voltage divider, thereby increasing the overall efficiency and decreasing no-load input power of the power supply.



FIG. 1 shows an example switch mode power supply 100 that includes a full bridge rectifier 110 comprising four diodes that convert an externally-generated ac bidirectional sinusoidal input line voltage VAC 105 into a fully rectified unidirectional voltage. The fully rectified unidirectional voltage coupled across a voltage reservoir unit (closed loop, low voltage controlled energy storage circuit), hereafter referred as “energy storage circuit” 120, generates a low fluctuation (substantially smooth) DC voltage VIN 115, which is presented by the symbolic waveform 116. In one example, the ac input voltage may be an ordinary ac line voltage (e.g., 85V-265V between 50-60 Hz). The DC voltage VIN 115 is provided at the input of the DC-to-DC power converter 170. The DC-to-DC power converter 170 could be of any known topology that regulates the input voltage VIN 115 to a desired DC output voltage level, VOUT 180 applied to a load 185.


Energy storage circuit 120 functions as a compensating filter in response to input voltage fluctuations of the fully rectified waveform signal. That is, in the absence of energy storage circuit 120, a fully rectified sinusoidal waveform of 112 is generated by bridge circuit 110. The instantaneous values of a fully rectified sinusoidal waveform shows dramatic fluctuations between a peak voltage value 112A and the zero reference potential 112B. Energy storage circuit 120 produces a DC voltage with small fluctuations during steady state operation. Depending on the bulk capacitance value of energy storage circuit 120, and the peak voltage value 112A of the line voltage, DC voltage VIN 115 may fluctuate between a crest voltage value 116A and a valley voltage value 116B. The crest and valley values define the amplitude of the ripple (e.g., 120 Hz frequency) of voltage VIN 115 input to DC-to-DC power converter 170.



FIG. 2 is a circuit schematic diagram of a switch mode power supply 200 coupled to receive an externally-provided AC supply line voltage VAC 205 at a pair input terminals of a rectifier bridge 210. Rectification produces a voltage VIN 215 across an energy storage circuit 220. Voltage VIN 215 is also input to DC-to-DC power converter 270. As shown, energy storage circuit 220 includes a base capacitor Cbase 225 having a capacitance value and voltage rating selected for reliable operation at the maximum AC input voltage of the power supply.


Energy storage circuit 220 is also shown including an adjust capacitor Cadjust 230 coupled in parallel with Cbase 225 through a series switching device S1235. When switching device S1235 is closed, Cbase 225 is connected in parallel with Cadjust 230 between ground 218 and the positive input node of DC-to-DC power converter 270. The diode D1236, which is shown coupled between ground 218 and the cathode of Cadjust 230, allows current to flow through capacitor Cadjust 230 in one direction only (unidirectional current through switching device S1335) and cannot charge when switching device S1235 is open. However, it can discharge when the switching device S1335 is either open or closed. Switching device S1235 is closed for a limited duration in each half line cycle around the valley region of the line cycle when the rectified input voltage has dropped below a predefined threshold value.


As configured in the example of FIG. 2, capacitor Cbase 225 receives a charging current from rectifier bridge 210 at all times during normal operation. Cadjust 230 only receives charging current from rectifier bridge 210 when switching device S1235 is closed. In one implementation, capacitor Cadjust 230 is a low voltage capacitor having a relatively large capacitance to keep the valley of voltage VIN 215 from dropping below a minimum desired value. Capacitor Cbase 225, on the other hand, is a high voltage capacitor (i.e., high voltage rating) having a relatively small capacitance. In one embodiment, a capacitance ratio of Cadjust 230 to a Cbase 225 is greater than 2:1.


In the embodiment of FIG. 2, switching device S1235 is controlled in a closed loop manner through control circuit 240. Control circuit 240 is driven by a low voltage (LV) control signal 265 from an internal supply in DC-to-DC power converter 270 in response to fluctuations in the input voltage VIN 215, as shown by waveform 216. DC-to-DC power converter 270 receives the input voltage VIN 215 and generates the regulated DC voltage VOUT 280 having a desired voltage level and low amplitude of the low frequency ripple at the output across the load 285.



FIG. 3 is a detailed circuit schematic diagram of another example switch mode power supply 300 with a closed loop, low voltage controlled energy storage circuit 320. Power supply 300 also includes a DC-to-DC converter 370, which, in this example, is shown as a flyback converter with a low voltage bias winding 373 that is utilized to generate a low voltage DC supply VBIAS 365 coupled to control circuit 340. It is appreciated that other DC-to-DC converter topologies may be utilized to provide a low voltage supply in response to the input line voltage instantaneous value going below a predefined threshold.


Power supply 300 further includes a rectifier bridge 310 that receives AC supply voltage VAC 305 and generates, rectified input voltage VIN 315 therefrom. Rectified input voltage VIN 315 is provided to energy storage circuit 320. Energy storage circuit 320 includes a base high voltage capacitor Cbase 325 that may define a minimum required value for the holding time of the power supply. Capacitor Cbase 325 is coupled to receive charging current from rectifier bridge 310. Low voltage adjust capacitor Cadjust 330 is selectively coupled in parallel with Cbase 325 through a series switching device S1335 during the valley region in each half line cycle when the rectified input voltage has dropped below a predefined threshold value. Diode D1336 allows unidirectional current across switching device S1335. Hence, the low voltage capacitance Cadjust 330 cannot charge when the switching device S1335 is open, although it can discharge when the switching device S1335 is either open or closed.


In the example shown, switching device S1335 comprises an n-channel MOSFET having gate, source, and drain terminals. As shown, the gate of S1335 is coupled to resistors 342 and 366, the drain is coupled to the cathode of diode D1336 and to negative terminal of Cadjust 330, and the source connected to anode of diode D1336 and to ground 318.


In one embodiment the closed loop control signal 341 for the series switching device S1335 is provided through a low voltage DC supply VBIAS 365 and is controlled through a control circuit 340. In one implementation, control signal 341 is generated through the low voltage supply of DC bias VBIAS 365 through a voltage divider formed by resistors 366 and 342, which are commonly connected to the gate of MOSFET S1335. A voltage regulator 345 is shown connected between the gate of S1335 and ground 318. The signal 341 input to the gate of S1335 is controlled in closed loop by control circuit 340, which, in the example shown, generates a voltage control signal Vcont 344 through a bias winding on transformer 375 of the DC-to-DC power converter 370.


In the embodiment of FIG. 3, DC-to-DC power converter 370 is shown as a flyback power converter; however, persons of skill in the art will appreciate that the power supply disclosed herein may utilize any other topology of DC-to-DC power converter, such as boost, forward, or other power converter topologies that provide an internal low voltage supply for control circuit 340.


As shown, DC-to-DC power converter 370 includes an isolation transformer 375 with a primary winding NP 371 coupled to the input bus having a voltage VBUS 319, which in a flyback converter configuration may, be the same as input voltage VIN 315. A power switch 350, which is shown coupled in series with primary winding 371, controls the transfer of energy from primary/input circuit to the output of power converter VOUT 385 and to the load 380 through the secondary winding NS 372 and the output circuitry 382.


An auxiliary/bias winding NB 373 on the core of isolation transformer 375 is coupled through a rectified diode 362 and a bulk bias capacitor 364 that generates a low voltage DC VBIAS 365 that may be utilized through an RC noise filter circuit (i.e., R 355 and C 354) to enable a switch controller 356. It is appreciated that switch controller 356 may receive multiple signals (not shown) to generate a switching signal to turn on/off power switch 350 of DC-to-DC power converter 370. In addition to providing the switching signal for power switch 350, the low voltage DC VBIAS 365 may also be utilized to generate control signal 341 that controls switching device S1335. When switching device S1335 is turned on, capacitor Cadjust 330 is coupled in parallel with capacitor Cbase 325 for an efficient and local compensation of the voltage drop in each half line cycle only during the valley region of the rectified AC line voltage 305.


Practitioners in the art understand that when power switch 350 is turned on (i.e., conducting) current flows through primary winding 371. Due to the reverse winding direction of secondary winding 372 and the reverse bias of the output rectifier 382 no current/energy is transferred through output circuitry 383 to load 380. In this mode of operation load current is supplied through the output bulk capacitor 384.


It is appreciated that the fluctuating input voltage VIN 315 may be sensed through the AC induced voltage in auxiliary/bias winding 373 at node 374. When the power switch 350 is turned on (i.e., on-state) the current induced in auxiliary/bias winding 373 represents the instantaneous value of the input voltage VIN 315. During the time that power switch 350 is on, current flowing through auxiliary/bias winding 373 does not charge bias capacitor 364 due to the reverse direction of bias rectifier 362. Hence, bias current is conducted from node 374 through diode rectifier Dx 348 of control circuit 340. The signal at node 374 is representative of the fluctuating input voltage VIN 315 (symbolic waveform 316), which voltage charges capacitor Cx 347, and through the resistive divider formed by resistors R1343 and R2346 generates a control, signal on the control terminal Vcont 344 of voltage regulator 345. In one embodiment, voltage regulator 345 is a three terminal shunt regulator (e.g., a TL431 regulator) utilized to turn on/off switching device S1335, thereby engaging and disengaging capacitor Cadjust 330 in energy storage circuit 320.


In operation, when power switch 350 turns off, the energy stored in the primary winding 371 transferred through the output rectifier 382 to output VOUT 385 and load 380. At the same time, the reversed direction of current in the bias winding 373 conducts current through the bias rectifier 382 to charge bulk bias capacitor 364, thereby generating DC bias voltage Vbias 365. DC bias voltage Vbias 365 provides supply for the switch controller 356 through RC noise filter R 355 and C 354 to generate the control signal (gating signal) for power switch 350. DC bias voltage Vbias 365 is also applied through resistor 366 to provide a regulated control/gating signal 341 for switching device S1 (e.g., MOSFET) 335. When MOSFET 335 is conducting, capacitor Cadjust 330 is engaged in energy storage circuit 320.


Persons of skill in the art will appreciate that the dashed capacitor 337 symbolizes the Miller capacitance between drain and gate of MOSFET 335. Resistor 342 provides a discharge path for the total gate capacitance of MOSFET 335. Note that diode D1336 coupled across switching device S1335 is also coupled to Cadjust 330 (low voltage capacitance) and to Cbase 325 (high voltage capacitance) through the common input return (ground) 318. Diode D1336 allows current to pass only in one direction when switching device S1335 is open. Hence, low voltage capacitor Cadjust 330 cannot be charged when the switching device S1335 is open; however, Cadjust 330 can discharge when the switching device S1335 is either open or closed.


Continuing with the example of FIG. 3, the voltage across capacitor Cx 347 and the resistive divider R1343 and R2346 provides the control signal on the control terminal Vcont 344 of voltage regulator 345. The voltage across capacitor Cx 347 may be calculated from the primary winding voltage, VP=(VBUS−VDSon), the bias winding voltage when diode 362 is not conducting, VP (NB/NP)+VBIAS, and the forward drop of diode DX, as shown below.

VCx=(NB/NP)(VBUS−VDSon)+VBIAS−VDx(FWD);


The control signal Vcont 344 is calculated as: Vcont=VCx R1/(R1+R2).


Around the crest area of the fluctuating input voltage VIN 315 the voltage VCx 349 across capacitor Cx 347 and the control voltage Vcont 344 on control terminal 344 of voltage regulator 345 remain high to activate voltage regulator 345 and pull down the voltage on the control terminal (gate) of MOSFET 335 below its turn-on threshold, which keeps MOSFET 335 turned off (i.e., off-state). However, during the valley region of the fluctuating input voltage VIN 315 the voltage VCx 349 and the control voltage Vcont 344 drop below the turn-on threshold of voltage regulator 345 causing regulator 345 to be in an off-state. When voltage regulator 345 is turned-off, voltage at the gate of MOSFET 335 (signal 341) is pulled up through resistor 366 to the bias voltage VBIAS 365 which causes MOSFET 335 to turn on, thereby coupling capacitor Cadjust 330 in parallel with capacitor Cbase 325.


The above description of illustrated example embodiments, including what is described in the Abstract, are not intended to be exhaustive or to be limitation to the precise forms or structures disclosed. While specific embodiments and examples of the subject matter described herein are for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present invention. Indeed, it is appreciated that the specific example currents, voltages, resistances, capacitances, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings of the present invention.

Claims
  • 1. An energy storage circuit for use with a power converter, the power converter having an energy transfer element that receives a fluctuating input voltage produced from a rectified AC input line voltage, the fluctuating input voltage being provided on an input bus coupled to a primary side of the energy transfer element, the energy transfer element having an output side that delivers an output signal to a load, a power switch being coupled to the primary side of the energy transfer element for regulating a transfer of energy to the output signal delivered to the load, a bias supply of the energy transfer element being coupled between first and second nodes, the bias supply producing a bias voltage at the first node, the energy storage circuit comprising: a base capacitor coupled between the input bus and a ground potential, the base capacitor having a first capacitance;an adjust capacitor having a second capacitance;a switching device coupled in series with the adjust capacitor between the input bus and the ground potential; anda control circuit that includes a voltage regulator having first and second terminals respectively coupled to a control terminal of the switching device and the ground potential, the control circuit further including a resistor coupled between the first node and the control terminal, the voltage regulator further having an input coupled to the second node,wherein during normal operation when the power switch is turned on a signal at the second node is representative of the fluctuating input voltage, the voltage regulator being activated when the fluctuating input voltage is in a crest region thereby turning the switching device off and disengaging the adjust capacitor, the voltage regulator being deactivated when the fluctuating input voltage is in a valley region, thereby turning the switching device on and engaging the adjust capacitor, such that when the adjust capacitor is engaged a total capacitance of the energy storage circuit is equal to a sum of the first and second capacitances.
  • 2. The energy storage circuit of claim 1 wherein the first capacitance is relatively small as compared to the second capacitance.
  • 3. The energy storage circuit of claim 2 wherein a ratio of the second capacitance to the first capacitance is 2:1 or greater.
  • 4. The energy storage circuit of claim 1 wherein the base capacitor has a relatively high voltage rating as compared to the adjust capacitor.
  • 5. The energy storage circuit of claim 2 wherein the first capacitance is determined by a holdup time of the power converter.
  • 6. The energy storage circuit of claim 1 wherein the power converter is a DC-to-DC power converter.
  • 7. The energy storage circuit of claim 1 wherein the power converter is a DC-to-DC flyback power converter.
  • 8. The energy storage circuit of claim wherein the total capacitance is determine by a minimum specified valley voltage of the fluctuating input voltage.
  • 9. The energy storage circuit of claim 1 wherein the control circuit further includes a charging capacitor coupled to the second node and to the input of the voltage regulator, in the valley region of the fluctuating input voltage a voltage on the charging capacitor dropping below a turn-on threshold of the voltage regulator.
  • 10. The energy storage circuit of claim 9 wherein the charging capacitor is coupled to the input of the voltage regulator through a resistor divider.
  • 11. The energy storage circuit of claim 1 wherein the switching device is a MOSFET.
  • 12. A power converter comprising: an energy transfer element having a primary side that receives a fluctuating input voltage produced from a rectified AC input line voltage, the fluctuating input voltage being provided on an input bus, the energy transfer element also having a bias supply coupled between first and second nodes, the bias supply producing a bias voltage at the first node, and an output side that delivers an output signal to a load;a power switch coupled to the primary side for regulating a transfer of energy to the output signal delivered to the load;a base capacitor coupled between the input bus and a ground potential, the base capacitor having a first capacitance;an adjust capacitor having a second capacitance;a switching device coupled in series with the adjust capacitor between the input bus and the ground potential; anda control circuit that includes a voltage regulator having first and second terminals respectively coupled to a control terminal of the switching device and the ground potential, the control circuit further including a resistor coupled between the first node and the control terminal, the voltage regulator further having an input coupled to the second node,wherein during normal operation when the power switch is turned on a signal at the second node is representative of the fluctuating input voltage, the voltage regulator being activated when the fluctuating input voltage is in a crest region thereby turning the switching device off and disengaging the adjust capacitor, the voltage regulator being deactivated when the fluctuating input voltage is in a valley region, thereby turning the switching device on and engaging the adjust capacitor, such that when the adjust capacitor is engaged a total capacitance of the energy storage circuit is equal to a sum of the first and second capacitances.
  • 13. The energy storage circuit of claim 12 wherein the first capacitance is relatively small as compared to the second capacitance.
  • 14. The power converter of claim 13 wherein a ratio of the second capacitance to the first capacitance is 2:1 or greater.
  • 15. The power converter of claim 12 wherein the base capacitor has a relatively high voltage rating as compared to the adjust capacitor.
  • 16. The power converter of claim 12 wherein the first capacitance is determined by a holdup time of the power converter.
  • 17. The power converter of claim 12 wherein the power converter is a DC-to-DC power converter.
  • 18. The power converter of claim 12 wherein the power converter is a DC-to-DC flyback power converter.
  • 19. The power converter of claim 12 wherein the total capacitance is determined by a minimum specified valley voltage of the fluctuating input voltage.
  • 20. The power converter of claim 12 wherein the control circuit further includes a charging capacitor coupled to the second node and to the input of the voltage regulator, in the valley region of the fluctuating input voltage a voltage on the charging capacitor dropping below a turn-on threshold of the voltage regulator.
  • 21. The power converter of claim 20 wherein the charging capacitor is coupled to the input of the voltage regulator through a resistor divider.
  • 22. The power converter of claim 12 wherein the switching device is a MOSFET.
US Referenced Citations (140)
Number Name Date Kind
3740581 Pfiffner Jun 1973 A
4777580 Bingham Oct 1988 A
4866585 Das Sep 1989 A
4871686 Davies Oct 1989 A
4875151 Ellsworth et al. Oct 1989 A
4972237 Kawai Nov 1990 A
4982260 Chang et al. Jan 1991 A
5008794 Leman Apr 1991 A
5072268 Rumennik Dec 1991 A
5164891 Keller Nov 1992 A
5258636 Rumennik et al. Nov 1993 A
5274259 Grabowski et al. Dec 1993 A
5282107 Balakrishnan Jan 1994 A
5285367 Keller Feb 1994 A
5313082 Eklund May 1994 A
5323044 Rumennik et al. Jun 1994 A
5411901 Grabowski et al. May 1995 A
5510972 Wong Apr 1996 A
5612567 Baliga Mar 1997 A
5850337 Lee Dec 1998 A
5880942 Leu Mar 1999 A
5969566 Weber et al. Oct 1999 A
6084277 Disney et al. Jul 2000 A
6157049 Mitlehner et al. Dec 2000 A
6168983 Rumennik et al. Jan 2001 B1
6207994 Rumennik et al. Mar 2001 B1
6252288 Chang Jun 2001 B1
6366485 Fujisawa Apr 2002 B1
6424007 Disney Jul 2002 B1
6445600 Ben-Yaakov Sep 2002 B2
6465291 Disney Oct 2002 B1
6468847 Disney Oct 2002 B1
6489190 Disney Dec 2002 B2
6501130 Disney Dec 2002 B2
6504209 Disney Jan 2003 B2
6509220 Disney Jan 2003 B2
6549439 Yu Apr 2003 B1
6552597 Disney Apr 2003 B1
6555873 Disney et al. Apr 2003 B2
6555883 Disney et al. Apr 2003 B1
6563171 Disney May 2003 B2
6570219 Rumennik et al. May 2003 B1
6573558 Disney Jun 2003 B2
6577512 Tripathi et al. Jun 2003 B2
6583663 Disney Jun 2003 B1
6633065 Rumennik et al. Oct 2003 B2
6635544 Disney Oct 2003 B2
6639277 Rumennik et al. Oct 2003 B2
6661276 Chang Dec 2003 B1
6667213 Disney Dec 2003 B2
6680646 Disney Jan 2004 B2
6724041 Rumennik et al. Apr 2004 B2
6724244 Wu Apr 2004 B2
6730585 Disney May 2004 B2
6734461 Shiomi et al. May 2004 B1
6734714 Disney May 2004 B2
6750105 Disney Jun 2004 B2
6759289 Disney Jul 2004 B2
6768171 Disney Jul 2004 B2
6768172 Rumennik et al. Jul 2004 B2
6777749 Rumennik et al. Aug 2004 B2
6781198 Disney Aug 2004 B2
6787437 Rumennik et al. Sep 2004 B2
6787847 Disney et al. Sep 2004 B2
6798020 Disney et al. Sep 2004 B2
6800903 Rumennik et al. Oct 2004 B2
6815293 Disney et al. Nov 2004 B2
6818490 Disney Nov 2004 B2
6825536 Disney Nov 2004 B2
6828631 Rumennik et al. Dec 2004 B2
6838346 Disney Jan 2005 B2
6865093 Disney Mar 2005 B2
6882005 Disney et al. Apr 2005 B2
6933769 Koelling Aug 2005 B2
6987299 Disney et al. Jan 2006 B2
7092268 George Aug 2006 B2
7115958 Disney et al. Oct 2006 B2
7135748 Balakrishnan Nov 2006 B2
7193402 Lee et al. Mar 2007 B2
7220629 Balakrishnan May 2007 B2
7221011 Banerjee et al. May 2007 B2
7221128 Usui May 2007 B2
7233191 Wang et al. Jun 2007 B2
7253042 Disney Aug 2007 B2
7253059 Balakrishnan Aug 2007 B2
7295451 Charles Nov 2007 B2
7301389 Soady Nov 2007 B2
7335944 Banerjee Feb 2008 B2
7348830 Debroux Mar 2008 B2
7381618 Disney Jun 2008 B2
7391088 Balakrishnan Jun 2008 B2
7408796 Soldano Aug 2008 B2
7459366 Banerjee Dec 2008 B2
7468536 Parthasarathy Dec 2008 B2
7494875 Disney Feb 2009 B2
7557406 Parthasarathy Jul 2009 B2
7585719 Balakrishnan Sep 2009 B2
7595523 Parthasarathy et al. Sep 2009 B2
7616050 Eckstein Nov 2009 B2
7696598 Francis et al. Apr 2010 B2
7741788 Ito et al. Jun 2010 B2
7746156 Massie et al. Jun 2010 B1
7760524 Matthews Jul 2010 B2
7893754 Kung Feb 2011 B1
7999606 Kung et al. Aug 2011 B2
8115457 Balakrishnan et al. Feb 2012 B2
8125265 Kung et al. Feb 2012 B2
8278994 Kung et al. Oct 2012 B2
8300440 Ho et al. Oct 2012 B2
8373356 Shao et al. Feb 2013 B2
9148929 Jiang et al. Sep 2015 B2
20010043480 Shona Nov 2001 A1
20020125541 Korec et al. Sep 2002 A1
20030201821 Coady Oct 2003 A1
20040041622 Wu Mar 2004 A1
20040061454 Prasad Apr 2004 A1
20040109335 Gan et al. Jun 2004 A1
20050035371 Fujihira Feb 2005 A1
20050167749 Disney Aug 2005 A1
20050212583 Pai Sep 2005 A1
20050230745 Fatemizadeh et al. Oct 2005 A1
20050242411 Tso Nov 2005 A1
20060028779 Bax et al. Feb 2006 A1
20070035286 Lee et al. Feb 2007 A1
20070146020 Williams Jun 2007 A1
20070211504 Unkrich Sep 2007 A1
20080018261 Kastner Jan 2008 A1
20080136350 Tripathi et al. Jun 2008 A1
20080259653 Baurle et al. Oct 2008 A1
20090016090 Knight Jan 2009 A1
20090040795 Park et al. Feb 2009 A1
20090120200 Chakrabartty May 2009 A1
20090261790 Arduini Oct 2009 A1
20100109561 Chen et al. May 2010 A1
20110025278 Balakrishnan et al. Feb 2011 A1
20110149615 Matthews Jun 2011 A1
20120028083 Jung Feb 2012 A1
20120074896 Lui et al. Mar 2012 A1
20130020964 Nuhfer et al. Jan 2013 A1
20140340065 Svorc et al. Nov 2014 A1
Foreign Referenced Citations (2)
Number Date Country
0975024 Jan 2000 EP
2003142698 May 2003 JP
Non-Patent Literature Citations (2)
Entry
Popa et al., “Optimal Curvature-Compensated BiCMOS Bandgap Reference”. Image and Signal Processing and Analysis, 2001, pp. 507-510, Fig. 2.
Maleis: “Full-Wave Rectifier for CMOS IC chip”. Reg. No. H64, May 6, 1986.