Patent Application
20150235711
A non-volatile memory cell with an improved sensing amplifier is disclosed.
Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
Read operations usually are performed on floating gate memory cells using sensing amplifiers. A sensing amplifier for this purpose is disclosed in U.S. Pat. No. 5,386,158 (the “'158 Patent”), which is incorporated herein by reference for all purposes. The '158 Patent discloses using a reference cell that draws a known amount of current. The '158 Patent relies upon a current mirror to mirror the current drawn by the reference cell, and another current minor to minor the current drawn by the selected memory cell. The current in each current mirror is then compared, and the value stored in the memory cell (e.g., 0 or 1) can be determined based on which current is greater.
Another sensing amplifier is disclosed in U.S. Pat. No. 5,910,914 (the “'914 Patent”), which is incorporated herein by reference for all purposes. The '914 Patent discloses a sensing circuit for a multi-level floating gate memory cell or MLC, which can store more than one bit of data. It discloses the use of multiple reference cells that are utilized to determine the value stored in the memory cell (e.g., 00, 01, 10, or 11). Current mirrors are utilized in this approach as well.
The current minors of the prior art utilize PMOS transistors. One characteristic of PMOS transistors is that a PMOS transistor can only be turned “on” if the voltage applied to the gate is less than the voltage threshold of the device, typically referred to as VTH. One drawback of using current minors that utilize PMOS transistors is that the PMOS transistor causes a VTH drop. This hinders the ability of designers to create sensing amplifiers that operate at lower voltages.
Another drawback of the prior art design is that PMOS transistors are relatively slow when the gate transitions from high to low (i.e., when the PMOS transistor turns on). This results in delay of the overall sensing amplifier.
What is needed is an improved sensing circuit that operates using a lower voltage supply than in the prior art.
What is further needed is an improved sensing circuit where the voltage supply can be turned off when not in use to save power, but where the sensing circuit can become operational without a significant timing penalty once the voltage supply is turned back on.
The aforementioned problems and needs are addressed by providing a sensing circuit that utilizes a resistor pair instead of a transistor pair as a current mirror. The use of a resistor pair instead of a transistor pair enables the use of a lower voltage supply with a shorter startup time.
In one embodiment, a reference cell current is applied to a current mirror. The mirrored current is coupled to the selected memory cell. The mirrored current is compared to the selected memory cell current, and a sense output is generated that indicates the state of the memory cell (e.g., 0 or 1) and that is directly related to the relative size of the current through the selected memory cell compared to the reference current.
In another embodiment, a mirror pair block is added between the current mirror and the selected memory cell.
Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.
An embodiment will now be described with reference to
Reference circuit 50 will draw a set amount of current, iREF. The current through resistor 20 will be iREF. Because operational amplifier 40 acts as a clamp loop, the voltage drop across resistor 20 and resistor 30 will be the same, and they therefore will form a current mirror, and the current through resistor 30 also will be iREF (or a multiple thereof, if the values of resistor 20 and resistor 30 are not equal).
In operation, memory cell 60 will draw a level of current, iS, that depends upon the value stored in the memory cell. For example, memory cell 60 might draw a low amount of current if it is storing a “0” and a high amount of current if it is storing a “1.”
In this example, if iREF>iS, then sense output 80 will have a relatively high voltage. If iREF<iS, then sense output 80 will have a relatively low voltage. Thus, if the value stored in memory cell 60 is “0,” then iS will be relatively low and iREF will be greater than iS, meaning that sense output 80 will have a high voltage representing a “1.” If the value stored in memory cell 60 is “1,” then iS will be relatively high and iREF will be less than iS, meaning that sense output 80 will have a low voltage representing a “0.” Thus, sense output 80 is the inverse of the value stored in memory cell 60. Optionally, sense output 80 can be coupled to an inverter (not shown), where the inventor would then output a value that directly corresponds to the value stored in memory cell 60.
In this example, because the current mirror is created using paired resistors instead of paired transistors, VDD can be a lower voltage than in a system using paired transistors. This design allows VDD to be able to operate at a voltage of less than 1.0V. For example, the disclosed embodiments can operate at a minimum voltage of around 0.9V.
A different embodiment will now be described with reference to
Reference circuit 150 will draw a set amount of current, iREF. The current through resistor 120 will be iREF. Because operational amplifier 140 acts as a clamp loop, the voltage drop across resistor 120 and resistor 130 will be the same, and they therefore will form a current mirror, and the current through resistor 130 also will be iREF (or a multiple thereof, depending upon the values of resistor 120 and resistor 130).
In operation, memory cell 160 will draw a level of current, iS, that depends upon the value stored in the memory cell. For example, memory cell 60 might draw a low amount of current if it is storing a “0” and a high amount of current if it is storing a “1.”
Additional detail on minor pair block 190 will now be described with reference to
Minor pair block 190 comprises PMOS transistor 193 and PMOS transistor 194. The sources of PMOS transistor 193 and PMOS transistor 194 are connected to VDD. The gates of PMOS transistor 193 and PMOS transistor 194 are connected together and to the drains of PMOS transistor 193, which in turn connects to the source of NMOS transistor 192. The voltage drop from the source-to-gate junction in PMOS transistor 193 and PMOS transistor 194 will be the same. Therefore, PMOS transistor 193 and PMOS transistor 194 will act as a current minor, and the current through PMOS transistor 194 also will be iREF (or a multiple thereof, depending on the characteristics of PMOS transistor 193 and PMOS transistor 194). The drain of PMOS transistor 194 is coupled to sense output 180, which in turn is connected to memory cell 160.
The current through sense output 180 will be iREF−iS. If iS>iREF, then this value will be negative, and sense output 180 will detect a low voltage (i.e., a “0”). If iS<iREF, then this value will be positive, and sense output 180 will detect a high voltage (i.e., a “1”). Thus, sense output 180 is the inverse of the value stored in memory cell 160. Optionally, sense output 180 can be coupled to an inverter (not shown), where the inventor would then output a value that directly corresponds to the value stored in memory cell 160.
Optionally, reference circuit 50 or reference circuit 150 could each comprise a current source circuit. Examples of current source circuits suitable for this purpose are well-known to those of ordinary skill in the art
References to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed there between) and “indirectly on” (intermediate materials, elements or space disposed there between). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed there between) and “indirectly adjacent” (intermediate materials, elements or space disposed there between). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements there between, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements there between.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201210419802.7 | Oct 2012 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US2013/063272 | 10/3/2013 | WO | 00 |
