Patent Application
20100013537
1. Field
The disclosure relates to a method and apparatus for providing low-voltage differential signaling (“LVDS”) with common mode noise suppression. More specifically, the disclosure relates to a method and apparatus for noise suppression in an LVDS receiver by providing improved common mode noise immunity through a bypass circuit.
2. Related Art
Low-voltage differential signaling is a relatively new technology suitable for high performance data transmission applications. The popularity of LVDS is driven by its ability to provide high data rates while consuming significantly less power than competing technologies. The data rate of the LVDS system is in the gigabits per sec (Gbps) range while power consumption is in the milli-watts range.
LVDS uses two signal lines to convey information. The cost of using LVDS is having two traces to conduct a signal. However, the gain is an exceptional noise tolerance in the form of common-mode rejection, allowing signal swing to be reduced to only a few hundred millivolts. Thus, LVDS provides a low-swing, differential signaling method which allows single channel data transmission at data rates above Gbps. Its low swing and current-mode driver output provide low noise and low power consumption across a wide range of frequencies.
LVDS receivers are susceptible to sudden changes in the common mode voltage at the input. The sudden change causes jitter in the received signal, and noise in the entire system. If the noise is sufficiently high, a complete data cycle can be skipped by the receiver if the sudden noise pushes the receiver front-end beyond its common mode range. A conventional method for addressing this problem includes processing the signal through passive circuit elements such capacitors and resistors prior to processing the signal to decouple common mode from transmitted signal. Signals with inherent periodicity can be transmitted using such decoupling networks. If the original signal has a DC component, encoding is required to make sure that the data stream has enough transitions to be passed through DC blocking capacitor with negligible loss. However, this is sometimes not desired due to increased complexity and encoding overhead. Thus, there is a need for a method and apparatus to provide a LVDS receiver with common mode noise suppression that can work from DC to high data rates.
In one embodiment, the disclosure relates to a method for providing LVDS signaling, where the signal information is carried on two lines that have same magnitude voltage swing with opposite polarities with respect to a common mode voltage level. In one embodiment, the method includes the following steps: receiving a first and a second input signals; converting the input voltage to current using a transconductance preamplifier; blocking the DC component of the signal through the transconductance preamplifier and bypassing the AC component of the input signal using bypass capacitors; converting the current back to voltage using a plurality of pull-up devices; and amplifying the converted current using a second amplifier.
In another embodiment, the disclosure relates to an apparatus for providing Low Voltage Differential signaling (LVDS), the apparatus comprising: a preamplifier circuit for receiving a DC component of a first signal and providing a processed DC signal; a first bypass circuit for receiving an AC component of the first signal, the first bypass circuit providing a first AC output signal; a first node for combining the processed DC signal with the first AC output signal to form a first combined output signal; and an amplifier circuit for amplifying the first combined output signal and a second signal to provide a first amplified signal and a second amplified signal, wherein the first bypass circuit is in parallel with the preamplifier circuit.
In still another embodiment, the disclosure relates to an apparatus for providing low voltage differential signaling, the apparatus comprising: a preamplifier circuit for receiving a DC component of a first signal and a DC component of a second signal, the preamplifier outputting a first processed DC signal and a second processed DC signal; a first bypass circuit for receiving an AC component of the first signal, the first bypass circuit outputting a first AC output signal; a second bypass circuit for receiving and AC component of the second signal, the second bypass circuit outputting a second AC output signal; a first node for combining the first processed DC signal and the first AC output signal to provide a first combined output; a second node for combining the second processed DC signal and the second AC output signal to provide a second combined output; and an amplifier circuit for amplifying the first combined output to provide a first amplified signal, the amplifier circuit amplifying the second combined output to provide a second amplified circuit, wherein the first bypass circuit and the second bypass circuit are in parallel with the preamplifier circuit.
These and other embodiments of the disclosure will be discussed with reference to the following non-limiting and exemplary illustrations in which like elements are numbered similarly, and where:
In one embodiment of the disclosure, the AC and the DC components of the incoming signals are separated such that a spike in the AC signal does not affect the signaling. Thus, in the embodiment of
It should be noted that while the embodiment of
The DC component of first signal 112 and DC component of second signal 122 are processed through preamplifier circuit 140. Preamplifier circuit 140 can have a gain of 1, 1.5, 2 or other suitable gains. In one embodiment, preamplifier circuit 140 applies a unity gain to each of DC component signal 112 and DC component signal 122. Consequently, first processed DC signal 118 is substantially identical to DC component of first signal 112 and second processed DC signal 128 is substantially identical to DC component of second signal 122.
As stated, AC component of first signal 114 is processed through first capacitor 130 to obtain first AC output signal 116. AC component of second signal 124 is processed through second capacitor 132 to obtain second AC output signal 126. At first node 117, first AC output signal 116 is combined with first processed DC signal 118. Similarly, at second node 127, second processed DC signal 128 is combined with second AC output signal 126. Each of first node 117 and second node 127 can define a node, an adder or a junction.
First combined output 119 and second combined output 129 are directed to amplifier circuit 150. Amplifier circuit 150 can comprise a conventional amplifier circuit. Amplifier circuit 150 can have a sufficiently high gain to convert LVDS level to CMOS level (e.g., from 350 mV to 3.5 V). As discussed in greater detail below, the built-in hysteresis prevents output from changing when differential signals dwell around 0 volts. Such event can occur during signal transition or when pre-amplifier 140 is turned off in response to an out-of-range input common mode voltage.
The output from amplifier circuit 150 comprises first amplified signal 152 and second amplified signal 154. First amplified signal 152 and second amplified signal 154 can provide the input to a receiver circuit (not shown). Advantageously, the common mode voltage is set internally at the preamplifier circuit 140, hence there is less jitter noise in the main amplifier 150. Thus, in the case of large and sudden common mode jump, DC path provides sufficient gain even though the AC path is momentarily turned off or isolated.
In circuit 200, the signal information is carried on lines 110 and 120 which have same magnitude voltage swing with opposite polarities with respect to a common mode voltage level. Pre-amplifier 140 can be a transconductance amplifier for converting the input differential voltage to differential output currents. Preamplifier 140 can be connected to an internal termination network 210, which sets the internal common mode voltage and converts current signal back to voltage. Amplifier 150 can process both AC and DC components, as long as the incoming signal is within its common mode input range, which is typically from 0.2V to 2.2V. There is also a parallel signal path from differential inputs, where inputs are bypassed by capacitors 130 and 132 to the internal termination network. Bypass capacitors 130, 132 only pass the AC level of the signal, independent of the input common mode voltage. The gain of the pre-amplifier 140 can be adjusted to be unity, such that the current through the bypass capacitors 130, 132 is 0, hence the circuitry is not loaded as long as the input signals are within the common mode range of pre-amplifier 140. Signal at the internal termination network can be amplified by a second amplifier stage 150, which convert its inputs from LVDS level (e.g., 1V-1.4V) to CMOS level (e.g., 0V-3.3V). Furthermore, amplifier 150 can have a built-in hysteresis for suppressing noise when the differential input signal crosses zero level.
Referring to
Termination network: R1=R2=R (1)
It should be noted that termination network 210 can be implemented using diode connected pull-up transistors (not shown). If diode connected pull-up transistors are used, the resistance will be equal to 1/gm (where gm is the transconductance gain). For the bypass network, the following relationship applies:
C1=C2=C (2)
Thus, the gain in the first stage (or, the preamplifier stage) can be chosen such that:
Gm*R=1 (3)
With this relationship, there will be no current through the caps as long as the inputs are within the common mode range of preamplifier 140. In one embodiment of the disclosure, C should be selected such that time constant R*C does not limit the speed of operation (that is, R*C<Tbit/2; where Tbit is the shortest input pulse width). When the input falls outside the common mode range, pre-amp turns off and the current proportional to the AC component in the signal flows into the termination network by blocking the input DC level.
Having blocked the DC current, steady input levels result in zero differential voltage at the termination network outputs. Therefore, the second amplifier stage (amplifier 150) needs to have a built-in hysteresis in order to prevent the output state to change in response to noise at the termination network. Thus, in
In step 435, the DC component of the first signal and the DC component of the second signal are directed to a preamplifier circuit. The preamplifier circuit can define a conventional amplifier with a unity gain. In one embodiment of the disclosure, the DC component of the first signal and the DC component of the second signal are directed to a preamplifier circuit. In another embodiment, the DC component of the first signal is directed to a first preamplifier circuit while the DC component of the second signal is directed to a second preamplifier circuit.
In step 440, the DC component of the first signal is combined with the AC component of the first signal. In addition, the AC component of the second signal is combined with the DC component of the second signal. Thus, a first signal and a second signal are reformed after being processed through bypass circuits and preamplifier circuit(s). Finally, in step 450, the first and the second circuits are processed through an amplifier circuit having a gain, G.
While the specification has been disclosed in relation to the exemplary and non-limiting embodiments provided herein, it is noted that the inventive principles are not limited to these embodiments and include other permutations and deviations without departing from the spirit of the disclosure. For example, while the exemplary embodiments are directed to a combination filter device protecting human eyes from laser, the principles can be used to filter out photons of any undesirable wavelength or wavelengths.
