The present invention relates to voltage regulators, more particularly, to a low voltage drop out (LDO) regulator having a high power supply rejection ratio (PSRR).
Voltage regulators are used to provide a stable voltage source to other electronic circuits. Low voltage drop out (LDO) regulators are widely used in modern applications since the operation voltages of the modern electronic devices are going lower and lower than an external supply voltage.
The battery voltage (i.e. the external supply voltage) VBAT usually includes an AC perturbation of about 200 mV peak-to-peak value in addition to the DC component of 4.3V in this example. When the battery voltage VBAT passes through the HV regulator 205 to be converted into a converted voltage VCON, the DC component is converted from 4.3V to 2.8 or 3.3V, for example. Furthermore, the AC perturbation will be filtered out. The electrical signal at a node A (i.e. VBAT) in
The present invention is to provide a low voltage drop out (LDO) regulator, in which elements of small sizes can be used so as to save a layout area thereof. In the meanwhile, the LDO regulator of the present invention maintains a high power supply rejection ratio (PSRR) characteristic.
The present invention also provides a method for improving a power supply rejection ratio (PSRR) of a low voltage drop out (LDO) regulator having a control stage and an output stage connected with and controlled by the control stage.
In accordance with the present invention, a low voltage drop out (LDO) regulator comprises a voltage buffer for receiving an input voltage containing a DC component of a first level and an AC component, converting the input voltage to output a converted voltage, the converted voltage having a DC component of a second level lower than the first level and an AC component following that of the input voltage; a control stage having a first amplifier applied with the converted voltage; and an output stage having a power transistor connected with an output of the first amplifier of the control stage, the power transistor being applied with the input voltage and being controlled by the control stage to output an output voltage with a third level.
The LDO regulator of the present invention further has a compensation block for causing a pole splitting is provided between the control stage and the output stage.
The control stage of the LDO regulator of the present invention may have two or more amplifiers cascaded together. Each amplifier in the control stage is applied with the converted voltage having the lower DC component as compared to the input voltage and the AC component following that of the input voltage.
In accordance with the present invention, a method for improving a power supply rejection ratio (PSRR) of a low voltage drop out (LDO) regulator comprising converting an input voltage containing a DC component of a first level and an AC component into a converted voltage having a DC component of a second level and an AC component following the AC component of the input voltage; applying the converted voltage to the control stage and applying the input voltage to the output stage; and applying a reference voltage to the control stage so that the control stage controls the output stage to output an output voltage of a third level.
The present invention will be further described in details in conjunction with the accompanying drawings.
The control stage 320 includes an amplifier 321 and a current mode approach block 325. A desired reference voltage Vref is fed to an inverting input of the amplifier 321. A non-inverting input of the amplifier 321 is connected with a voltage divider consisting of resistors 343 and 345 in the output stage 340. The voltage developed at a node C is fed back to the non-inverting input of the amplifier 321. An output of the amplifier 321 is connected to the current mode approach block 325. The current mode approach block 325 is used to transfer the output of the amplifier 321 from a lower voltage level to a higher voltage level so as to prevent the LDO regulator 300 from voltage stress. The output stage 340 comprises a power transistor 341, which is implemented by a power PMOS transistor in the present embodiment, and the voltage divider consisting of the resistors 343 and 345. The power transistor 341 is a path element. The battery voltage VBAT is connected to a source of the power transistor 341. An output of the current mode approach block 325 is connected to a gate of the power transistor 341. A drain of the power transistor 341 is connected to the voltage divider as an output of the LDO regulator 300 to output a regulated voltage VOUT. According to a difference between the reference voltage Vref and the feedback voltage from node C, the amplifier 321 controls the gate voltage of the power transistor 341 so that the power transistor 341 outputs the regulated output voltage of a specific level, which is substantially determined by the reference voltage Vref.
The control stage 320 is fed with the lower voltage VCON converted by the voltage buffer 305. That is, the control stage 320 is in a low power domain. Therefore, components of smaller sizes can be used in the control stage 320. In contrast, the output stage 340 is directly fed with the battery voltage VBAT, and therefore the output stage 340 is in a high power domain. The compensation block 330 is connected between these two different power domains. The compensation block 330 is connected between the output of the amplifier 321 and the gate of the power transistor 341. The compensation block 330 is used to implement Miller compensation, that is, to cause a phenomenon of “pole splitting”, which is well known in this field. The compensation block 300 generates a dominant pole at the low power domain side, and pushes a pole at the high power domain away, and thereby improving the stability of the LDO regulator 300.
As can be seen, the signal at a node A of this drawing is the battery voltage VBAT, which contains the DC component and the AC component (i.e. AC perturbation). In addition, as described above, by converting the input battery voltage VBAT into the converted voltage VCON without filtering out the AC component, the signal at a node B (i.e. VCON) contains the DC component lower than that of VBAT and the AC component following that of VBAT. Accordingly, the AC perturbation will appear at both the source and gate of the power transistor 341. As can be seen, a gate-to-source voltage VGS of the power transistor 341 will be constant since the effect of the AC perturbation is cancelled out. Therefore, the power supply rejection ratio (PSRR) of the regulator 300 is improved.
The voltage buffer 305 can be implemented by any appropriate electronic element or circuit to achieve the functions of converting down the DC component while substantially maintaining the AC component of an input signal.
Alternatively, the voltage buffer 305 can be implemented by a circuit 605 shown in
As practical requirement, the control stage of the LDO regulator in accordance with the present invention may include more than two amplifiers cascaded together. That is, there can be more than two amplification stages. No matter how many amplification stages are in the control stage, these amplification stages are all fed with the converted voltage with the AC component following the AC component of the input battery voltage VBAT. By doing so, AC components will be seen at the source and gate of the power transistor of the output stage, so that the gate-to-source voltage VGS of the power transistor can substantially maintain constant. Accordingly, PSRR of the LDO regulator of the present invention is high.
While the preferred embodiment of the present invention has been illustrated and described in details, various modifications and alterations can be made by persons skilled in this art. The embodiment of the present invention is therefore described in an illustrative but not in a restrictive sense. It is intended that the present invention should not be limited to the particular forms as illustrated, and that all modifications and alterations which maintain the spirit and realm of the present invention are within the scope as defined in the appended claims.