Low voltage, fast settling precision current mirrors

Abstract

Low voltage, fast settling precision current mirrors and methods. The precision current mirror have first and second current mirrors, each having an input to be mirrored and a mirror output, the current mirrors being coupled so that the mirror output of each current mirror receives part of the input to be mirrored by the other current mirror, the first current mirror also mirroring current for re-mirroring to the input of the second current mirror, and to a precision current mirror output in proportion to the current provided to the input of the second current mirror. Various embodiments are disclosed, including MOS and junction transistor embodiments, and an embodiment having increased output impedance.Details of the method are disclosed.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of current mirrors, particularly as used in integrated circuits.

2. Prior Art

Current mirrors are very frequently used in integrated circuits to set bias currents for various parts of the circuit. Typically the currents of one or more current sources, such as a current source that is independent of temperature or proportional to absolute temperature, is mirrored to various parts of a circuit so that one (or a very few) current sources may be mirrored to numerous sub-circuits for biasing purposes. In other cases, current mirrors may be used in the signal path itself, mirroring a signal current of one sub-circuit to one or more other sub-circuits. Whatever the application of the current mirror, the accuracy and/or sensitivity of the current mirror to such parameters as power supply noise and β (beta) variation of the transistors used (junction transistors in this example) with process variations and collector current frequently has a very substantial effect on the performance of the circuit. Reduction in such sensitivities can substantially improve circuit performance, or reduce power supply filtering requirements, or both.

By way of example, the well-known PNP current mirror circuit is shown in FIG. 1 . The output current I O is:

I O =I IN /(1+(p+1)/β PNP )

Where:

I IN =the input current to the current mirror

p=the area ratio of transistor Q 2 to transistor Q 1

β PNP =the ratio of collector current to base current for the PNP transistors Q 1 and Q 2

The current multiplication error is set by the β PNP parameter value. For most cases this parameter has a low value (10 to 50) and is rapidly falling at high collector currents. The output current sensitivity to β PNP variation is:

(ΔI O /I O )/(Δβ PNP /β PNP)≅( 1+p)/β PNP

The output current sensitivity to power supply voltage variation is:

(ΔI O /ΔV+)/I O ≅1/V AP

BRIEF SUMMARY OF THE INVENTION

Low voltage, fast settling precision current mirrors and methods. The precision current mirror have first and second current mirrors, each having an input to be mirrored and a mirror output, the current mirrors being coupled so that the mirror output of each current mirror receives part of the input to be mirrored by the other current mirror, the first current mirror also mirroring current for re-mirroring to the input of the second current mirror, and to a precision current mirror output in proportion to the current provided to the input of the second current mirror. Various embodiments are disclosed, including MOS and junction transistor embodiments, and embodiments having increased output impedance.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram for a prior art PNP current mirror circuit.

FIG. 2 is a simplified circuit diagram of an embodiment of the invention.

FIG. 3 is a circuit diagram for an embodiment of the invention using n-channel MOS transistors as the active devices.

FIG. 4 is a circuit diagram for another embodiment using bipolar transistors as the active devices.

FIG. 5 is a circuit diagram for a version of the embodiment of FIG. 4 , but having an improved (higher) output impedance.

FIG. 6 is a diagram of a generalized form of the embodiment of the present invention shown in FIG. 3 .

FIG. 7 is a diagram of a generalized form of an embodiment of the present invention similar to FIG. 6 , but with the additional transistors P 2 A and P 3 A to further increase the output impedance of the circuit.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Now referring to FIG. 2 , a simplified circuit of an embodiment of the invention may be seen. In this embodiment, the active devices, Device 1 to Device 5 , are n-type transistors (bipolar or field-effect). Device 1 , Device 2 , Device 3 and Device 4 , Device 5 , respectively, are matched devices. Device 1 and Device 5 are diode-connected. Thus, the impact of collector/drain to emitter/source voltage (Early voltage) upon the transfer characteristics of Device 1 , Device 2 , Device 4 and Device 5 is minimal. Thus I 1 =I 3 , and I 4 =I 5 .

For simplicity of illustration, assume that the current flowing into the control terminals of each transistor is negligible. With this assumption:

I IN1 =I 1 +I 4 and I SENSE +I IN2 =I 3 +I 5

This yields:

I SENSE −(I IN1 −I IN2 )=(I 3 −I 1 )+(I 5 −I 4 )=0

Therefore:

I SENSE =I IN1 −I IN2

The current I 2 is the input to the Output Current Control Circuit, providing appropriate functionality of the feedback system. This block has such a structure that we may assume that I OUT =m*I SENSE . Based on the previous result:

I OUT =m*(I IN1 −I IN2 )

Where:

m=a multiplying factor normally realized by a ratio of transistor sizes

Thus the source output current, I OUT , is precisely controlled by the difference in the input currents (I IN1 −I IN2 ),

Similarly, if devices Device 1 to Device 5 are p-type and the Output Current Control Circuit is correspondingly changed, then the output sink-current, I OUT , is proportional to the difference in the input sink-currents, I IN1 −I IN2 .

FIG. 3 is a circuit diagram for an embodiment of the invention using MOS transistors as the active devices. The input signal is applied in two places through the currents I IN1 =2*I and I IN2 =I. The input currents I IN1 , I IN2 can have any relative values, though for optimum performance, the ratio between these two currents I IN1 /I IN2 should be two.

In the following analysis, it is assumed that NMOS transistors N 1 , N 2 , N 3 and N 4 , N 5 are matched, having the same aspect ratio (W/L) N1 =(W/L) N2 =(W/L) N3 , and (W/L) N4 =(W/L) N5 .

PMOS transistors P 1 , P 2 are matched, having the same aspect ratio (W/L) P1 =(W/L) P2 . PMOS transistor P 3 is an exact multiple of transistor P 2 : (W/L) P3 /(W/L) P2 =M P . Similarly, NMOS transistor N 7 is an exact multiple of the transistor N 6 : (W/L) N7 /(W/L) N6 =M N .

For simplicity, assume that the diode-connected transistors N 1 , N 5 and N 6 have the same V GS (gate-source voltage). Thus transistors N 1 , N 3 have the same V GS and equal V DS (drain-source voltage) Transistors N 4 , N 5 have the same V GS and equal V DS . Transistors 22 and P 3 have the same V GS and equal V DS .

Also assume that all NMOS and PMOS devices operate in the strong inversion region. Therefore, the square law applies:

I D =K*(V GS −V T ) 2 *(1+λ*V DS )

Where:

K=a constant

V GS =the gate to source voltage

V T =the threshold voltage of the transistor

λ=1/V A $$ V A = I D ∂ I D ∂ V DS

I D =the drain current

V DS =the drain to source voltage

Based on the above:

I N1 =I N3 , I N4 =I N5 and I P3 =M P *I P2

By simple inspection of the circuit:

I N1 +I N4 =2*I and I N3 +I N5 =I P2+I

From the foregoing two sets of equations:

I P2 =I and I P3 =M P *I

The result obtained in the foregoing equation shows that the proposed circuit generates a current I P3 that is a precise multiple of the input current I. Further, the current I P3 is multiplied by the current mirror formed by transistors N 6 ,N 7 generating the output current I N7 . This circuit contains a composite negative-positive feedback: transistor N 4 closes the negative feedback path (primary loop), while transistor N 3 closes the positive feedback path (secondary loop).

The loop-gain is kept low due to the diode-connected transistors N 1 and N 5 . The loop should be stable without any additional compensation, though if needed, compensation can be added, such as by a capacitor connected between the gate of transistor N 1 and ground.

The supply voltage rejection can be simply explained as follows: the supply voltage variation will change I P2 ; the feedback loop action will change I N1 and I N4 in opposite directions, therefore canceling out the variation of I P2 and, consequently, the variation of I P3 .

The improvement in power supply rejection with regard to I P3 current compared to the traditional cascaded current mirror solution can be estimated with the following formula:

(ΔI P3 /ΔV+)/I P3 | NEW /(ΔI P3 /ΔV+)/I P3 | OLD ≈(V GS5 −V T )*(λ P +λ N )/2.

Where:

V+=the positive power supply voltage

This circuit improves the power supply rejection by at least an order of magnitude compared to the traditional solution with cascaded simple current mirrors.

There are three major points of merit associated with this circuit:

1) The minimum supply voltage is (V+) min =V GS +(V DS ) sat ≈1.1V.

2) Improved power supply rejection compared to simple current mirrors.

3) Fast settling time; the AC response of the circuit is excellent (normally, no compensation network is required).

FIG. 4 is a circuit diagram for another embodiment using bipolar transistors as the active devices. This circuit generates an output current I C8 , which is a precise multiple of the input current difference (I IN1 −I IN2 ):

I C8 =p*(I IN1 −I IN2 )

Where:

p=the ratio of the area of transistor Q 8 and transistor Q 6 or Q 7

I C8 is applied to the current mirror formed by transistors Q 9 ,Q 10 . The circuit functionality is similar to that presented in the previous embodiment.

In this circuit:

V BE1 =V BE3 , V BE4 =V BE5 and V EB7 =V EB8

The voltage drop across the diode-connected transistors Q 1 , Q 5 , Q 9 may be considered to be the same. Therefore:

V CE1 =V CE3 , V CE4 =V CE5 and V EC7 =V EC8

I C1 =I C3 , I C4 =I C5 and I C8 /I C7 =p

Neglecting the base currents for the moment:

I IN1 =I C1 +I C4

I C3 +I C5 =I C7+I IN2 =I C8 /p+I IN2

I C8 =p*(I IN1 −I IN2 )=p*I

The precise control of the current I C8 is achieved through a negative-positive feedback loop: transistor Q 4 closes a negative feedback path while transistor Q 3 closes a positive feedback path. The loop gain is kept low due to the low impedance diode-connected transistors Q 1 and Q 5 . In most cases, this enables the loop to be AC-stable without any additional compensation network. If needed, a capacitor connected between the base and emitter of transistor Q 1 can be added.

The frequency response of this circuit is excellent, providing fast settling. Some merits of this circuit can be evaluated through the following formulas, derived from circuit analysis:

I C8 sensitivity to β PNP variations is:

(ΔI C8 /I C8 )/(Δβ PNP /β PNP )≅5*(p+2)/(β PNP *β NPN )

I C8 sensitivity to β NPN variations:

(ΔI C8 /I C8 )/(Δβ NPN /β NPN )≅(5/β NPN )*(1+(p+2)/β PNP −0.4*I IN1 /(I IN1 −I IN2 ))

Considering I IN1 =2* I, I IN2 =I then:

(ΔI C8 /I C8 )/(Δβ NPN /β NPN )≅(5/β NPN )*(0.2+(p+2)/β PNP )

I C8 sensitivity to V+ variations:

(ΔI C8 /I C8 )/(ΔV+)≅(5/β NPN )*(1+(p+2)/β PNP )/V AP

Where:

V AP =V A for the β PNP transistors

The performance improvement of the proposed circuit in FIG. 4 with regard to that of the circuit in FIG. 1 can be derived from the above equations:

Output current sensitivity to β PNP variation:

(ΔI O /I O )/(Δβ PNP /β PNP )| NEW /(ΔI O /I O )/(Δβ PNP /β PNP | OLD ≅5/β NPN

Output current sensitivity to supply variation:

(ΔI O /ΔV+)/I O | NEW /(ΔI O /ΔV+)/I O | OLD ≈(5/β NPN )*(1+(p+2)/β PNP )

The above equations show that this novel circuit of FIG. 4 improves the performance by at least an order of magnitude compared to the traditional solution with a simple current mirror of FIG. 1 . There are three major points of merit associated with this novel circuit:

1) The minimum supply voltage is (V+) min =V BE +(V CE ) sat ≈0.9V.

2) Improved power supply rejection compared to simple current mirrors.

3) Fast settling time; the AC response of the circuit is excellent (normally, no compensation network is required).

FIG. 5 is a circuit diagram for a version of the previous embodiment having an improved (higher) output impedance. The functionality of the circuit in FIG. 5 is similar to that presented with respect to the embodiment of FIG. 4 , and generally the analytical results for that embodiment apply to this embodiment as well. The addition of transistor Q 9 , which forms a cascode with transistor Q 7 , together with transistor Q 10 , increases the output impedance roughly by an order of magnitude. In particular, as a first order approximation, V BE10 =V EB9 . Thus the collector voltage of transistor Q 7 will always be substantially equal to the collector voltage of transistor Q 8 . This causes the current I C8 to very accurately track p*I C7 throughout the output voltage range. Also, to the extent that the base current I B10 approximates p times the base current I B9 , the output current I O will very accurately track p*I C9 over the output voltage range. The minimum output voltage compliance is:

(V+)−V O =V EC7 +(V EB9 −V BE10 )≅V EC7 ≈(V EC7 ) sat

A generalized form of one embodiment of the present invention may be seen in FIG. 6 . As shown therein, the precision current mirror comprises first (current mirror 1 ) and second (current mirror 2 ) current mirrors, each having an input (I N1 and I N2 , respectively) to be mirrored and a mirror output (OUT 2 and OUT, respectively), the current mirrors being coupled so that the mirror output of each current mirror (OUT 2 and OUT, respectively), receives part of the input (I N1 and I N2 , respectively) to be mirrored by the other current mirror, the first current mirror also mirroring current (OUT 1 ) for re-mirroring (I) to provide part of the input of the second current mirror, and to a precision current mirror output M p I in proportion to the current provided to the input of the second current mirror. FIG. 5 also has a mirror on the output, providing a final output of M p M h I.

FIG. 7 is similar to FIG. 6 , though with the addition of transistors P 2 A and P 3 A, two transistors F. preferably with the same threshold voltage. Thus the drain potential of transistor P 2 will follow the drain potential of transistor P 3 , therefore achieving a high output impedance. In general, any mirror circuits using any transistor and conductivity types can be used in the circuits of the present invention as desired.

Obviously, as is well known in the art, any of the exemplary circuits, and obvious modifications thereof, may be realized by devices of the opposite conductivity type by flipping the applicable circuit diagram about a horizontal axis and reversing the current flow directions, so that the circuits previously acting as sources become sinks, and circuits previously acting as sinks become sources. Thus while the present invention has been disclosed and described with respect to certain preferred embodiments thereof, it will be understood to those skilled in the art that the present invention may be varied without departing from the spirit and scope thereof.

Claims

1. A current mirror comprising:first through fifth semiconductor devices and an output current control circuit; a first component of the current to be mirrored being coupled to a common connection of the first and fourth semiconductor devices; a second component of the current to be mirrored being coupled to a common connection of the third and fifth semiconductor devices; the current in the first device being mirrored to the second and third semiconductor devices; the current in the fifth semiconductor device being mirrored to the fourth semiconductor device; the output current control circuit having one output coupled to the common connection of the third and fifth semiconductor devices and responsive to the current in the second semiconductor device to mirror the current in the second semiconductor device to the fifth and third semiconductor devices and to a current mirror output.

2. The current mirror of claim 1 wherein the first, second and third semiconductor devices are matched devices, and the fourth and fifth semiconductor devices are matched devices.

3. The current mirror of claim 1 wherein the first component of current to be mirrored is twice the second component of current to be mirrored.

4. The current mirror of claim 1 wherein the semiconductor devices are bipolar transistors.

5. The current mirror of claim 1 wherein the semiconductor devices are MOS transistors.

6. The current mirror of claim 1 wherein the output current control circuit comprises sixth, seventh and eighth semiconductor devices, the sixth semiconductor device being coupled to the second semiconductor device and responsive to the current in the second semiconductor device to mirror the current in the second semiconductor device to the seventh and eighth semiconductor devices, the seventh semiconductor device being coupled to the fifth and third semiconductor devices, and the eighth semiconductor device providing the current mirror output.

7. The current mirror of claim 6 wherein the sixth, seventh and eighth semiconductor devices are complimentary semiconductor devices to the first through fifth semiconductor devices.

8. The current mirror of claim 7 wherein the sixth and seventh semiconductor devices are the same size and the eighth semiconductor device is a different size than the sixth and seventh semiconductor devices.

9. The current mirror of claim 7 further comprised of a circuit causing the voltages on the seventh and eighth transistor devices to track.

10. A method of mirroring current comprising:coupling a first component of the current to be mirrored to a common connection of first and fourth semiconductor devices; coupling a second component of the current to be mirrored to a common connection of third and fifth semiconductor devices; mirroring the current in the first device to second and third semiconductor devices; mirroring the current in the fifth semiconductor device to the fourth semiconductor device; and, mirroring the current in the second semiconductor device to the common connection of the fifth and third semiconductor devices and to a current mirror output.

11. The method of claim 10 wherein the first, second and third semiconductor devices are matched devices, and the fourth and fifth semiconductor devices are matched devices.

12. The method of claim 10 wherein the first component of current to be mirrored is twice the second component of current to be mirrored.

13. The method of claim 10 wherein the semiconductor devices are bipolar transistors.

14. The method of claim 10 wherein the semiconductor devices are MOS transistors.

15. A precision current mirror comprising first and second current mirrors, each having an input to be mirrored and a mirror output, the current mirrors being coupled so that the mirror output of each current mirror receives part of the input to be mirrored by the other current mirror, the first current mirror also mirroring current for re-mirroring to provide part of the input of the second current mirror, and to a precision current mirror output in proportion to the current provided to the input of the second current mirror.

16. The precision current mirror of claim 15 wherein the input to be mirrored by the first current mirror is twice the input to be mirrored by the second current mirror.

17. A method of mirroring current comprising:providing a first current to be mirrored to a first current mirror and as part of the output of a second current mirror; providing a second current to be mirrored to a second current mirror and as part of the output of a first current mirror; and also, mirroring current of the first current mirror to the input of the second current mirror, and to a precision current mirror output in proportion to the current provided to the input of the second current mirror.

18. The method of claim 17 wherein the first current to be mirrored is twice the second current to be mirrored.