Patent Application
20100073070
This invention relates to bandgap voltage reference circuits, and more particularly to temperature-compensated reference circuits implemented in all complementary metal-oxide-semiconductor (CMOS) technologies.
Many kinds of electronic circuits such as voltage regulators and analog-to-digital converters compare voltages as a fundamental part of their operation. For example, an operational amplifier (op amp) compares two voltages applied to its input, and then amplifies the detected voltage difference. One of the applied voltages may be an external voltage that varies depending on operating conditions and events, while the other input is a relatively fixed voltage known as a reference voltage.
Ideally, the reference voltage would be a truly fixed voltage that never varied in voltage. However, reference voltages in real-life systems often vary significantly with variations in temperature, power-supply voltage, noise from other circuits, loading of its output, etc. Circuit designers try to minimize these variations in reference voltages by careful and creative circuit design.
While an external reference could be applied to a system, the high level of integration desired in today's systems provides significant cost and size savings when the reference is generated on-chip. Bandgap voltage reference circuits are widely popular for internal reference circuits, since the reference voltage ultimately depends on well-understood semiconductor device properties such as voltages produced at p-n junctions.
Traditional bandgap reference circuits used bipolar transistors such as PNP transistors. However, most high-integration systems use complementary metal-oxide-semiconductor (CMOS) technology. A hybrid technology with both CMOS and bipolar transistors known as BiCMOS has been used, but it is more expensive than standard CMOS. Additional mask layers are often used with BiCMOS, and power consumption is usually higher.
The higher circuit density on today's integrated circuit chips is made possible by shrinking device sizes. These smaller transistors have thinner insulator layers and are not able to withstand voltages that were used just a few years ago. Power supply voltages of 5 volts could break down transistors that are now designed for 2 or 1.5-volt power supplies.
While power supply voltages have been reduced to prevent damage to the smaller transistors used in today's circuits, other fundamental device characteristics have not tracked. For example, the transistor threshold voltage has remained at about 0.7 to 0.5 volts. As further device shrinks require that power supplies be reduced to near 1.0 volt, design of circuits that can still operate and turn on transistors using a 0.5 to 0.7 volt threshold is challenging.
Many bandgap reference circuits can only operate using power supply voltage above 2 volts. Some bandgap reference circuits that are designed to operate with 1-volt supplies suffer from low current amplification (low beta), and sacrifice current drive strength to achieve low-voltage operation. Poor power-supply rejection ratios (PSRR) and noise due to large impedances are typical.
Bandgap reference circuits can be difficult to implement when the power supply is close to 1 volt since turning on an op amp from a PNP transistor reference requires that the NMOS transistor threshold voltage Vth be less than the base-emitter junction voltage Vbe. Since Vtn and Vbe are close to each other, process yields may be low due to this requirement.
Bandgap reference circuits may feed into amplifiers that will amplify any noise that is injected into the sensitive bandgap reference circuit. Noise may be fed back into the bandgap reference circuit from its load, especially when the load is insufficiently driven by a low current drive amplifier. The reference voltage may then fluctuate due to loading noise, and this noise may even be amplified.
What is desired is a bandgap reference circuit that can be implemented in a standard CMOS process using a parasitic PNP transistor. A bandgap reference circuit that can operate with a 1-volt power supply and yet still have a high current drive to its load is desirable. A bandgap reference circuit with a low startup voltage and good line regulation and noise rejection is desirable. A bandgap reference circuit that compensates for temperature is desirable.
The present invention relates to an improvement in CMOS bandgap reference circuits. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
The inventors have realized that a bandgap reference circuit can generate a referenced voltage that is conceptually the sum of two internal reference voltages: a complementary-to-absolute temperature (CTAT) reference voltage Vctat, and a proportional-to-absolute temperature (PTAT) reference voltage Vptat. A first stage uses the parasitic PNP transistor to generate Vctat, while a second stage generates Vptat and combines it with Vctat to generate the output reference voltage Vref.
The parasitic PNP transistor may be formed in a standard CMOS process, so that a more expensive BiCMOS process is not needed. The combination of Vctat with a negative temperature coefficient and Vptat with a positive temperature coefficient produces a temperature-compensated reference voltage despite the low power supply voltage.
PMOS transistor 50 supplies current to the emitter of PNP transistor 22 to turn it on when the power supply on the source of PMOS transistor 50 is approaching 1 volt. The base-emitter voltage Vbe on the emitter of PNP transistor 22 is divided by resistors 62, 64, producing a voltage applied to the inverting input of op amp 20. The non-inverting input of op amp 20 is the voltage Va, which is generated by a current mirrored to PMOS mirror transistor 52 that passes through Va resistor 66.
Op amp 20 adjusts the voltage of its output, Vbp, depending on the voltage difference between its inputs. When Va is higher than the voltage between resistors 62, 64, op amp 20 raises Vbp, causing less current Ia to flow through PMOS mirror transistor 52, and the decreased current Ia passes through Va resistor 66, causing Va to fall. At steady-state, Va is driven by op amp 20 to be equal to the voltage between resistors 62, 64.
The gates of PMOS transistors 50, 52, 54 are tied together and driven to voltage Vbp by the output of op amp 20. Thus the current through PMOS transistor 50 is mirrored to PMOS mirror transistor 52, which produces current Ia, and PMOS mirror transistor 54, which produces current Ictat. The sizes of PMOS mirror transistors 52, 54 can be larger than the size of PMOS transistor 50 to ramp up the currents that a mirrored, but is assumed to be equal in the equations below.
As bias voltage Vbp falls, the excess current through PMOS transistor 50 is easily discharged to ground through PNP transistor 22 with little change in voltage Vbe, since the current through a PNP transistor is exponentially dependent on the base-emitter voltage. Thus the reference voltage is relatively undisturbed by feedback from op amp 20 to PMOS transistor 50.
The mirrored current through PMOS mirror transistor 54, Ictat, passes through summing resistor 60 to ground. The voltage across summing resistor 60 (Vctat) generated by the current Ictat is complementary to the absolute temperature.
The current equation for Ictat can be generated by combining equations for Va and Ia:
Va=Vbe(R64/(R62+R64))
Ia=Va/R66
Ictat=Ia=Va/R66=Vbe(R64/(R62+R64))/R66
Ictat=(Vbe/R66)*(R64/(R62+R64))
Since Vbe is complementary to absolute temperature, Ictat is also complementary-to-absolute temperature.
In a first leg, PNP transistor 24 has its emitter connected to receive the mirrored current through PMOS mirror transistor 56, and this emitter voltage is applied to the non-inverting (+) input of op amp 40. The base voltage of PNP transistor 24 is generated between resistors 72, 70.
In a second leg, PNP transistor 26 has its emitter connected to receive the mirrored current through PMOS mirror transistor 58, and this emitter voltage is applied to the inverting (−) input of op amp 40. The base voltage of PNP transistor 26 is generated between resistors 70, 60.
The third leg of the second stage has op amp 40 driving the gate of PMOS output transistor 80. The drain of PMOS output transistor 80 is voltage Vrp. The current generated by PMOS output transistor 80 flows through the series of resistors 72, 70, 60 to ground. Base voltages to PNP transistors 24, 26 are generated at intermediate points in the series of resistors 72, 70, 60, with voltage Va being applied to the base of PNP transistor 26. Current Iptat flows through resistor 70. A PTAT loop generates current Iptat. The PTAT loop includes the negative input of op amp 40 through PMOS output transistor 80 to adjust voltage VB, and adjustments in VB are applied to the base of PNP transistor 26 to adjust the collector voltage, which is the positive input to op amp 40. Op amp 40 forces the collector voltages of PNP transistors 24, 26 to be equal. This ultimately sets Iptat.
Op amp 40 adjusts the gate voltage of PMOS output transistor 80 until the two inputs of op amp 40 are equal in voltage. When the non-inverting (+) input is higher than the inverting (−) input, op amp 40 raises the gate voltage, causing a reduction in current through PMOS output transistor 80. The reduced current lowers the base voltages to PNP transistors 24, 26, causing both inputs of op amp 40 to drop. However, since the base of PNP transistor 24 passes through an extra resistor 70 compared to the base of PNP transistor 26, the base voltage of PNP transistor 24 drops more than the base voltage of PNP transistor 26 does, causing PNP transistor 24 to draw more current and pull its emitter voltage down more than PNP transistor 26. Thus the + input to op amp 40 falls more than the − input. The feedback continues until the two inputs are equal.
The voltages on the inputs of op amp 40 are:
Vopamp+Vbe24+Iptat*R70+VB
Vopamp−=Vbe26+VB
At steady state, the two op amp inputs are equal in voltage:
Vopamp+=Vopamp−
Vbe24+Iptat*R70+VB=Vbe26+VB
Vbe24+Iptat*R70=Vbe26
Iptat*R70=Vbe26−Vbe24
Iptat=(Vbe26−Vbe24)/R70
Since the transistor current depends exponentially on its Vbe:
I=Isat*(exp(Vbe/Vt)−1)
where the thermal voltage Vt=kT/q, and T is absolute temperature, q is the electron charge and k is Boltzmann's constant. Isat is the saturation current.
Vbe24=Vt ln(I24/Is24) for transistor 24, and
Vbe26=Vt ln(I26/Is26) for transistor 26.
Where I24 is the emitter current and Is24 is the saturated current for transistor 24. The saturated current Is=BT3e(−VGO/VT) where B is the proportional constant and VGO is the silicon bandgap voltage.
The voltage across resistor 70 is:
VR70=Vbe26−Vbe24
Substituting for Vbe26 and Vbe24:
VR70=Vt ln(I26/Is26)−Vt ln(I24/Is24)
Rearranging:
VR70=Vt ln((I26*Is24)/(Is26*I24)
When transistors 24, 26 are matched in size. Is24/Is26=n, which is the ratio of sizes of PNP transistors 24, 26.
VR70=Vt ln(n)
Since VR70=Iptat*R70, when Iptat is the current flowing through resistor 70:
Iptat=Vt ln(n)/R70
Since the difference in Vbe's is proportional to temperature, and Vt ln(n) is also proportional to temperature, Iptat is proportional to temperature. Thus while the first stage (
PMOS mirror transistor 54 generates current Ictat from the first stage, which flows through resistor 60 to ground. However, resistor 60 is also part of the second state, and receives current Iptat from resistor 70. Thus the sum of complementary current Ictat and proportional current Iptat flows through summing resistor 60.
In the second stage, PNP transistors 24, 26 have base voltages generated on either side of resistor 70, and have emitters driving inputs of op amp 40. Op amp 40 adjusts the gate voltage of PMOS output transistor 80, adjusting current Iptat and the base voltages of PNP transistors 24, 26 until the emitter voltages are equal. The steady-state current, Iptat, is proportional-to-absolute-temperature because Vt ln(n) is proportional to temperature. Since n is just a ratio of transistor currents, and Vt is a parameter that increases linearly with temperature, Vt ln(n) is also proportional to temperature. This Iptat current also flows through summing resistor 60 to ground.
Both currents Ictat from the first stage and Iptat from the second stage flow through summing resistor 60, producing a total voltage drop through PMOS output transistor 80 of:
VB=Ictat*R60+Iptat*R60
The reference voltage output by the drain of PMOS output transistor 80, Vref, also includes the voltage drops through resistors 70, 72, which only have current Iptat flowing through them:
Vref=Iptat*(R72+R70)+Iptat*R60+Ictat*R60
When Vptat=Iptat*(R72+R70+R60), then
Vref=Vptat+Vctat
Thus the reference voltage Vref is the combination of proportional-to-absolute-temperature and complementary-to-absolute-temperature voltage drops caused by proportional-to-absolute-temperature and complementary-to-absolute-temperature currents Iptat, Ictat.
Positive and negative compensation loops are formed inside the second stage. A positive loop is formed by PNP transistor 24, the + input of op amp 40 driving the gate of PMOS output transistor 80, which adjusts Iptat current through resistor 72 to adjust the base voltage of PNP transistor 24. A negative loop is formed by PNP transistor 26, the − input of op amp 40 driving the gate of PMOS output transistor 80, which adjusts Iptat current through resistors 72, 70 to adjust the base voltage VBof PNP transistor 26. The negative loop is larger than the positive loop since it includes an extra resistor 70.
These feedback loops provide good load line regulation. Coupling capacitor 84 can be adjusted in size for dominant pole compensation to produce a stable total loop gain. Other filers such as R-C networks could be substituted for coupling capacitor 84.
The inputs to op amp 40 are swapped in comparison to
Current is steered between differential transistors 30, 32, depending on the voltage difference of V+, V−. When V+ is lower than V−, more current flows through differential transistor 30 than through differential transistor 32, so the gate and drain of PMOS current source transistor 44 are driven lower to increase the current flow through transistors 44, 30. The lower gate voltage of PMOS current source transistor 44 is also applied to the gate of PMOS current source transistor 42, and the increased current through PMOS current source transistor 42 causes the drains between transistors 42, 34 to rise in voltage. The drain voltage is tied to the gates of NMOS transistors 34, 36, causing output node Vo, the drain of NMOS transistor 36, to go lower.
The lower V+ causes less current to flow through differential transistor 32 and PMOS current source transistors 46, 48, causing output Vo to fall.
PNP transistor 214 has its collector grounded and its emitter driven by current through PMOS transistor 218; its emitter also drives the gates of NMOS transistors 226, 210.
NMOS transistor 226 has its drain connected to the gate and drain of PMOS transistor 222, which also is the gate of PMOS transistor 220. PMOS transistor 220 has its drain driving output Vo, which is also driven by the drain of NMOS transistor 224.
The voltage difference V+, V− are amplified first by differential transistors 204, 206, then by PNP transistors 212, 214, and finally are buffered by NMOS transistors 224, 226, and PMOS transistors 220, 222.
The gates of PMOS transistors 202, 216, 218, are connected together and driven by the drain and gate of PMOS transistor 228, which also connects to the drain of NMOS transistor 230. The gate of NMOS transistor 230 is driven by the gate and drain of NMOS transistor 234. Output signal Vo is fed back to the gate of PMOS transistor 232 to drive current through NMOS transistor 234 to generate the gate bias for PMOS transistors 202, 216, 281 in the primary and secondary amplifying portions of the circuit.
Several other embodiments are contemplated by the inventors. For example. Several other embodiments are contemplated by the inventors. For example p-channel and n-channel transistors could be swapped, with p-channel transistors being used as current sources and n-channel transistors used for the sub-threshold transistors and charging transistors rather than p-channel transistors. NPN rather than PNP transistors could be substituted for some CMOS processes. This may be beneficial for processes such as n-substrate processes or dual-well processes.
Additional components may be added at various nodes, such as resistors, capacitors, inductors, transistors, etc., and parasitic components may also be present. Enabling and disabling the circuit could be accomplished with additional transistors or in other ways. Pass-gate transistors or transmission gates could be added for isolation.
Inversions may be added, or extra buffering. The final sizes of transistors and capacitors may be selected after circuit simulation or field testing. Metal-mask options or other programmable components may be used to select the final capacitor, resistor, or transistor sizes.
When a p-channel (PMOS) output transistor is used, a low-dropout (LDO) voltage regulator may be obtained with excellent frequency characteristics. Miller compensation may be provided rather than just using a coupling capacitor for pole compensation. Output and power-supply noise may be filtered out or otherwise compensated for. However, p-channel transistor tend to have lower current drive per unit size than n-channel transistors, so an NMOS source-follower may be desirable for some applications requiring higher current drive.
The circuit designer may choose the resistor to have a ratio that produces the desired reference voltage. While Complementary-Metal-Oxide-Semiconductor (CMOS) transistors have been described, other transistor technologies and variations may be substituted, and materials other than silicon may be used, such as Galium-Arsinide (GaAs) and other variations.
While positive currents have been described, currents may be negative or positive, as electrons or holes may be considered the carrier in some cases. Charging and discharging may be interchangeable terms when referring to carriers of opposite polarity. Currents may flow in the reverse direction.
The power supply may be less than 2.0 volts, such as 1.8 volts, 1.5 volts, 1.2 volts, or 1.0 volts. The generator circuit begins to operate when the power supply reaches about 0.9 volts in simulations.
While the term “bandgap” has been used, this is something of a misnomer, since the base-emitter voltage of the PNP transistor provides the reference voltage, rather than a bandgap. However, the term bandgap is nevertheless widely used for these circuits.
The background of the invention section may contain background information about the problem or environment of the invention rather than describe prior art by others. Thus inclusion of material in the background section is not an admission of prior art by the Applicant.
Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machine, computer, or other device and are not intended to be performed solely by humans without such machine assistance. Tangible results generated may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio-generating devices, and related media devices, and may include hardcopy printouts that are also machine-generated. Computer control of other machines is another a tangible result.
Any advantages and benefits described may not apply to all embodiments of the invention. When the word “means” is recited in a claim element, Applicant intends for the claim element to fall under 35 USC Sect. 112, paragraph 6. Often a label of one or more words precedes the word “means”. The word or words preceding the word “means” is a label intended to ease referencing of claim elements and is not intended to convey a structural limitation. Such means-plus-function claims are intended to cover not only the structures described herein for performing the function and their structural equivalents, but also equivalent structures. For example, although a nail and a screw have different structures, they are equivalent structures since they both perform the function of fastening. Claims that do not use the word “means” are not intended to fall under 35 USC Sect. 112, paragraph 6. Signals are typically electronic signals, but may be optical signals such as can be carried over a fiber optic line.
The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
