Claims
- 1. A frequency divider circuit that generates output signals having a frequency substantially half of the frequency of an input signal, comprising two D-Flip-Flop circuits wherein one employs said input signal and the other one employs the complement of said input signal, and wherein each of the two D-Flip-Flop circuits includes a pair of loading transistors, two regenerative transistor pairs coupled with each other, and two common-gate switches.
- 2. The circuit of claim 1, wherein said pair of loading transistors comprises p-channel CMOS transistors.
- 3. The circuit of claim 1, wherein said regenerative transistor pairs comprise four n-channel CMOS transistors.
- 4. The circuit of claim 1, wherein said switches comprise an n-channel CMOS transistor operated in a common-gate configuration.
- 5. The circuit of claim 1, wherein said pair of loading transistors comprises n-channel CMOS transistors.
- 6. The circuit of claim 1, wherein said regenerative transistor pairs comprise four p-channel CMOS transistors.
- 7. The circuit of claim 1, wherein said switches comprise a p-channel CMOS transistor operated in a common-gate configuration.
Parent Case Info
This application claims benefit of provisional application 60/381,783 filed May 21, 2002.
US Referenced Citations (3)
Provisional Applications (1)
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Number |
Date |
Country |
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60/381783 |
May 2002 |
US |