Patent Application
20190384343
This application claims priority to U.S. patent application Ser. No. 15/993,629, filed on May 31, 2018, entitled “Low Voltage Reference Current Circuit,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
The present invention relates generally to current reference circuits, and more particularly to current reference circuits that operate at low voltages.
Integrated circuit components continue to shrink in size, and demands in battery-powered devices continue to increase. Reference current circuits are widely used in integrated circuits to generate bias currents. However, as supply voltages fall, some commonly used reference current circuits can no longer operate or operate poorly under low voltage conditions. Thus, the supply voltage represents one of the challenges in the design of reference current circuits. Most analog systems are supplied with a battery voltage. Generating a reference current from a battery voltage generally provides good performance in terms of leakage current and output resistance, but with a relatively high power consumption. Generating a reference current from a low supply voltage enables a small silicon area and low power consumption, but requires the use of core devices that have the drawbacks of current leakage and low output resistance. Further, as the supply voltage decreases, conventional reference current circuits may not function properly. Another challenge is the low noise requirement. A low noise reference current circuit requires filter capacitors, however, a gate leakage current flowing through the filter capacitors causes a voltage shift in the current mirror circuit of the reference current circuit, thereby affecting the matching of the current mirror circuit. Yet another challenge is the required accuracy of the reference current circuit. Thus, a low supply voltage faces the problems of a current leakage that can significantly affect a current mirror performance, and a low output resistance of a current mirror may require an output buffer to drive an output load.
Accordingly, there is a need for improved circuits for generating an accurate low-noise current reference with low supply voltages.
Embodiments of the present application provide a novel current reference circuit that operates at a low voltage supply. In one aspect of the present invention, a current reference circuit may include a current source, a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the current source, and an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the drain of the first PMOS transistor. The current reference circuit also includes a first resistive element having a first terminal coupled to a source of the NMOS transistor and a gate of the first PMOS transistor and a second terminal coupled to a ground potential, a second PMOS transistor having a drain coupled to the first supply voltage, and a second resistive element having a first terminal coupled to the first terminal of the first resistive element and a second terminal coupled to the gate of the second PMOS transistor.
In another aspect of the present invention, a current mirror may include a current source, a first p-channel metal oxide semiconductor (PMOS) transistor having a source coupled to a first supply voltage, a gate, and a drain coupled to the first current source, a second PMOS transistor having a source coupled to the first supply voltage, a gate coupled to the gate of the first PMOS transistor, and a drain configured to provide a second current source, and an n-channel MOS (NMOS) transistor having a drain coupled to a second supply voltage, a gate coupled to the first current source, and a source coupled to the gate of the first PMOS transistor.
The following detailed description together with the accompanying drawings will provide a better understanding of the nature and advantages of the present invention.
The accompanying drawings, referred to herein and constituting a part hereof, illustrate embodiments of the disclosure. The drawings together with the description serve to explain the principles of the invention.
The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of the preferred embodiments of the invention, which, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only. The embodiments are described in sufficient detail to enable one of skill in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention.
It will be understood that, when an element or component is referred to as “adjacent to,” “connected to,” or “coupled to” another element or component, it can be directly adjacent to, connected or coupled to the other element or component, or intervening elements or components may also be present. In contrast, when an element is referred to as being “directly connected to,” or “directly coupled to” another element or component, there are no intervening elements or components present between them. It will be understood that, although the terms “first,” “second.” “third,” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
The terms “a”, “an” and “the” may include singular and plural references. It will be further understood that the terms “comprising”, “including”, having” and variants thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, the words “and/or” may refer to and encompass any possible combinations of one or more of the associated listed items.
The use of the terms first, second, etc. do not denote any order, but rather the terms first, second, etc. are used to distinguish one element from another. Furthermore, the use of the terms a, an, etc. does not denote a limitation of quantity, but rather denote the presence of at least one of the referenced items. The terms “current reference circuit,” “current reference device,” “current mirror,” “current mirror circuit,” and “current mirror device” are used interchangeably.
As discussed in the background section, continuing reduction in feature sizes of semiconductor devices provides improvement in device performance in terms of lower power consumption and higher switching speed. MOS transistor performance may be improved by reducing the thickness of the gate dielectric layer. However, a thin gate dielectric layer may result in gate tunneling leakage currents, especially at high supply voltages. Therefore, a semiconductor device may have a core region having a low-voltage power source and an input/output (IO) region having a high-voltage power source. The core region includes core devices that have low-threshold voltages (e.g., 04V to 0.5V), and the IO region includes IO devices that have high-threshold voltages (e.g., 0.9V to 1.0V). The threshold voltage of a MOS transistor is defined as the gate voltage required to turn the transistor on or off depending upon the type of the transistor. As used herein, a high-voltage power source may have a supply voltage that is the battery voltage (e.g., 1.5V to 4.5V), and a low-voltage power source may have a supply voltage that is lower than the battery voltage (e.g., 1.0V or less).
Current mirror circuit 10 works well when the supply voltage Vbatt is sufficient high to provide certain voltage headroom for the p-channel MOS transistors and the current reference source. For example, the p-channel MOS transistors are disposed in the input/output (IO) region of an integrated circuit, the voltage across the drain and source of the p-channel MOS transistor MP1 may be about 1V to be in the saturation region, and the voltage at the current reference source Iref may be greater than 0.5V for its proper operation. That is, current mirror circuit 10 can only functions properly with a supply voltage greater than 1.5V.
Thus, the RC low-pass filter can filter out noise of the current reference source Iref. However, the low-pass filter may cause a gate tunneling current leakage due to the thin gate dielectric layer that adversely affects the current mirroring performance of current mirror circuit 20 when the transistors MP1 and MP2 each are core devices. Further, the current reference source Iref rises with the supply voltage Vcc and affects thus the performance of current mirror circuit 20. Thus, it is desirable to have transistors with higher threshold voltages to reduce current leakage and power consumption by using IO devices for the transistors MP1 and MP2. Unfortunately, IO devices with higher threshold voltages require higher supply voltages.
In one embodiment, the n-channel MOS transistor MN1 is configured to compensate for the variation of the supply voltage Vcc. When the supply voltage Vcc rises, the voltage at the node n1 tends to rise. As the voltage at the node n1 is applied to the gate of the transistor MN1, the transistor MN1 tends to conduct less current, so that the voltage at the node n2 drops resulting in a drop of the drain voltage of first transistor MP1, thereby counteracting the rise of the supply voltage Vcc. The NMOS transistor operates as a negative feedback loop of the current path comprising the first transistor MP1 and the current source Iref of current mirror circuit 30.
In one embodiment, the n-channel transistor (NMOS) MN1 may be a transistor having a low threshold voltage of about 0.4V or lower. In one embodiment, the n-channel transistor MN1 may be a native transistor (e.g., with undoped channel) having a threshold voltage of approximately 0.1V or 0V. In one embodiment, the voltage Vd applied to the drain D3 of the NMOS transistor MN1 may be Vd≥Vg−Vt, where Vd is the voltage applied to the drain of the NMOS transistor MN1, Vg is the voltage applied to the gate of the NMOS transistor MN1, and Vt is the threshold voltage of the NMOS transistor MN1.
In a numerical exemplary embodiment, a current mirror circuit in accordance with the present invention has a supply voltage in the range between 0.9V and 1.0V, a current source in the order of 10 μA, a voltage source-drain of the transistor MP1 is in the range between 0.4V and 0.5V, the voltage at the node n1 is about 0.4V, the voltage at the node n2 is about 0.1V, the current flowing through the resistor R2 is about 10 nA, and the resistive element R2 has a value about 10 MΩ. In one embodiment, since the drain voltage Vd has to be greater than Vg-Vt, where Vt is the threshold voltage of a native NMOS transistor, the drain voltage applied to the NMOS transistor may be chosen to be 0.6V.
Embodiments of the present invention may be utilized advantageously in a variety of applications. For example, the current mirror or the current reference circuit shown in
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is derived to achieve the same purpose may be substituted for the specific embodiments shown. Many modifications of the invention will be apparent to those of ordinary skill in the art. Accordingly, this disclosure is intended to cover any modifications or variations of the invention. It is intended that this invention be limited only by the following claims and their equivalents.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15993629 | May 2018 | US |
| Child | 16557808 | US |
