The present invention relates to the field of electronic integrated circuits. More particularly, the invention relates to a current driver integrated-circuit for high-resolution Light Detection and Ranging (LIDAR) applications.
Late boosts in development of autonomous vehicles, Unmanned Aerial Vehicles (UAV)s such as drones and industrial robots create a huge demand for a short-range environment-sensing interface.
Some prior art methods of driving a laser diode utilize a Bipolar Junction Transistor (BJT) avalanche phenomenon. While these methods potentially result in fast rise times and short pulse width, it requires a number of transistor stages to improve the rise time in every subsequent transistors stage. It is also requires extremely high voltages, on the order of hundreds and even thousand volts to generate an avalanche. Pulse shaping is complex and the efficiency of these methods is rather low, resulting in bulky and excessive heat generating installations, with low Pulse Repetition Frequency (PRF) located within kilohertz scale.
An alternative and simpler approach to drive a laser diode is to charge a capacitor to a predefined voltage, and then activate a switch that discharges the capacitor to the laser diode to generate a light pulse. This approach too requires a relatively high voltage, since the current is developed according to the impedance of the laser diode. The most significant drawback of this method is that switching device/s with extremely short transition and delay times are required.
Furthermore, both of the abovementioned methods require a special technology for integrated circuit implementation such as an expensive avalanche BJT or a gallium nitride (GaN) device with proper drive.
It is an object of the present invention to provide a high and rapid current-sourcing power driver for LIDAR applications that overcomes the drawbacks of the prior art.
Other objects and advantages of the invention will become apparent as the description proceeds.
The present invention is directed to a low voltage sub-nanosecond pulsed current driver for driving current to a load, which comprises:
The current driver may further comprise:
The current driver may further comprise:
The current routing network may comprise three MOSFET power switches, two of which are arranged in parallel to each other and to the load, and the third of which is arrange in series to the load.
The timing sequence provided by the controller may be repeated periodically, on demand.
An additional power transistor may be further connected in series with the load, such that when the additional power transistor is turned off, the impedance of the load path is increased and the current flow via the load is rapidly halted, to thereby reduce turn off delays introduced by stray inductances.
The power switches may be high-voltage 5V-gated LDMOS-2 power transistors having a gate width of 15, 000 μm.
The current sensor may comprise:
The comparator may comprise:
The comparator may further comprise active load current mirror structures and bias currents.
The current driver may further comprise an external clamping voltage rail to which the monolithic clamping diode is connected, for providing an additional low impedance path.
The current sensor may be implemented solely by standard CMOS devices.
The comparator may further comprise isolating rings for increasing noise-immunity of the differential pMOS and nMOS pairs.
The low voltage sub-nanosecond pulsed current driver may be implemented on an integrated circuit (IC).
The load may also be a laser diode configured to emit a light pulse proportional to the current supplied thereto.
The constant current source may be switched to lower amplitude, or completely turned off, depending on the PRF and the desired duty cycle of the load.
The switching frequency of the rectifier may be selected to be sufficiently slower than the width of the load pulse, so that the current source is virtually constant to the pulse generation switches.
In the drawings:
Reference will now be made to embodiments of the present invention, examples of which are provided in the accompanying figures for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods exemplified herein may be employed, mutatis mutandis, without departing from the principles of the invention.
The use of the additional parallel transistor Q2, as opposed to operation with Q1 alone, allows flexible setting of the pulse duration with precise and high time resolution, which cannot be obtained using a single device, due to the relatively long intrinsic delays and response time that are involved with high current devices. The series transistor Q3, when turned off, increases the impedance of the load path so that the current flow is rapidly halted. As will be detailed below, it also assists to overcome the effect of stray inductances that in the practical case, introduces significant turn off delays.
It should be noted that the gating sequence described above (with relation to
As it is an object of the present invention to provide a power driver that is able to supply high-resolution pulse width adjustment, ultra-fast rise and fall times, controllable current amplitude, and it is compatible for IC implementation, there are several challenges associated with the objectives above.
The current routing switches are power MOSFETs with unavoidable intrinsic delay between turn on command and the conduction of the MOSFET channel, td(on). In particular, for power devices that are designed to handle significant current ratings, these delays are on the order of several nanoseconds to some tens of nanoseconds. To achieve time resolution of some hundreds of picoseconds for the pulse width setting, a Vernier method (a time measuring technique) is employed. Two MOSFETs, Q1 and Q2 (
Prior to the turn on phase, MOSFET Q2 is turned off, while MOSFET Q1 is left on. At the point t1 (
MOSFET switch Q1 is the main path for high constant current generated by the current source. To attain high efficiency, the on state resistance of the switch, Rds,on, needs to be as small as possible. According to an embodiment of the present invention, a large MOSFET with low Rds,on is used. However, this comes at the cost of higher drain-source (output) capacitance of the device, CDS. This capacitance imposes finite slew-rate of the voltage build up across the load, which in turn limits the rise time of the current due to stray inductances in series with the load. To achieve high voltage slew-rates, high currents are required from the source. In addition to limiting the slew-rate, the parasitic capacitance CDS resonates with parasitic inductance of the load path, setting up the limit for rise time.
To address these challenges, a current driver according to the present invention is implemented on an integrated circuit design. Adjustable design of the power device, and miniaturization of the whole circuit, i.e. on-chip implementation, allows achieving several goals. Reduction of the parasitic components in the current path, i.e. lower CDS and lower parasitic inductances due to the on-chip interconnections. A better balance between on-resistance and switch output capacitance according to the output requirements and integration of the gate driver with the power switches (Q1-Q3) to facilitate higher driving speeds are achieved.
Fall time of the current pulse through the laser diode depends on the parasitic inductances and the voltage that is applied to the laser diode during its turn off. In conventional current driving methods, a freewheeling diode (a diode connected across an inductor used to eliminate sudden voltage spike seen across an inductive load when its supply current is suddenly reduced or interrupted) is added in parallel to the load to avoid high voltage damage as a result of the residual energy in the stray inductance. However, since the forward voltage of laser diodes is relatively low, if freewheeling is allowed, the turn off time extends and cannot be regulated. It should also be noted that during the turn off period, the current ‘tail’ circulates energy through the load path, which is an undesirable scenario for LIDAR applications.
To overcome this challenge, an additional switch Q3 in the load path is employed. Switch Q3 turns off together with the turn on of Q2 so that any residual current in load path charges the output capacitance of Q3, which in turn boosts the voltage at the drain of Q3. Increased voltage at the drain of Q3 creates a high negative voltage across the parasitic inductance, resulting in rapid turn off time of the load.
Additional effects of parasitic inductances in the presence of current source are instantaneous voltage spikes at the switching nodes. In this circuit, the node prone to this problem is VL2 (numeral 302 in
One way to overcome this challenge is to add an auxiliary Zener diode. This solution however, adds extra parasitic capacitance and in terms of monolithic implementation and requires large silicon area. This problem is addressed, according to the present invention, on a solution based on avalanche rated integrated MOSFETs, which is symbolically represented as numeral 304 in
According to an embodiment of the present invention, the controlled current source is implemented by a half-bridge synchronous rectifier 305 that feeds an inductance to create high output impedance, as shown in
Current driver IC 401 comprises a current source and current routing power MOSFETs (Q1, Q2 and Q3); a synchronous rectifier includes a pMOS high-side switch 402 and an nMOS low-side switch 403; a monolithic clamping diode 405; a current sensor 407; and inductor 408; and a rail-to-rail comparator 409, each of which are explain in detail hereinbelow.
A unique feature of IC implemented driver 401 is the low voltage operation, Vin=5V, while being capable of providing high amplitude current pulses to the load at high PRF. Since the size factor of the design is a valuable merit as well, the half-bridge power-stage is realized by standard 5V CMOS devices. As shown in
The drain voltage 404 of the switches Q1 and Q2 can potentially rise over the rated breakdown voltage of the standard 5V CMOS devices. To guarantee the reliability in terms of overvoltage protection of a high performance power system on-chip, high breakdown voltage Laterally Diffused MOS (LDMOS) power devices are used. According to an embodiment of the present invention, transistors Q1, Q2 and Q3 are implemented symmetrically by a high-voltage 5V-gated nLDMOS power device having a gate width of 15,000 μm.
Another issue associated with power switches is voltage clamping, which is achieved using an avalanche breakdown effect of the LDMOS. A batch of three types of LDMOS transistors with different doping levels and oxide thickness have been fabricated and examined through a life-cycle test. The test forces avalanche conditions with various energy levels, at repetition rates of 1 MHz over four weeks per device. It has been found that in case that the energy levels applied per avalanche do not exceed the safe operating area of the transistor, the device operates under breakdown conditions, without any reliability issues such as drifts, or other oxide memory effects.
To avoid any additional failure risks of the IC implemented driver 401 due to overvoltage at node 404, and to promote IC compatibility for gate drive application, a monolithic clamping diode 405 rated up to 40V is provided. According to an embodiment of the invention, the diode is connected to an external clamping voltage rail (a voltage “rail” refers to a single voltage provided by the power supply unit) 406, thereby providing an additional low impedance path, if needed.
A fully monolithic sub-nanosecond-pulsed current driver design is allowed mainly due to high-performance current sensing. The sensor is required to provide a relatively accurate reading of the current swing from tens milliamps to several amperes, under the frequency range of several MHz.
I
mirror
=I
L
R
on,Q
/R
on,M
=I
L
/M Eq. 1
Given the ratio of M:1 between Q1 and MSFET 501, current mirror 503's current, Imirror is M times smaller than the actual inductor current IL. To convert current Imirror to a voltage suitable for the controller operation, current Imirror is mirrored again to the output of the sensor, and flows through an on-chip poly based resistor Rsense, 504. As a result, the voltage Vsense across Rsense is proportional to inductor current IL. Sensing signal Vsense is expressed, as shown in Eq. 2:
V
sense
=I
mirror
R
sense
=I
L
R
sense
/M Eq. 2
It should be noted that although Q1 and MSFET 501 are implemented by LDMOS power devices, according to an embodiment of the present invention, sensing circuit 407 is implemented by standard CMOS devices only, resulting in better overall size and power consumption. The current mirror is in cascode configuration to increase the output resistance reducing the systematic mismatches. Additionally, current mirror 503's structure and transistor MPT (505) are properly sized and matched to guarantee that a sufficient current can be pulled down, such that the amplifier 502 will be able to force the voltages at nodes VL2 and VSFET to be equal.
Referring once again to
Complementary p-channel and n-channel differential pairs are used at the input stage to accommodate a rail-to-rail operation (a “rail” is a boundary that a signal has to work within). For low input voltages, the differential pMOS pair 601 is biased, amplifying the voltage difference at the input nodes (NIN and PIN). In a complementary manner for high input voltages the differential nMOS pair 602 is biased to amplify the input.
Comparator 409's negative input NIN is connected to the sensed signal Vsense (506 in
In a post layout experiment that was performed, measurements of the comparator resulted in total current consumption of 750 μA from the 5V supply voltage, at an operating frequency of 2.5 MHz. The propagation delay of the comparator was measured to be 8 ns for a slew rate of 2.7V/μs.
To guarantee high matching of both differential pairs for process, voltage and temperature variations, the input pairs 601 and 602 are addressed in the layout stage by using common-centroid technique. Active load current mirror structures 606 and 607 and bias currents 608 and 609 are implemented using inter digitation technique to guarantee proper matching between the transistors. According to an embodiment of the invention, isolating guard rings are added to further increase the noise-immunity of the differential pairs.
A low voltage sub-nanosecond pulsed current driver IC has been designed and fabricated in TS 0.18 μm 5V-gated power management process. The overall die area is 2.56 mm2, the chip layout is shown in
The first step of the experimental validation is to characterize the avalanche ratings of the fabricated LDMOS devices. An experimental life-cycle test that extended to four weeks per device was carried out by feeding the devices with a constant current source, while applying short turn off pulses repeated at 1 MHz. The clamped voltage of the devices was measured continuously to monitor any potential degradation of performance. During this experiment, different current amplitudes were applied to validate the change of the drain-to-source voltage, VDS, rise time. In terms of slew rate and stable avalanche voltage, the best performance including extreme current cases has been achieved for LDMOS-2, as presented in
It should be noted that further increase of the current did not improve the voltage slew rate. This is explained by the limitations of the gate driver and relatively large parasitic inductances in the gate-driving path, present in the experimental setup, which was built of discrete components. According to the obtained results of the different LDMOS devices, a new generation of custom designed LDMOS has been constructed in the driver IC prototype, to attain an avalanche voltage of 18V.
The driver IC was verified with post-layout results using Cadence Spectre simulator, demonstrating a closed-loop operation of the driver architecture. The laser diode was modeled with forward biasing of 2V including the key parasitic elements as shown in
To validate the principle of operation of the driver architecture and to validate the method to shorten the fall time of the laser diode current, a discrete prototype was built and tested as part of the experiment. A constant current source is followed by a network of power switches according to
Although embodiments of the invention have been described by way of illustration, it will be understood that the invention may be carried out with many variations, modifications, and adaptations, without exceeding the scope of the claims.
Number | Date | Country | Kind |
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257786 | Feb 2018 | IL | national |
Filing Document | Filing Date | Country | Kind |
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PCT/IL2019/050211 | 2/25/2019 | WO | 00 |