BACKGROUND
Bandgap references are electronic circuits that ideally provide a fixed output voltage signal used as a reference to other circuitry, such as analog to digital converters (ADCs), voltage regulators, sensors, and the like. Temperature stability of a bandgap reference is often achieved by combining a circuit signal that is proportional to absolute temperature (PTAT) with a signal that is complementary to absolute temperature (CTAT). Existing designs provide an output voltage of about 1.2-1.3 V based on the nominal theoretical 1.22 eV bandgap of silicon at 0° Kelvin based on a voltage difference between two p-n junctions (e.g., ΔVGS). This limits the minimum operating voltage to about 1.4 V in practice. However, stable reference voltages are needed in low-voltage, low-power circuit applications in which supply voltages of 1.0 V or less are available. Existing low-voltage bandgap reference designs are largely incapable of achieving a precision voltage reference from a supply voltage under 1.0 V over a wide temperature range (e.g., −50° C. to +150° C.), while consuming currents below 1 uA. One approach for a low voltage bandgap reference is to use an internal charge pump circuit to boost a low voltage supply to 1.4 V or higher, but this is noisy, adds cost and requires additional circuit area. Other approaches use MOSFET transistors and fractional bandgap references which can operate at low supply voltage levels using current summing circuits. However, these circuits typically suffer from poor accuracy at low currents, have multiple stable operating points at cold temperatures which limit practical operational temperature ranges, and the circuits use large resistors to generate CTAT currents and are thus not area efficient for ultralow power applications. Reverse bandgap circuits can provide robust accuracy across processes, but these approaches also suffer from multiple operating points and are not area efficient. An area efficient approach uses the threshold voltage difference between two transistors (e.g., ΔVT) to generate a Zero Temperature Coefficient (ZTC) reference signal, but this approach suffers from uncontrolled current levels and the accuracy is not robust across processes.
SUMMARY
Described examples provide a bandgap voltage circuit with a first circuit to generate an output voltage as a sum of a first voltage with an amplitude that is proportional to absolute temperature, and a first feedback voltage with an amplitude that is complementary to absolute temperature, a second circuit to generate a voltage having an amplitude that is complementary to absolute temperature, a scaling circuit to generate a second feedback voltage with an amplitude that is a fraction of the voltage of the control terminal, and a regulator circuit to regulate the first feedback voltage according to the second feedback voltage by controlling a first input current of the first circuit and a second input current of the second circuit. Example methods include providing a first current to generate a first feedback voltage across a resistor, providing a second current to generate a CTAT voltage across a transistor, scaling the transistor voltage to generate a second feedback voltage, generating an output voltage as a sum of the first feedback voltage, and a PTAT voltage, and regulating the first feedback voltage according to the second feedback voltage by controlling the amplitudes of the first and second currents. Disclosed examples facilitate robust accuracy across multiple processes for generated CTAT and PTAT voltages over wide temperature ranges, along with controlled circuit current levels to provide improved solutions for low-voltage, low-power applications.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic diagram of a bandgap voltage circuit according to one aspect of the present disclosure.
FIG. 2 is a signal diagram of signal waveforms of a self-cascoded MOSFET circuit as a function of temperature.
FIG. 3 is a signal diagram of signal waveforms of a diode connected bipolar transistor as a function of temperature.
FIG. 4 is a signal diagram of an example output voltage of the bandgap voltage circuit of FIG. 1 as a function of temperature.
FIG. 5 is a flow diagram of a method of generating an output voltage according to another aspect of the present disclosure.
FIG. 6 is a system diagram of an example system including the bandgap voltage circuit of FIG. 1
FIG. 7 is a signal diagram of an example output voltage of the bandgap voltage circuit of FIG. 1 over a first temperature range.
FIG. 8 is a signal diagram of example voltage waveforms of the bandgap voltage circuit of FIG. 1 over the first temperature range of FIG. 7.
FIG. 9 is a signal diagram of example voltages and currents in the bandgap voltage circuit of FIG. 1 at different example temperatures as a function of time.
DETAILED DESCRIPTION
In the drawings, like reference numerals refer to like elements throughout, and the various features are not necessarily drawn to scale. In the following discussion and in the claims, the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are intended to be inclusive in a manner similar to the term “comprising”, and thus should be interpreted to mean “including, but not limited to . . . ” Also, the terms “coupled”, “couple” or “couples” are intended to include indirect or direct electrical or mechanical connection or combinations thereof. For example, if a first device couples to or is coupled with a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via one or more intervening devices and/or connections.
FIG. 1 shows an example bandgap voltage circuit 100. The bandgap voltage circuit 100 includes a first circuit 101, a second circuit 102, and an output node 104 that provides an output voltage VREF. The first and second circuits 101 and 102 are each coupled between a supply node 106 and a reference node 108. In one example, the reference node 108 is a ground reference with a ground or common voltage VSS and the supply node 106 has a positive voltage VDD relative to the voltage VSS, although not a requirement of all implementations. The first circuit 101 includes a self-cascoded transistor circuit 110 with a first transistor 111 of size XN connected in series with a second transistor 112 of size X1. As used herein, a self-cascoded transistor circuit has two or more transistors connected in series with one another, with control terminals of the transistors connected together. In the example of FIG. 1, the gate terminals of the transistors 111 and 112 are connected together, and are connected to the drain of the transistor 111. Other self-cascoded transistor circuit implementations can be used, which include more than two series-connected transistors with control terminals connected together. In the illustrated example, the transistors 111 and 112 are n-channel MOSFETs (e.g., NMOS) of different sizes, but with same gate length and channel width per finger to ensure good matching. In one example, the first transistor 111 has an effective width larger by a factor of “N”. The first circuit 101 includes a first input node 114 that couples the circuit 110 with the supply node 106. The second transistor 112 of the first circuit 101 provides a first output current 115 with an amplitude I1A to a resistor 116. The resistor 116 has a resistance R2, and the resistor 116 controls a first feedback voltage VFB1 according to a current 117 having an amplitude I3. The current 117 is based at least partially on the first output current 115 from the self-cascoded transistor circuit 110. A first feedback node 118 connects the source of the second transistor 112 to the resistor 116.
The self-cascoded transistor circuit 110 is connected between the first input node 114 and the first feedback node 118. The self-cascoded transistor circuit 110 can be any cascode connected transistors, such as the MOSFET transistors 111 and 112 in the example of FIG. 1. The first transistor 111 includes a drain connected to the first input node 114, a source connected to the output node 104, and a gate connected to the first input node 114. The second transistor 112 includes a drain connected to the output node 104, a source connected to the first feedback node 118, and a gate connected to the first input node 114. A regulator circuit 120 is coupled between the supply node 106 and the first input node 114. The regulator circuit 120 provides a first input current 121 with a first amplitude I1 to the first input node 114. Apart from any loss current in the transistors 111 and/or 112, the self-cascoded transistor circuit 110 conducts the first input current 121 to the first feedback node 118 as the first output current 115.
The self-cascoded transistor circuit 110 provides the output voltage VREF as a sum of the first feedback voltage VFB1 and a first voltage, in this case the difference between the gate-source voltages VGS of the transistors 111 and 112 (e.g., VREF=VFB1+ΔVGS, where ΔVGS=VGS2−VGS1, VGS1 is the gate-source voltage of the first NMOS transistor 111, and VGS2 is the gate-source voltage of the second NMOS transistor 112). The first voltage ΔVGS is a PTAT voltage that is proportional to absolute temperature. As used herein, PTAT signals (e.g., PTAT voltage and current signals), are electrical signals that increase with increasing temperature in a generally proportional manner, and PTAT circuits are those that have a positive temperature coefficient (PTC). Also, CTAT signals (e.g., CTAT voltage and current signals), are electrical signals that decrease with increasing temperature in a generally proportional manner, and CTAT circuits are those that have a negative temperature coefficient (NTC). The regulator circuit 120 provides the first input current 121 to the first input terminal 114, and the self-cascoded transistor circuit 110 provides the corresponding current 115 that controls the amplitude of the first feedback voltage VFB1 at the first feedback node 118.
The regulator circuit 120 also provides a second input current 122 to the second circuit 102. The second input current 122 has an amplitude I2. The regulator circuit 120 includes a first regulator transistor 124 connected between the supply node 106 and the first input terminal 114 of the self-cascoded transistor circuit 110. In one example, the first regulator transistor 124 is a p-channel MOSFET (e.g., PMOS) transistor with a source connected to the supply node 106, a gate terminal connected to a control node 126, and a source terminal. Other types and forms of mirror circuit transistors can be used in other implementations. The source terminal of the first regulator transistor 124 is connected to the first input terminal 114 to provide the first input current 121 to the first circuit 101.
The regulator circuit 120 also includes an amplifier 128 with an output connected to the control node 126. The amplifier 128 controls the first amplitude I1 of the first input current 121, and the second amplitude I2 of the second input current 122, according to the difference between the first feedback voltage VFB1 and a second feedback voltage VFB2 from the second circuit 102. The amplifier 128 provides a closed-loop that regulates the first feedback voltage VFB1 according to the second feedback voltage VFB2 by controlling the first input and second input currents 121 and 122 provided to the first and second circuits 101 and 102, respectively. The second circuit 102 includes a second input node 130 that connects a second current regulator transistor 132 with a transistor 134 between the supply node 106 and the reference node 108. The second regulator transistor 132 is a p-channel MOSFET (e.g., PMOS) transistor with a source connected to the supply node 106, a gate terminal connected to the control node 126, and a source terminal that provides the second input current 122 to the second circuit 102. In one example, the second regulator transistor 132 is the same size as that of the first regulator transistor 124. In another example, the second regulator transistor 132 is larger than the first regulator transistor 124, such as twice as large.
In one example, the transistor 134 of the second circuit 102 is an NPN, diode connected bipolar transistor, although other types and forms of transistor can be used in different implementations. In the illustrated example, the collector and base control terminal of the transistor 134 are connected to the second input node 130, and the emitter of the transistor 134 is connected to the reference node 108. The diode-connected NPN bipolar transistor 134 provides the base-emitter voltage VBE to the control terminal at the second input node 130 with an amplitude that is complementary to absolute temperature (CTAT). As used herein, PTAT or “proportional to absolute temperature” or “proportional to temperature” characterizes a device or a circuit that provides or controls a signal, such as a current or voltage, in a manner that increases or decreases generally proportional to an increase or decrease in absolute temperature, respectively. For example, the amplitude of a PTAT voltage signal increases with increasing temperature, and decreases with decreasing temperature. Similarly, a transistor or circuit with a PTAT characteristic generates a signal that increases with increasing temperature, and decreases with decreasing temperature. As used herein, CTAT or “complementary to absolute temperature” or “complementary to temperature” characterizes a device or a circuit that provides or controls a signal, such as a current or voltage, in a manner that increases or decreases inversely with an increase or decrease in absolute temperature, respectively. For example, the amplitude of a CTAT voltage signal decreases with increasing temperature, and increases with decreasing temperature. Similarly, a transistor or circuit with a CTAT characteristic generates a signal that decreases with increasing temperature, and increases with decreasing temperature.
The second circuit 102 further includes a scaling circuit 136 coupled between the transistor 134 and the reference node 108. The scaling circuit 136 includes a second feedback node 138 having the second feedback voltage VFB2. In operation, the scaling circuit 136 scales a base-emitter voltage VBE of the diode-connected transistor 134 to provide the second feedback voltage VFB2 with an amplitude KVBE that is a fraction of the voltage VBE of the control terminal 130 (e.g., VFB2=KVBE). The scaling circuit 136 includes a first divider resistor 140 with a resistance R1 connected between the second input node 130 and the second feedback node 138. The first divider resistor 140 includes a first terminal connected to the second input node 130, and a second terminal connected to the second feedback node 138. The scaling circuit 136 also includes a second divider resistor 142 with a resistance R2 connected between the second feedback node 136 and the reference node 108. The second divider resistor 142 includes a first terminal connected to the second feedback node 138, and a second terminal connected to the reference node 108.
The resistive voltage divider circuit formed by the series connection of the resistors 140 and 142 between the control terminal of the transistor 134 and the reference node 108 scales the base-emitter voltage VBE of the diode-connected transistor 134. The second feedback node 138 that joins the resistors 140 and 142 generates the second feedback voltage VFB2 with the amplitude KVBE. In this example, K is a scaling factor representing the ratio R1/(R1+R2). In one example, the resistor 116 of the first circuit 101 has a resistance R2 equal to the resistance R2 of the second divider resistor 142, although not a strict requirement of all possible implementations. Although the illustrated scaling circuit 136 is a resistive divider, other forms and types of scaling circuits can be used in other implementations that generate the second feedback voltage VFB2 is a fraction of the transistor voltage VBE of the second circuit 102.
The scaling circuit 136 provides the second feedback voltage VFB2 at the second feedback node 138. The second feedback node 138 is connected to an inverting input (−) of the amplifier 128. The non-inverting input (+) is connected to the first feedback node 118 to receive the first feedback voltage VFB1. The amplifier 128 includes an output terminal connected to the gate control terminals of the first and second regulator transistors 124 and 132 at the control node 126. The amplifier 128 provides an output voltage according to the difference between the first and second feedback voltages VFB1 and VFB2. The voltage at the control node 126 controls the first amplitude I1 of the first input current 121, and the second amplitude I2 of the second input current 122.
The regulator circuit 120 provides closed loop control of the first input current 121, which in turn affects the current 117 through the first circuit resistor 116. The negative feedback of the scaled CTAT voltage represented by the second feedback voltage (VFB2=KVBE) regulates the current first feedback voltage VFB1 to be generally equal to the second feedback voltage VFB2. As previously mentioned, the output voltage VREF is generated by the first circuit 101 as the sum of VFB1 and the gate-source voltage VGS of the transistor 112 (e.g., VREF=VFB1+VGS). In this regard, the closed-loop regulation of the first feedback voltage VFB1 to be equal to the second feedback voltage (VFB1=VFB2=KVBE) causes the first feedback voltage at the first feedback voltage node 118 to be a CTAT signal that generally decreases with increasing circuit temperature. At the same time, the gate-source difference voltage ΔVGS of the transistors 111 and 112 is a PTAT signal with an amplitude that varies proportional to absolute temperature (e.g., increases with increasing temperature). Thus, the bandgap voltage circuit 100 provides the output voltage VREF with a generally zero temperature coefficient (ZTC) having a generally temperature independent value. In addition, the scaling of the CTAT feedback through the scaling circuit 136 facilitates low-voltage operation of the circuit 100. In addition, the ZTC characteristic of the output voltage VREF is robust across different processes. In these respects, the bandgap voltage circuit 100 of FIG. 1 provides improvements over conventional designs, particularly for low-voltage, low-power applications. Moreover, the example circuit 100 does not require supply voltage boost circuitry, and provides a robust efficient solution for applications with supply voltages of 1.0 V or less.
The current/voltage (I-V) relationship for the self-cascoded MOSFETs (e.g., the transistors 111 and 112 of the self-cascoded circuit 110 in FIG. 1) operating in a sub threshold region is given by the following equations (1) and (2):
In these formulas, Cox is a capacitance of the MOSFET gate oxide, Cd is the MOSFET depletion capacitance, Vgs is the gate-source voltage, Vds is the drain-source voltage, VT is the thermal voltage, and Vth is the threshold voltage, where Vds>4.7 VT ensures <1% loss of accuracy. For the same current (e.g., I1 in FIG. 1) through the MOSFETs 111 and 112, ΔVGS=VGS1−VGS2=mVT ln(N), which exhibits a PTAT characteristic. In one example, the scaling circuit 136 and the transistor 134 control the current 121 flowing through the self-cascoded transistors 111 and 112, and the length and width dimensions of the transistors 111 and 112 is designed large enough such that the transistors 111 and 112 operate at sub threshold bias current levels for the provided current 121. The bipolar transistor voltage VBE includes a nonlinear third term which varies as a logarithmic function of temperature in a CTAT fashion, as shown in equations (3), (4), and (5) below.
The self-Cascoded MOSFETs 111 and 112 achieve ΔVGS while generally carrying the same current 121 (e.g., the current 121 and the current 115 are substantially equal, other than leakage currents). Consequently, example implementations do not need current mirrors and any associated errors can be mitigated or avoided. Certain examples can include compensation circuitry 150, such as a current source 152 and a current mirror circuit 156, 158, although not required of all possible implementations. The currents generated in the legs of the second circuit (e.g., the bipolar transistor leg, and the resistive divider leg) are CTAT (e.g., the current 122 is determined according to VBE/(R1+R2), where the voltage VBE has a CTAT characteristic). Accordingly, the current 122 decreases with increasing temperature, and increases with decreasing temperature. As discussed below in connection with FIGS. 5 and 6, moreover, the compensation circuitry 150 can be used in specific implementations to facilitate compensation for any leakage current of the transistors 111 and/or 112 by sinking a second compensation current 162, having a PTAT amplitude I4, from the first feedback node 118. In addition, the ΔVGS and VBE values are weak functions of the currents flowing through the corresponding first and second circuits 101 and 102, and accordingly current variations do not have any significant adverse impact on the bandgap voltage accuracy.
Referring also to FIGS. 2-4, simulation results for the example bandgap voltage circuit 100 illustrate robust accuracy across different processes. FIG. 2 shows a signal diagram with a graph 200 including curves 201, 202 and 203. The curves 201-203 illustrate PTAT temperature variance of the gate-source voltage difference between the self-cascoded circuit transistors 111 and 112 in FIG. 1 (e.g., ΔVGS). The curve 201 represents a circuit 100 simulated for fabrication with a first fabrication process, the curve 202 represents a circuit 100 simulated for a different second process, and the curve 203 represents a circuit 100 simulated for a different third process. The curves 201-203 have similar PTAT characteristics to one another, where each begins from or near a nominal value labeled “Z” on the vertical axis, and vary in similar proportion to one another, increasing proportionally with increasing temperature. The vertical axis in FIG. 2 includes scale markings labeled “Y” and “Z” above and below the Z value for reference. The curves 201-203 demonstrate that the self-cascoded circuit 110 in the example circuit 100 has robust PTAT performance across multiple processes.
FIG. 3 shows a signal diagram with a graph 300 that includes curves 301, 302 and 303. The curves 301-303 illustrate CTAT temperature variance of the scaled base-emitter voltage (e.g., KVBE) of the diode-connected bipolar transistor 134 in the second circuit 102 of FIG. 1 for three processes corresponding to the curves 201-203, respectively, in FIG. 2. The CTAT curves 301-303 have similar CTAT characteristics to one another, where each curve 301-303 begins from or near a nominal value labeled “Z” on the vertical axis, and vary in similar proportion, decreasing proportionally with increasing temperature. The vertical axis scale markings labeled “Y” and “Z” in FIG. 3 represent the same scaling as used in FIG. 2. The curves 301-303 show that the example second circuit 102 in FIG. 1 has robust CTAT performance across multiple processes.
In addition FIG. 4 is a signal diagram with a graph 400 showing an output voltage curve 402 (VREF) at the output node 104 in FIG. 1. The curve 402 represents all three modeled processes corresponding to the curves in FIGS. 2 and 3, and is basically flat, showing that the overall bandgap voltage circuit 100 provides a stable temperature independent reference voltage with high accuracy over a wide temperature range as well as robustness across processes. As illustrated in FIG. 2-4, the thermally stable operation of the circuit 100 over a wide temperature range (e.g., −50° C. to +150° C.) comes from the robustness of the generated CTAT and PTAT signals in the circuit 100. In addition, the example bandgap voltage circuit 100 facilitates low-voltage, low-power operation by controlled current levels in the circuit.
The bandgap voltage circuit 100 facilitates low-voltage operation by scaling down the CTAT voltage VBE generated by the bipolar transistor 134, and adding the scaled CTAT voltage to the PTAT voltage ΔVGS of the self-cascoded sub-threshold MOSFET transistors 111 and 112 through the closed-loop operation of the regulator circuit 120 using the scaled CTAT voltage KVBE as negative feedback. The example circuit 100 operates over a wide temperature range, unlike the current summing bandgap design or other low voltage CMOS reference designs, while maintaining good accuracy across multiple processes, supply voltages and temperatures (robust with respect to PVT). The disclosed examples 100 provides a bandgap design solution with robustness and accuracy, along with the ability to operate at low supply voltages, while providing circuit area economy without charge pump voltage boosting circuitry or other additional circuits.
The example circuit 100 of FIG. 1 also includes a compensation circuit 150 to provide further temperature stability. In other implementations, the compensation circuit 150 can be omitted. The example compensation circuit 150 includes an output node connected to the first feedback node 118 to offsets the I3 current 117 provided to the first circuit resistor 116 by sinking a PTAT current from the first feedback node 118. The compensation circuit 150 includes a current source 152 coupled between the supply node 106 and the reference node 108. The current source 152 has an output node that generates a first compensation current 154. The first compensation current 154 has a PTAT first amplitude, labeled IPTAT in FIG. 1, which is proportional to absolute temperature PTAT. Any suitable PTAT current source 152 can be used. The example compensation circuit 150 also includes a first current mirror transistor 156 (e.g., an NMOS) connected between the current source 152 and the reference node 108, as well as a second current mirror transistor 158 (e.g., NMOS) connected between the first feedback node 118 and the reference node 108. The output terminal of the current source 152, and the gate control terminals of the current mirror transistors 156 and 158, are connected to a control node 160. The second current mirror transistor 158 sinks a second compensation current 162 from the first feedback node 118. The second compensation current 162 has a second amplitude I4 that is proportional to the first amplitude IPTAT, and has a PTAT characteristic.
In the example of FIG. 1, the PTAT current source 152 includes an upper current mirror circuit formed by PMOS transistors 164 and 166, as well as a lower NMOS current mirror formed by the transistor 156 and a lower NMOS transistor 168. A right circuit branch or circuit leg in the current source 152 includes the series connection of the transistors 156 and 166 between the supply node 106 and the control node 160. The first feedback node 118 connects the drains of the transistors 156 and 166 to one another. A left circuit branch or leg includes the series connection of the transistors 164 and 168, as well as a resistor 170 with a resistance RS between the supply node 106 and the reference node 108. The right circuit branch conducts the PTAT output current 154 (IPTAT).
In one example, the regulator transistors 132 and 124 are sized with a ratio of 1:2 as shown in FIG. 1, and the compensation circuit 150 can be omitted. In a second example, the bandgap voltage circuit includes the compensation circuit 150, and the regulator transistors 132 and 124 are sized with a ratio of 1:1. In a third example, regulator transistors 132 and 124 are sized with a ratio of 1:1, but instead of the compensation circuit including the NMOS transistor 158 sinking a PTAT current from the current 115, the compensation circuit 150 instead includes a PMOS transistor that sources a PTAT current into the bipolar transistor 134. As shown in FIG. 1, assuming a very high impedance at the non-inverting input of the amplifier 128, the current I3 across the resistor 116 is equal to the first output current 115 (I1A) minus the compensation current 162 (I4). In operation, the compensation circuit 150 sinks the PTAT compensation current 162 from the feedback node 118. The circuit 150 facilitates conduction of additional drain current in the MOSFET transistors 111 and 112, particularly at high temperatures, to offset any effects related to increased MOSFET leakage currents or reduced Vds of transistor 111 due to reduced Vgs, at high temperatures. With a 1:1 sizing of the regulator transistors 124 and 132, the current through R1 and R2 is equal to the current 115. The current through the bipolar resistor 134 is equal to the compensation current 162. Ensuring a PTAT current through the BJT reduces the non-linear curvature error term in the CTAT VBE voltage signal.
Referring now to FIGS. 5 and 7-9, FIG. 5 shows an example method 500 to generate an output voltage. FIG. 7 shows example output voltage of the bandgap voltage circuit 100 of FIG. 1 over a first temperature range, and FIG. 8 shows example voltage waveforms of the bandgap voltage circuit 100 over the first temperature range. FIG. 9 shows the response of example voltages and currents in the bandgap voltage circuit 100 to temperature changes as a function of time.
The method 500 of FIG. 5 can be implemented in a variety of bandgap circuits, such as the bandgap voltage circuit 100 of FIG. 1. The method 500 is implemented as a continuous closed loop, including providing a first current at 502 (e.g., current 121 or 115 in FIG. 1 from the first circuit 101 to the first feedback node 118) to generate a first feedback voltage across a resistor (e.g., voltage VFB1 across the resistor 116 in FIG. 1). At 504, the method 500 includes providing a second current (e.g., current 122) to generate a voltage across a diode connected bipolar transistor with an amplitude (e.g., CTAT voltage VBE across the transistor 134). The method 500 continues at 506 with scaling the voltage VBE to generate a second feedback voltage (e.g., the second feedback voltage VFB2) with an amplitude that is a fraction of the transistor voltage amplitude (e.g., KVBE). The method 500 further includes generating an output voltage at 508 (e.g., VREF) in the first circuit 101 as a sum of the first feedback voltage and a first PTAT voltage (e.g., VFB1+VGS). At 510, the method 500 includes regulating the first feedback voltage (e.g., VFB1) according to the second feedback voltage by controlling the amplitude I1 of the first input current 121, and the amplitude I2 of a second input current 122 of the second circuit 102. In one example, the method 500 proceeds again to 502 as described above. In another example, the method 500 also includes sinking a compensation current (e.g., compensation current 162 in FIG. 1) from the first feedback node 118 at 512, where the compensation current 162 has a PTAT amplitude (e.g., I4 in FIG. 1).
Referring also to FIG. 6, the example circuits 100 and methods 500 can be used in a variety of different host circuits and systems to provide a stable reference voltage. FIG. 6 shows one example battery system 600 that includes a supply source 602, such as a battery, which is connected to the supply node 106. The output node 104 is connected to the input terminal of a buffer amplifier 604, and a buffer amplifier output terminal 606 is connected to an ADC 610. The ADC 610 has an analog input terminal 608 that receives an analog input signal to be converted. The ADC 610 has an output terminal or bus 612 that provides a converted digital value to a host processor 614. In other example systems, the buffer amplifier output 606 is connected to a voltage regulator, a sensor, or another host circuit component or components (not shown). The output node 104 provides the output voltage VREF as an input signal to the buffer amplifier 604. The buffer amplifier provides a stable buffered voltage signal as an input to the ADC, voltage regulator, sensor, or other host circuit component. For example, the buffered reference voltage can be used by a host ADC circuit for comparison with an input voltage signal to be converted to a digital value. In certain examples, the buffer amplifier can be omitted, and the output node 104 is connected directly to the ADC, voltage regulator, sensor, or other host circuit component to provide the output voltage VREF as an input signal thereto. The bandgap voltage circuit 100 is beneficial for low quiescent current conditions, such as in the system 600 that operates on battery or limited power.
Referring also to FIGS. 7-9, FIG. 7 shows a signal diagram 700 with an example bandgap voltage circuit output voltage signal curve 702 (e.g., VREF in FIG. 1) over a range from a first temperature T1 to a second temperature T2. FIG. 8 shows a signal diagram 800 with a curve 802 of the second input node voltage VBE having a CTAT characteristic from T1 to T2 (e.g., decreasing with increasing temperature). A curve 804 in FIG. 8 shows an example first voltage (e.g., ΔVGS) of the first circuit 101 with a PTAT characteristic (e.g., increases with increasing temperature), and a curve 806 shows the CTAT scaled voltage signal KVBE. In the example of FIGS. 7 and 8, the variation of VREF (curve 702) from the nominal value VNOM is less than 0.2 mV over the range from T1 to T2 due to the regulation of the currents 121 and 122 according to the influence of the PTAT first voltage ΔVGS on the first feedback voltage VFB1, and the CTAT influence of the bipolar transistor voltage VBE on the second feedback voltage VFB2.
FIG. 9 is a signal diagram of example voltages and currents in the bandgap voltage circuit 100 of FIG. 1 at different example temperatures as a function of time. A curve 902 shows the supply voltage VDD at the supply node 106 in FIG. 1 and a curve 904 shows the bandgap voltage circuit output voltage signal curve (e.g., VREF in FIG. 1). A curve 906 shows the circuit temperature, which rises in steps over time after the circuit 100 is powered on at −50 degrees C. Curve 908 show the first input current 121 (I1) provided by the first regulator transistor 124 to the self-cast coated transistor circuit 110, and curve 910 shows the second input current 122 (I2) provided by the second regulator transistor 132 to the transistor 134 of the second circuit 102. Both the currents in curves 908 and 910 are controlled by the amplifier 128 in FIG. 1 based on the difference between the voltages at the feedback nodes 118 and 138.
A curve 912 shows the current 117 (I3) through the resistor 116 of the first circuit 101, which establishes the first feedback voltage VFB1. A curve 914 shows the second compensation current 162 (I4) sinked from the first feedback node 118 by the compensation circuit 150 in the example of FIG. 1. A curve 916 in FIG. 9 shows the voltage VBE at the second input node 130, which is established by the second input current 122 (I2) and the operation of the bipolar transistor 134, and a curve 918 shows the scaled voltage provided as the second feedback voltage VFB2=KVBE. Because the transistor 134 exhibits a complementary to absolute temperature (CTAT) operating characteristic, the voltages shown by the curves 916 and 918 decrease with increasing temperature. In this example, since the temperature (curve 906) increases in a stepwise fashion, the second feedback voltage curve 918 decreases in stepwise fashion.
FIG. 9 also shows a curve 920 that represents the gate-source voltage difference ΔVGS of the transistors 111 and 112 of the self-cascoded transistor circuit 110. As previously discussed, this voltage difference of the circuit 110 exhibits a proportional to absolute temperature (PTAT) characteristic, and the curve 920 accordingly increases in stepwise fashion with increasing temperature. The first feedback voltage VFB1 at the first feedback node 118 is shown by curve 922 in FIG. 9, with a CTAT characteristic that decreases with increasing temperature. The cumulative effect of the CTAT characteristic of the bipolar transistor 134 in the second circuit 102, combined with the PTAT ΔVGS characteristic of the self-cascoded transistor circuit 110 provides a generally stable output voltage VREF=ΔVGS+KVBE at the output node 104 that is substantially independent of the temperature of the circuit 100.
The above examples are merely illustrative of several possible embodiments of various aspects of the present disclosure, wherein equivalent alterations and/or modifications will occur to others skilled in the art upon reading and understanding this specification and the annexed drawings. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
Patent Application
20200142438
