Patent Application
20090184766
The present invention relates generally to integrated circuits, and more particularly relates to transconductor devices.
Transconductance is often an important measure of performance parameters including, but not limited to, bandwidth, gain, and noise. Transconductance is an expression of the performance of certain electronic circuits, and traditionally refers to the ratio of output current to input voltage of a particular circuit, or mutual conductance. The term “transconductance” refers to herein as the control of an output current as a result of an input voltage.
In integrated circuits, it may be important for the transconductance, also generally referred to as Gm, of an electronic circuit to remain constant over one or more operating parameters as well as processing variations. The stability or robustness of transconductane of transistors may be an important design parameter, as it may be affected by many operation and processing conditions, such as temperature, carrier mobility, supply voltage, etc.
Transconductors, also generally referred to as Gm Cells, are typically important building blocks in any circuit design. Generally, transconductors are widely used in applications, such as Gm-C filters, Sigma-delta modulators, multipliers and so on. Also generally, in these applications, transconductors are key components that can limit a required dynamic range.
One conventional solution, i.e., a Gm Cell having the most wide linear operating range is shown in
However, it can be seen that the Gm Cell 100 shown in
A low-voltage, low-power, wide range, and linear transconductor cell is disclosed. According to an aspect of the subject matter, the Gm Cell includes an emitter degenerated input stage, a compression stage, a Caprio circuit, a current biasing circuit, and a current mirror output stage. The emitter degenerated input stage is formed by transistors Q1 and Q4 and resistors R1 and R2, receives an input differential voltage from signal input terminals VinP and VinM by the emitter degenerated input stage and outputs a current including a linear part and a nonlinear part at signal output terminals Iout_P and Iout_M.
The compression stage formed by the transistors Q2, Q3, Q9 and Q10 converts the non-linear part of the output current received from the emitter degenerated input stage to a voltage difference between emitters of the transistors Q9 and Q10. Then, the Caprio circuit formed by transistors Q5, Q8, Q11 and Q12 converts the voltage difference between the emitters of the transistors Q9 and Q10 to a linear output current. The current mirror output stage formed by transistors Q6 and Q7 outputs the linear output current to the signal output terminals Iout_P and Iout_M. In some embodiments, the linear output current through transistors Q5 and Q8 is mirrored out by the transistors Q6 and Q7. Further, the output currents of the emitter degenerated input stage and the Caprio circuit are summed at the signal output terminals Iout_P and Iout_M to obtain a linear output current with the input differential voltage. In some embodiments, the transistor Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 are of the same type of transistors. In addition, the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 are CMOS transistors and/or bipolar transistors.
Example embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements and in which:
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.
A novel technique for a low-voltage, low-power, wide-range, and linear Gm Cell is disclosed. In the following detailed description of the embodiments of the invention, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
The terms “transconductance” and “Gm” are used interchangeably throughout the document. Further, the terms “transconductor cell” and “Gm Cell” are used interchangeably throughout the document.
As shown in
The Caprio circuit 130 is formed by transistor Q5, Q6, Q7, Q8 and resistors R3 and R4, where R3=R4=R1=R2. The Caprio circuit 130 converts the voltage difference between the emitters of the transistors Q3 and Q4 to a linear current that is superimposed on the emitter degenerated input stage 110, resulting in a linear output current over very wide range for the Gm Cell 100.
The emitter follower stage 140 is formed by transistors Q9 and Q10. The emitter follower stage shifts an input voltage at the same output voltage level for cascading connections. The current biasing circuit 150 is formed by transistors Q13, Q14, Q15, Q16, Q17, Q18 and resistors R5, R6, R7, R8, R9. As shown in
As shown in
In operation, the Gm Cell 100 requires a supply voltage of at least 3V in order to keep all the transistors in a linear region. The voltage VB coupled to the compression stage 120 requires at least 3*Vbe+Vce,sat volts, which is around 2.4V. For example, if the loading circuitry needs 0.6V to stay in high-Z (Impedance) mode, then the supply voltage requires 3V, which does not include the extra room that is required for an output swing. Therefore, it can be seen that the Gm cell 100 shown in
As shown in
Further as shown in
The Gm Cell 200 also includes the compression stage 220 coupled to the supply voltage terminal AVDD, the signal input terminals VinP and VinM, and the Caprio circuit 230. The compression stage 220 includes a second transistor Q2, a third transistor Q3, a ninth transistor Q9 and a tenth transistor Q10.
Further, the Gm Cell 200 includes the current biasing circuit 240 coupled to the emitter degenerated input stage 210, the Caprio circuit 230, a supply voltage terminal AVSS and a current input terminal IB. The current biasing circuit 240 includes a fourteenth transistor Q14. Also, the current biasing circuit 240 includes a thirteenth transistor Q13, a fifteenth transistor Q15, and a sixteenth transistor Q16 and associated fifth resistor R5, a sixth resistor R6 and a seventh resistor R7, respectively.
In addition, the Gm Cell 200 includes the current mirror output stage 250 coupled to the signal output terminals Iout_P and Iout_M. The current mirror output stage 250 includes transistors Q6 and Q7.
As shown in
Further, each of the thirteenth, fifteenth and sixteenth transistors Q13, Q15 and Q16 includes an associated first electrode, second electrode and control electrode. In some embodiments, the second electrode of the fourteenth transistor Q14 is coupled to the control electrodes of the thirteenth transistor Q13, the fifteenth transistor Q15 and the sixteenth transistor Q16.
As shown in
Further, each of the first transistor Q1 and the fourth transistor Q4 in the emitter degenerated input stage 210 has an associated input electrode, second electrode and control electrode, and each of the first resistor R1 and the second resistor R2 in the emitter degenerated input stage 210 has an associated input and output. As shown in
Further as shown in
Further as shown in
Further, the first electrode of the seventh transistor Q7 is coupled to the signal output terminal Iout_P, the control electrode of the seventh transistor is coupled to the control electrode of the eighth transistor Q8, the second electrode of the seventh transistor Q7 is coupled to the output of the fourth resistor R4, the first electrode of the eighth transistor Q8 is coupled to the second electrode of the twelfth transistor Q12 and the control electrode of the fifth transistor Q5, the second electrode of the eighth transistor Q8 is coupled to the output of the fourth resistor R4, the control electrode of the eighth transistor Q8 is further coupled to the first electrode of the fifth transistor Q5 and the second electrode of the eleventh transistor Q11, the first electrode of the twelfth transistor Q12 is coupled to the supply voltage terminal AVDD, the control electrode of the twelfth transistor Q12 is coupled to the second electrode of the tenth transistor Q10 and the first electrode of the third transistor Q3, and the output of the third resistor R3 is coupled to the input of the fourth resistor R4.
In some embodiments, the transistor Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 are of the same type of transistors. In addition, the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, and Q16 are CMOS transistors and/or bipolar transistors.
In operation, an input differential voltage from the signal input terminals VinP and VinM is received by the emitter degenerated input stage 210 and a current including a linear part and a nonlinear part is outputted at the signal output terminals Iout_P and Iout_M. The non-linear part of the output current received from the emitter degenerated input stage 210 is converted to a voltage difference between the emitters of the transistors Q9 and Q10 by the compression stage 220. Further, the voltage difference between the emitters of the transistor Q9 and Q10 is converted to a linear output current by the Caprio circuit 230.
In operation, the linear output current is outputted using the current mirror output stage 250 to the signal output terminals Iout_P and Iout_M. Finally, the output currents of the emitter degenerated input stage 210 and the Caprio circuit 230 are summed at the signal output terminals Iout_P and Iout_M to obtain a linear output current with the input differential voltage. In these embodiments, the linear output current through the transistors Q5 and Q6 is mirrored out by the transistors Q6 and Q7 and then superimposed on the emitter degenerated input stage 210, resulting in a linear current-voltage (I-V) conversion over very wide range of input voltage for the Gm Cell 200. In some embodiments, the emitter areas of the transistors Q1 (AE1), Q2 (AE2), Q3 (AE3), Q4 (AE4), Q5 (AE5), Q6 (AE6), Q7 (AE7), and Q8 (AE8) are sized such that AE1/AE2=AE4/AE3=AE6/AE5=AE7/AE8. In some embodiments, the transistor Q9 and Q10 are of the same type. Further, the transistors Q9 and Q1 are CMOS transistors and/or bipolar transistors.
In accordance with the above described procedure, the Gm Cell 200 requires a supply voltage AVDD of about 3*Vbe+Vce,sat, which is around 2.4V. In one embodiment, the input is directly biased at the same voltage level (AVDD) as the output voltage (e.g., VDD/2=2.4/2=1.2), thus getting rid of the input emitter follower. Hence, the Gm Cell 200 operates at a lower voltage.
In accordance with the above described embodiments, the Gm Cell 100 and the Gm Cell 200 are simulated with the same total biasing current (100 μA) for the same transconductance (50 μS). For example, for Gm Cell 100, the VB is biased at 2.5V and the supply voltage is 4V, whereas for the Gm Cell 200 (S-cell), the supply voltage is 2.4V.
In summary, the following observations can be made:
Although the present embodiments have been described with reference to specific example embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the various embodiments. For example, the various devices, modules, analyzers, generators, etc. described herein may be enabled and operated using hardware circuitry (e.g., CMOS based logic circuitry), firmware, software and/or any combination of hardware, firmware, and/or software (e.g., embodied in a machine readable medium). For example, the various electrical structure and methods may be embodied using transistors, logic gates, and electrical circuits (e.g., application specific integrated ASIC circuitry).
