Patent Grant
8810189
Example embodiments relate to pre-power diagnostics of inverter-fed machine systems for real-time failure detection, such as in the field of electric and hybrid vehicles and equipment.
It is known for a drive system for an electric or hybrid vehicle to have an engine (e.g., internal combustion engine), a generator coupled to the engine, a Direct Current (DC) bus, and a motor. The DC bus is coupled electrically between the generator and the motor to drive one or more elements of the vehicle. A converter is coupled electrically between the generator and the DC bus and is controlled to convert Alternating Current (AC) power into DC power during generating of the generator and DC power into AC power during motoring of the motor. The motor can be a Switched Reluctance (SR) motor, a Permanent Magnet (PM) AC Motor or an Induction AC Motor.
In an inverter-fed drive system, a power inverter is coupled electrically between the DC bus and the motor and is controlled to convert DC power from the DC bus into AC power during motoring of the motor and to convert AC power into DC power during electric braking of the motor. In vehicles with regenerative braking, the inverter also takes power from the motor (now acting as a generator) and stores it in batteries. A voltage sensor is coupled electrically to the DC bus to sense a DC bus voltage and output a DC bus voltage signal indicative thereof. A current sensor senses a phase current of the motor and outputs a phase current signal indicative thereof. A control system is coupled electrically to the voltage sensor and the current sensor to receive signals from the sensors pertaining to system operation.
In an inverter-fed electric drive system, it can be appreciated that a variety of failures can occur in the various power and control components used in the systems, such as, Insulated Gate Bi-polar Transistors (IGBTs) in the inverters, diodes in the inverters, electric machines, motor windings, dc bus capacitors, power cables between inverters and electric machines, etc.
Example embodiments propose a novel monitoring and control technique for inverter-fed machine systems. Pre-power diagnostics of electric machinery done at low voltage levels can detect incipient failures before the system is operated under full power, significantly reducing the cost of maintenance and the risk of unexpected failures at high voltage. In example embodiments, a failure may include an open circuit or a failure and is not limited to these two types of failures.
Example embodiments disclose at least two different methods that can be used for pre-power diagnostics of the system. A first method, which may be used for PM, Induction, or SR motors, utilizes measurements of sensed signal levels to determine if there is a failure in the system. It should be understood that “signal level” may refer to either a measured phase voltage or a measured phase current. It is possible to convert a measured phase voltage to a phase current with a transconductance amplifier or transresistance amplifier (e.g., op-amplifier plus a resistor). For the sake of brevity, the first method is described using measured phase currents as the signal levels. However, it should be understood that the first method may be implemented using measured phase voltages.
A second method, for systems having PM, Induction, or SR motors, utilizes measurements of sensed voltage at the AC mid-point voltage measured between high-side and low-side devices in an inverter leg with respect to the negative DC bus to determine if there is a failure in the system. The sensed voltages are processed in the Analog-to-Digital Converter (ADC) that is built into the Gate Drivers of the control system. This data is considered as ADC count data. This method compares the ADC count data to switching signals of the devices to identify and locate failures in the system.
Additionally, the pre-existing presence of a control system and voltage and current sensors in inverters used for standard operation mean that condition monitoring algorithms for pre-power diagnostics can be implemented with little incremental cost, and typically require little other than a software upgrade or a software sub-routine.
By relying on the information provided by pre-power monitoring and diagnostics to assess the machine's condition and identify failures, and future failures, cascading and catastrophic failures in the system can be prevented, thereby saving significant money and preventing system down-time.
The detection of failures in inverter-driven machines is challenging due to noise created by high switching frequency. However, the cost savings of detecting and preventing catastrophic failures makes pre-power diagnostics worth the development of such methods.
At least one example embodiment provides a drive system including a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with the plurality of phases and a direct current (DC) bus, operatively connected to the machine. The DC bus includes a high-side line, a low-side line, and an inverter including a plurality of switching systems, operatively connected between the high-side line and the low-side line, the plurality of switching systems, each configured to output a respective one of the plurality of phase currents. The drive system also includes a controller, operatively connected to the DC bus and the machine, the controller configured to determine if a failure exists in the drive system based on the plurality of phase currents and a DC bus voltage, the DC bus voltage being a voltage across the high-side line and the low-side line.
At least another example embodiment provides a drive system including, a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with the plurality of phases and a direct current (DC) bus, operatively connected to the machine. The DC bus includes a high-side line, a low-side line, and an inverter including a plurality of switching systems, operatively connected between the high-side line and the low-side line, the plurality of switching systems, each configured to output a respective one of the plurality of phase currents and a voltage. The drive system also includes a controller operatively connected to the DC bus and the machine, the controller configured to respectively apply voltages to the plurality of switching systems, the output voltages of the plurality of phase currents respectively based on the applied voltages. The controller includes an analog-to-digital converter (ADC) configured to measure voltages output by the plurality of switching systems, generate count data based on the measured voltages. The controller is configured to determine if a failure exists in the drive system based on the count data.
At least another example embodiment discloses a computer readable medium, when run on a computer, configured to instruct the computer to, determine if a failure exists in a drive system based on the plurality of phase currents and a DC bus voltage. The drive system includes a machine including a plurality of phases and configured to generate power based on a plurality of phase currents, each respectively associated with the plurality of phases, a direct current (DC) bus, operatively connected to the machine. The DC bus includes a high-side line, a low-side line, the DC bus voltage being a voltage across the high-side line and the low-side line, and an inverter including a plurality of switching systems, operatively connected between the high-side line and the low-side line, the plurality of switching systems, each configured to output a respective one of the plurality of phase currents.
Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.
Various example embodiments will now be described more fully with reference to the accompanying drawings in which some example embodiments are illustrated.
Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but on the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of the claims. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which example embodiments belong. It will be further understood that terms, e.g., those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Portions of example embodiments and corresponding detailed description are presented in terms of software, or algorithms and symbolic representations of operation on data bits within a computer memory. These descriptions and representations are the ones by which those of ordinary skill in the art effectively convey the substance of their work to others of ordinary skill in the art. An algorithm, as the term is used here, and as it is used generally, is conceived to be a self-consistent sequence of steps leading to a result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of optical, electrical, or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
In the following description, illustrative embodiments will be described with reference to acts and symbolic representations of operations (e.g., in the form of flowcharts) that may be implemented as program modules or functional processes including routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and may be implemented using existing hardware. Such existing hardware may include one or more Central Processing Units (CPUs), digital signal processors (DSPs), application-specific-integrated-circuits, field programmable gate arrays (FPGAs) computers or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise, or as is apparent from the discussion, terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.
Note also that the software implemented aspects of example embodiments are typically encoded on some form of tangible (or recording) storage medium or implemented over some type of transmission medium. The tangible storage medium may be magnetic (e.g., a floppy disk or a hard drive) or optical (e.g., a compact disk read only memory, or “CD ROM”), and may be read only or random access. Similarly, the transmission medium may be twisted wire pairs, coaxial cable, optical fiber, or some other suitable transmission medium known to the art. Example embodiments are not limited by these aspects of any given implementation.
The drive system 12 of example embodiments is well suited for diagnosing, identifying and classifying a failure of an inverter (e.g., a power inverter 30) in real-time or during an operational mode of the inverter, as opposed to a pre-test non-operational mode. In the operational mode, the inverter (e.g., power inverter 30) is capable of converting direct current into one or more alternating current signals for application to a machine 177 or motor for control of the machine or motor 32. In the test mode, the inverter does not provide or output one or more alternating current signals for application to a machine or motor 32.
The DC bus 28 may have a converter 26 coupled electrically between the generator 24 and the motor 32 to convert alternating current (AC) power into DC power during a generation operating mode of the generator 24 (i.e. conversion of mechanical energy from the power source into electric energy for supply onto the DC bus 28), and DC power into AC power during motoring of the generator 24 (i.e. removing electric energy from the DC bus 28 and converting it into mechanical energy for the power source). The DC bus 28 may have the power inverter 30 (e.g., a multi-phase inverter) coupled electrically between the converter 26 and the motor 32 to convert DC power from the DC bus 28 into AC power during motoring of the motor 32 and to convert AC power into DC power during braking of the motor 32. The drive system 12 may include a brake chopper 22 to dissipate electric power from the DC bus 28. In vehicles with a brake chopper 22 (i.e. regenerative braking), the inverter 30 also takes power from the motor 32 during braking and stores it in batteries (not shown).
A voltage sensor 36 (shown in
Referring to
The power converter 26 may be configured as an AC-DC converter to convert three-phase AC power from the generator 24, which may be a 3-phase permanent magnet (PM) generator, into DC power for the DC bus 28, and vice versa. The digital circuit voltages into the power converter 26 for the power generator 24 are denoted as Vdig_1 for the phase 1 voltage, Vdig_2 for phase 2 voltage, and Vdig_3 for phase 3 voltage. For each phase of the voltage, Vdig_1, Vdig_2 and Vdig_3, two switch packages 84 are placed across the DC supply, and are switched on and off to generate the three phases from the motor power converter 26 to the power generator 24. Each switch package 84 includes a diode 84-1 and an insulated gate bipolar junction transistor (IGBT) 84-2. Respective switch packages 84 may be coupled to a respective one of the generator 24 phase windings to convert AC power from the respective winding into DC power on the DC bus 28 between the positive DC power rail 44 and the negative DC power rail 46. When the appropriate voltage is applied to the base (gate) of an IGBT 84-2 of the power converter 26, the IGBT 84-2 may be activated and the collector may be coupled electrically to the emitter to supply electric power. The appropriate voltage depends on a rating of the IGBT 84-2. For example, 14 V may be applied at the base with respect to an emitter of the IGBT 84-2 to turn the IGBT 84-2 on. Negative 8 V may be applied at the base with respect to the emitter to turn the IGBT 84-2 off. The power converter 26 may be operated in reverse if the generator 24 is to operate as a motor.
Although IGBT refers to an insulated gate bipolar transistor, in any phase of the inverter 30, the high-side switching transistor (e.g., 94-2a) and the low-side switching transistor (e.g., 94-2b) may comprise field effect transistors, complementary metal oxide semiconductors, power transistors, or other suitable semiconductor devices.
The power converter 26 is controlled by the control system 40. A generator controller 48 of the control system 40 may have gate drivers and an analog-to-digital converter (ADC) 50, a microprocessor 52 coupled electrically to the gate drivers 50, and memory 54 coupled electrically to the microprocessor 52 and having stored therein operating instructions for the microprocessor 52. The base of each IGBT 84-2 is coupled electrically to a respective gate driver 50 that is dedicated to that IGBT 84-2 and may provide a low DC voltage (e.g., 24 VDC) to turn on and off that IGBT 84-2. Thus, there may be a gate driver 50 for each IGBT 84-2 of the power converter 26. The gate drivers 50 for the IGBT 84-2 of the power converter 26 are under the control of the microprocessor 52, which may employ a pulse-width-modulation control scheme to control those gate drivers 50 and the IGBT 84-2 of the power converter 26 to supply electric energy on the DC bus 28 in the generating mode of the generator 24 and remove electric energy from the DC bus 28 in the motoring mode of the generator 24. In example embodiments, space vector modulation may be used. However, it should be understood, that any known pulse-width-modulation scheme for drive systems may be used. Thus, for the sake of brevity, the pulse-width-modulation scheme will not be described in greater detail.
The motor 32, may be configured as a three-phase switched reluctance (SR) motor having three phase windings 42a, 42b and 42c, as shown in
As used in this document, switch states indicate whether a properly functioning or unimpaired semiconductor device is active (“on” or “closed”) or inactive (“off” or “open”). A failure of a semiconductor device to change states may result in a semiconductor device failing in an open state or a closed state, for example.
The power inverter 30 may include pairs of high-side and low-side switch packages 94a and 94b. Each high-side switch package 94a includes a diode 94-1a, an insulated gate bipolar junction transistor (IGBT) 94-2a, and a power diode 96. Each low-side switch package 94b includes a diode 94-1b, an IGBT 94-2b and a power diode 96. Pairs of switch packages 94a, 94b may be respectively coupled electrically to the motor 32 phase windings, 42a, 42b and 42c. As such, the power inverter 30 is depicted as having three sections, 31a, 31b and 31c, each associated with one of the phase windings 42a, 42b and 42c. The sections 31a, 31b and 31c, enable individual control of each individual phase A, B and C. In this configuration, for each section 31a, 31b and 31c, a high-side switch package 94a and a low-side switch package 94b are connected across a respective motor phase winding 42a, 42b and 42c. The high-side switch package 94a is coupled electrically to the positive DC rail 44, and the low-side switch package 94b is coupled electrically to the negative DC rail 46. When the appropriate voltage is applied to the base of an IGBT 94-2a and/or 92b of the power inverter 30, the IGBT 94-2a and/or 94-2b (switch) may be activated and the collector may be coupled electrically to the emitter to supply electric power to the respective winding 42a, 42b or 42c. The power inverter 30 may be operated in reverse if the motor 32 is to operate as a generator. An example of the power flow situations is depicted in more detail in
The power inverter 30 is controlled by the control system 40. A motor controller 56 of the control system 40 may have gate drivers 58, a field programmable gate array 60 (FPGA) coupled electrically to the gate drivers 58, a microprocessor (e.g., digital signal processor) 62 coupled electrically to the FPGA 60, and memory 64 coupled electrically to both the FPGA 60 and the microprocessor 62 and having stored therein operating instructions for the FPGA 60 and the microprocessor 62. The base of each IGBT 94-2a, 94-2b is coupled electrically to a respective gate driver 58 that is dedicated to that IGBT 94-2a, 94-2b and may provide a low DC voltage (e.g., 24 VDC) to turn on and off that IGBT 94-2a, 94-2b. The gate drivers 58 are under the control of the FPGA 60 which may employ a SR-motor control scheme to control the gate drivers 58, the IGBT 94-2a, 94-2b, and thus, the motor 32 (including varying the amplitudes and frequencies to the motor windings 42a, 42b, 42c) so as to vary the torque output of the motor 32 when the motor 32 is in its motoring mode or to vary the electric generation capacity of the motor 32 when the motor 32 is in its braking mode. As previously stated, it can be appreciated that the drive system 12 can have more than one motor 32 and attached inverter 30 and current sensor(s) 38 incorporated therein, and the control system 40 may have a motor controller 56 for each power inverter 30 to control that inverter 30, although only one such inverter 30 and motor controller 56 is discussed and shown.
Optionally, the drive system 12 may include a brake chopper 22 to control use of a brake resistor 70 to dissipate electric power from the DC bus 28. The brake chopper 22 may be coupled electrically between the rails 44, 46 as shown. The digital circuit voltage into the drive system 12 from the brake chopper 22 is shown as Vdig_Brake. The brake chopper 22 may include a switch package 74, with a diode 74-1 and an insulated gate bipolar junction transistor (IGBT) 74-2 and a diode 76. The diode 76 may be in parallel with the brake resistor 70. When the appropriate voltage is applied to the base of the IGBT 74-2 of the brake chopper 22, the IGBT 74-2 may be activated and the collector may be coupled electrically to the emitter to allow dissipation of electric power through the brake resistor 70. The gate driver for the IGBT 74-2 of the brake chopper 22 issues a brake resistor control signal in the form of, for example, a pulse-width modulated voltage signal that applies the voltage to the base of the switch IGBT 74-2, the voltage signal being pulse-width modulated according to a brake duty to turn the brake resistor 70 ON, to dissipate electric energy from the DC bus 28, and OFF correspondingly.
The brake chopper 22 is controlled by the control system 40. The gate driver for the IGBT 74-2 of the brake chopper 22 may be one of the gate drivers 58 of the motor controller 56. Such gate driver 58 for the IGBT 74-2 may be under the control of the FPGA 60 of the motor controller 56 to control that gate driver 58, the IGBT 74-2, and the brake resistor 70. In other example embodiments, the gate driver for the IGBT 74-2 may be one of the gate drivers 50 of the generator controller 48. In such a case, that gate driver 50 may be under the control of the microprocessor 52 of the generator controller 48 to control that gate driver 50, the IGBT 74-2, and the brake resistor 70.
The drive system 12 may have one or more voltage sensors coupled to the positive DC rail 44 of the DC bus 28 to sense the DC bus voltage. The DC bus voltage is the voltage across the rails 44 and 46. In some example embodiments, voltage sensors are also coupled to the negative DC rail 46 of the DC bus 28 and configured to sense the phase voltages for phases A, B and C. Voltage sensors 36 may be stand-alone sensors or may be incorporated into any of the controllers 48, 56 in the control system. For example, one voltage sensor 36 may be for the generator 24 and another voltage sensor 36 may be used for motor control and pole voltage measurements. The voltage sensor 36 may send a signal to the control system 40 including the sensed DC bus voltage level.
A DC link capacitor 700 may be provided between the rails 44, 46. The capacitor 700 may be configured, for example, as a bank of capacitors.
In alternate embodiments, the windings 42a, 42b and 42c may be replaced with or represent an inductor.
Referring now to
In a second operational mode, i.e. supplying negative current to a phase of the motor 32, the low-side IGBT 94-2b is on, and the high-side IGBT 94-2a is closed, such that the phase current flows in a direction 512 (with exception to SR machine as in SR machine there is no current reversal through motor winding) through the low-side switch 94b, returning the trapped magnetic energy to the DC bus 28. The power pulse is of short duration, and then the IGBT 94-2b is switched off. Because of the inductance of the winding 42a, the current continues to flow, going out through the diode 96. This occurs for each of the 3 phases, A, B and C; i.e. in each section 31a, 31b and 31c.
Example embodiments utilize these features of inverter fed electric machines systems by operating the system 12 in a pre-power up low voltage mode. In one method according to an example embodiment, the control system 40 utilizes measurements of sensed signal levels to determine if there is a failure in the system. It should be understood that “signal level” may refer to either a measured phase voltage or a measured phase current. It is possible to convert a measured phase voltage to a phase current with a transconductance amplifier or transresistance amplifier (e.g., op-amplifier plus a resistor). For the sake of brevity, the first method is described using measured phase currents as the signal levels. However, it should be understood that the first method may be implemented using measured phase voltages.
Another example embodiment utilizes measurements of sensed voltage at the AC mid-point measured between the high-side and low-side devices in an inverter leg with respect to the negative DC bus, as shown in
In both methods, once the type and location of failure is determined, the control system 40 will mitigate or eliminate ill effects of occurred failure(s), and will reconfigure the drive system 12 as necessary for it to resume operation at an optimum level without further compromise in system hardware, or an error message will be relayed to indicate the failure requires repair before the drive system 12 can continue safe operation.
The first method according to an example embodiment is described in more detail below and shown in
At step 100, the first step in the control system 40 (diagnostic system) determines whether the DC bus is operating at a test voltage VT, i.e., a low voltage used for the test mode (10 volts or less). For example, the test voltage VT may be any voltage between 10V and 25V. At a 10 V DC bus voltage, pre-power diagnosis may run slower and 25V DC bus, pre-power diagnosis runs faster. A 10 V DC bus may be used for large power inverter fed electric machines and 25 V may be used for small power inverter fed electric machines. An inductance of the motor 32 goes down as its power rating goes up. Low voltage (10 V) pre-power diagnosis may be used for a low inductance machine to reach an over current limit faster and high voltage (25 V) pre-power diagnosis may be used for a higher inductance machine.
If the DC bus is at a voltage greater than the test voltage VT, the control system 40 diagnostics will not be performed at step 100a. If the DC bus is operating at or below the test voltage VT the control system 40 enters a test mode, then at step 101, the control system 40 determines if the DC bus voltage is less than a threshold voltage VTH (e.g., 5 volts). If the DC bus voltage is less than the threshold voltage VTH, the control system 40 determines that a capacitor in the link capacitor 700 has failed, and at step 200 the control system 40 sends to a register an error indicating that the capacitor has failed. If the control system 40 is in the test mode, then at step 102, the control system 40 sets a phase A high-side over-current value (e.g., 10 amps). The over-current value is determined based on a permitted DC bus voltage diagnostic time of the vehicle. At step 103, the phase A high-side IGBT is set on and the phase B low-side IGBT is turned on by the control system 40.
At step 104, the control system 40 determines if there is a phase A high-side over current failure using the current sensor 38 for the phase A. If the control system 40 determines there is a phase A high-side over current failure at step 201, the control system 40 determines if the DC bus voltage has fallen below the threshold voltage VTH. If the DC bus voltage is below the threshold voltage VTH, this indicates that the phase A low-side IGBT is also on, due to the failure. At step 202, the control system 40 indicates that there is a shorted switch in the control system 40 and provides a system alert to the FPGA 60 about the failure. If, at step 201, the DC bus voltage has not fallen below 5 volts, then at step 203, the control system 40 monitors the phase A high-side over current to determine if the phase A high-side over current failure lasts for at least a threshold time TTH (e.g., 10 ms). If the phase A high-side over current lasts for at least the threshold time TTH, then at step 204, the control system 40 determines that a system failure of an open terminal has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the phase A high-side over current does not last for at least the threshold time TTH, then method proceeds to step 105.
If at step 104, if the phase A high-side over current does not experience a failure, then at step 105, the control system 40 checks to ensure the DC bus voltage is equal to or less than the test voltage VT to ensure the control system 40 is in the test mode before continuing with the pre-power test. If the DC bus voltage is not equal to or less than the test voltage VT, then the control system 40 stops the method at step 105a. If the DC bus voltage is less than or equal to the test voltage VT, then at step 106, the control system 40 sets a phase B high-side over-current value (e.g., 10 amps). At step 107, the control system 40 turns the phase A high-side IGBT and phase B low-side IGBT off, and sets the phase A low-side IGBT and the phase B high-side IGBT on.
At step 108, the control system 40 determines if there is a phase B high-side over current failure, then at step 301, the control system 40 determines if the DC bus voltage has fallen below the threshold voltage VTH. If the DC bus voltage is below the threshold voltage VTH, the control system 40 determines that the phase B low-side IGBT is also on, due to a failure. At step 302, the control system 40 indicates that there is a shorted switch (phase B low-side IGBT) in the drive system 12 and provides a system alert to the FPGA 60 about the failure. If, at step 301, the DC bus voltage has not fallen below 5 volts, then at step 303, the control system 40 monitors the phase B high-side over current to determine if the phase B high-side over current failure lasts for at least the threshold time TTH. If the phase B high-side over current lasts for at least the threshold time TTH, then at step 304, the control system 40 determines that a system failure of an open terminal has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the phase B high-side over current failure does not last for at least the threshold time TTH, then the method proceeds to step 109.
At step 108, if the control system 40 determines that the phase B high-side over current does not experience a failure value, then at step 109, the control system 40 checks to ensure the DC bus voltage is equal to or less than the test voltage VT to ensure the control system 40 is in test mode before continuing with the pre-power test. If the DC bus voltage is not equal to or less than the test voltage VT, then the control system 40 stops the method at step 109a. If the DC bus voltage is equal to or less than the test voltage VT, then at step 110, the control system 40 sets the phase A high-side over-current value (e.g., 10 amps). At step 111, the phase A high-side IGBT is set on and the phase C low-side IGBT is turned on by the control system 40.
At step 112, if the control system 40 determines there is a phase A high-side over current failure, then at step 401, the control system 40 determines if the DC bus voltage has fallen below the threshold voltage VTH. If the DC bus voltage is below the threshold voltage VTH, the control system 40 determines that the phase A low-side IGBT is also on, due to the failure. At step 402, the control system 40 indicates that there is a shorted switch in the drive system 12 and provides a system alert to the FPGA 60 about the failure. If, at step 401, the DC bus voltage has not fallen below the threshold voltage VTH, then at step 403, the control system 40 monitors the phase A high-side over current to determine if the phase A high-side over current failure lasts for at least the threshold time TTH. If the phase A high-side over current failure lasts for at least the threshold time TTH, then at step 404, the control system 40 determines that a system failure of an open terminal has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the phase A high-side over current failure lasts for at least the threshold time TTH, then the method proceeds to step 113.
If at step 112, the phase A high-side over current does not experience a failure, then at step 113 the control system 40 checks to ensure the DC bus voltage is equal to or less than the test voltage VT to ensure the control system 40 is in test mode before continuing with the pre-power test. If the DC bus voltage is equal to or less than the test voltage VT, the control system stops the method at step 113a. If the DC bus voltage is equal to or less than the test voltage VT, then at step 114, the control system 40 sets a phase C high-side over-current value (e.g., 10 amps). At step 115, the control system 40 turns the phase A high-side IGBT and phase C low-side IGBTs off, and sets the phase A low-side IGBT and the phase C high-side IGBTs on.
If at step 116, the control system 40 determines there is a phase C high-side over current failure, then at step 501, the control system 40 determines if the DC bus voltage has fallen below the threshold voltage VTH. If the DC bus voltage is less than the threshold voltage VTH, the control system 40 determines that the phase C low-side IGBT is also on, due to the failure. At step 502, the control system 40 indicates that there is a shorted switch (e.g., phase C side IGBT 94-2a) in the drive system 12 and provides a system alert to the FPGA 60 about the failure. If, at step 501, the DC bus voltage has not fallen below the threshold voltage VTH, then at step 503, the control system 40 monitors the phase C high-side over current to determine if the phase C high-side over current failure lasts for at least the threshold time TTH. If the phase C high-side over current failure lasts for at least the threshold time TTH, then at step 504, the control system 40 determines that a system failure of an open terminal has occurred, indicating that current is not flowing, and that the machine is therefore not connected to the inverter. A system alert is provided to the FPGA 60 about the failure. If the phase C high-side over current failure does not last for at least the threshold time TTH, the method proceeds to step 117.
If at step 116, if the phase C high-side over current does not experience a failure value, then at step 117 the control system 40 checks to ensure the DC bus voltage is equal to or less than the test voltage VT to ensure the control system 40 is in test mode before continuing with the pre-power test. If so, then the test mode will proceed for checks of the capacitors at step 120, checks of the inverter at step 130, checks of the generator at step 140, checks of the cables at step 150, etc. If the DC bus voltage is not equal to or less than the test voltage VT, the control system stops the method at step 117a.
If at step 117, the control system 40 determines that the DC bus voltage is not equal to at least the test voltage VT, the control system 40 continues to monitor the DC bus voltage until it is equal to at least the test voltage VT. If, at step 117, the DC bus voltage is still equal to the test voltage VT, then the control system 40 resets the IGBTs from step 115. At step 120, the control system 40 performs a pre-power diagnostics check of the capacitors in the drive system 12. A system alert is provided to the FPGA 60 about any failures. At step 130, the control system 40 performs a pre-power diagnostics check of the system inverter 30. A system alert is provided to the FPGA 60 about any failures. At step 140, the control system 40 performs a pre-power diagnostics check of the system generator 24. A system alert is provided to the FPGA 60 about any failures. At step 150, the control system 40 performs a pre-power diagnostics check of the brake chopper system 22. A system alert is provided to the FPGA 60 about any failures. At step 160, the control system 40 performs a pre-power diagnostics check of the system cables. A system alert is provided to the FPGA 60 about any failures. When all the system pre-power diagnostics are completed successfully at step 170, and the drive system 12 appears to be operating correctly, full-power up proceeds.
A second method of failure analysis according to an example embodiment is described in more detail below and the differences in voltage measurements are shown in
The second method utilizes measurements of sensed voltage at the AC mid-point measured between high-side and low-side devices in an inverter leg with respect to a negative DC bus. In example embodiments according to
In an SR motor system such as the SR motor system shown in
The sensed voltages are processed in the Analog-to-Digital Converter (ADC) that is built in to the gate driver (50, 58) of the control system 40. The converted digital data is sent to the relevant control board. The Vpole_A, Vpole_B, Vpole_C, Vpole_BC data is considered as ADC count data.
For example, the gate driver 58 may apply 0 to 5V analog signals to the IGBTs. To be in the linear range, the gate driver may use 0.5V to 4.5V. Thus, if a high-side IGBT is turned-on, voltage input to ADC will be 4.5V and if low-side IGBT is turned-on voltage input to ADC will be close to 0.5V. If no IGBT is turned-on, an inverter pole voltage will be close to 2.5V. A sensed voltage at an inverter pole point after processing by front stage remains in the range of 0.5V and 4.5V. The sensed voltage may be converted in ADC count data. For example, 4.5V may equal 921 counts for a 10 bit ADC and 0.5 V may equal 102 counts. Therefore, depending of ADC counts it can be determined weather an IGBT was turned-on. Once the IGBT is off, a voltage reading will change as current that was supplied by the IGBT will be taken over by a diode and reading to ADC will change.
This method compares the ADC count data to switching signals of the devices to identify and locate failures in the drive system 12.
It should be understood that Table 1, as well as Tables 2-5, may be produced from empirical data. For example, an electronic circuit may be placed between inverter pole points (with respect to negative DC bus) and an input of ADC (analog to digital converter) on gate driver boards. The electronic circuit reduces voltages at the ADC input to a max value of 5V and min value of 0V. ADC count per volt is stated as:
(1/(5V/2^10))
The gate driver 58 provides ADC counts to a control board and the control board determines values of pole voltages and then the pole voltages determined by control board are looked against a switch status [on or off or what has been done recently with switch(s) (IGBTs turned-on or off)] of the inverter. The developed ADC count data becomes decision criteria for the control system 40 to decide a type of failure in an inverter fed electric machine and where the failure has occurred.
The control system 40 is configured to detect the fault in the inverter (e.g., power inverter 30) if the ADC count data does not conform to one or more reference ranges (e.g. look-up Tables 1-5 below) stored in the memory 64 for corresponding switch states of the semiconductor devices. Conversely, the control system is adapted to detect the absence of fault in the inverter (e.g., power inverter 30) if the ADC count data conforms to one or more reference ranges stored in the memory 64 for corresponding switch states of the semiconductor devices.
The control system 40 may determine if the ADC count does not follow the pattern shown in Table 1. If the ADC count does not follow the pattern shown in Table 1, then a failure is declared by the control system 40. There are seven different categories of failures that can be identified in the control system 40 using this detection method. The categories are as follows:
Category A: DC bus failed short,
Category B: DC bus failed open,
Category C: IGBT failed open,
Category D: IGBT failed short,
Category E: Diode failed open,
Category F: Diode failed short,
Category G: Motor cable is not connected with inverter pole
Once the control system 40 determines that there is a failure in the drive system 12, the failure can be identified, as shown in Table 2.
The control system 40 may determine if the ADC count does not follow the pattern shown in Table 3. If the ADC count does not follow the pattern shown in Table 3, then a failure can be declared by the control system 40. There are seven different categories of failures that can be identified in the drive system using this detection method. The categories are as follows:
Category A′: DC bus failed short,
Category B′: DC bus failed open,
Category C′: IGBT failed open,
Category D′: IGBT failed short,
Category E′: Diode failed open,
Category F′: Diode failed short,
Category G′: Motor cable is not connected with inverter pole
Once the control system 40 has determined that there is a failure in the drive system, the control system 40 will proceed with detecting if there is a failure in the DC bus, as shown in Table 4.
If the DC bus passes the test, there is no failure in the DC bus, and the control system 40 proceeds with identifying the location of the failure in the inverter, machine and/or cable that connects machine with inverter.
When the analysis in Table 5 has been completed for Phase A by the control system 40, the control system 40 performs the analysis for phases B and C, with the switches (IGBTs and diodes) for phases B and C used, respectively, to get appropriate pole point voltages and ADC counts. A failure detection method for brake chopper IGBTs in SR Machines may same as stated in Table 2 above.
Any of Tables 1 through 5, inclusive, may be structured as one or more look-up tables, files, database, data records or other data structures that are stored in the memory 64 of the control system 40.
In any of the Tables, there are two illustrative possibilities or permutations of ADC count depending upon when switches (IGBTs in inverter) are commanded close and/or open. The above possibilities are stated in Table below for 10-bit or 12 bit analog to digital converter (ADC) (e.g., analog-to digital converter 14). In Tables 1 through 5, inclusive, by sensing alternating current node voltages (inverter midpoint voltage with respect negative direct current bus) and knowing ADC counts for, Vpole_A, Vpole_B, Vpole_C, and Vpole_BC, the following failures can be detected in the inverter fed electric machine systems: (1) any or pair of switching transistors (e.g., IGBTs) failed short in the inverter; (2) any switching transistor (e.g., IGBT) failed open in the inverter; (3) any diode (e.g., protective diode) failed short or failed open in the inverter; (4) any capacitor failed short; (5) any cable between inverter or machine failed short or failed open; (6) any machine winding failed short or failed open; (7) any braking circuit transistor (e.g., brake chopper IGBT) or diode failed open or failed short; and (8) brake grid resistance and/or cable failed open or failed short.
Example embodiments being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of example embodiments, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the claims.
This application claims the benefit under 35 U.S.C. §119 of U.S. Provisional Application Nos. 61/446,539, filed Feb. 25, 2011, and 61/454,690, entitled SYSTEM FOR DETECTING A FAILURE ASSOCIATED WITH AN INVERTER OR ASSOCIATED MACHINE, invented by Brij N. Singh, filed Mar. 21, 2011, the entire contents of each of which are incorporated herein by reference.
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