Magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate

Abstract

An improvement in a system for encoding a data field on a disk with write gate data. The system has an encoder and a data receiving controller for directing write gate data in the form of 0 and 1 bits to the encoder. The encoder, in response to the write gate data, produces a primary code in the form of 0 and 1 bits and directing the primary code to the disk. The primary code has certain predetermined criteria with the encoder producing a secondary coding rate as an exception when the write gate data does not result in the predetermined criteria. The improvement comprises a mechanism for ensuring that the last predetermined number of bits in the data field are free from the exception.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to a magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate for encoding data in preparation for writing said data on a disk during a write gate signal being active and, more particularly, it relates to a magnetic encoder system for a (1,7) channel having a 2/3 coding rate for encoding data in preparation for writing said data on a disk during a write gate signal being active with a mechanism for ensuring that data during the training and write pad portions of the written data field qualify as valid data for those fields irrespective of the data being presented to the encoder.

2. Description of the Prior Art

When data is written on a disk, there must be a way to read the data back from the disk in order to synchronize the data to a clock thereby clocking the data back in the shift register. Basically, the data must be encoded as the data is written to the disk in such a fashion to guarantee that the data information will be readable from the disk over time. The length of time is limited so that every time a new piece of data information is read, the clock can be synchronized.

Various ways have been proposed in the past for increasing the recorded data density on mediums such as magnetic discs or tapes and in other similar media. One approach utilized is known as run-length-limited (RLL) coding which requires that each 1 in a coded bit sequence must be separated from the nearest adjacent 1 by a specified number of 0's. This number must be at least equal to a minimum quantity d because of inter-symbol interference but must not exceed a maximum of k which is required for self-clocking purposes. Codes following this RLL format are generally referred to as (d,k) run-length-limited codes. The present invention relates to a particular code suited for magnetic recording channels wherein d=1 and k=7. To convert unconstrained data into a (d,k)-constrained format generally requires that m unconstrained bits be mapped into n constrained bits, where m<n. The ratio m/n is usually referred to as the coding rate or efficiency. It is obviously desirable to maximized this coding rate. The tradeoffs usually considered in maximizing the rate are the decoding look-ahead and the hardware complexity.

Raising the coding efficiency or rate at the expense of decoding look-ahead generally results in increasing the error propagation on data read back. That is, a single bit error introduced in the code stream will cause a certain number of subsequent bits to also be erroneous before the coding algorithm becomes self-correcting. It is always desirable to minimize error propagation. To this end, it has been found that a coding rate of 2/3 is optimal for the (1,7) code.

In the Adler et al, U.S. Pat. No. 4,413,251, an algorithm and hardware for producing a RLL code for magnetic recording channels is described. The system of the Adler et al patent produces sequences which have minimum of one 0 and a maximum of seven 0's between adjacent 1's. The code is generated by a sequential scheme that maps two bits of unconstrained data into three bits of constrained data. The encoder is a finite state machine whose internal state description requires three bits. The decoder requires a look-ahead of two future symbols (six bits) and its operation is chapel state independent.

While the hardware implementation of the system of the Adler et al patent is simple and can operate at very high data speeds, the Adler et al patent's system (and others like it) are generic and require knowledge within the controlling entity (controller) of the encoders encoding mechanism. Further, buffer space must be provided in the controller for the information written in the training and write pad fields. For instance, when writing the training field, data must be presented to the encoder which generates a known encoded symbol for proper symbol boundary alignment during read-back. Further, when writing the write pad field, data must be presented to the encoder which will guarantee all encoder exception processing is completed before the end of the write pad field. Both situations require knowledge of the encoders encoding mechanism if proper data is to be presented by the controller. In the latter situation, if all exception processing has not been completed at the end of the write gate signal being active then there exists a possible failure mode during read back. The decoder would require additional exception processing necessitating the reading of data beyond the end of the write pad field. The data previously encoded on the disk may not be appropriate for proper exception processing or could result in data sequences on the disk having less than one 0 or more than seven 0's between adjacent 1's. Such data sequences can produce erroneous decoded data during read back.

Accordingly, there exists a need for a system for encoding a data field on a disk in which the controller does not require knowledge of the encoding mechanism to properly write data fields on a disk in a manner appropriate for reading without introducing errors.

SUMMARY OF THE INVENTION

The present invention is an improvement in a system for encoding a data field on a disk during the write gate signal being active. The system has an encoder and a data selection multiplexer for directing data from the controller in the form of 0 and 1 bits to the encoder. The encoder, in response to the user write gate signal becoming active, produces a run length limited (RLL) code in the form of 0 and 1 bits dependent on the data presented by the controller and suitable for writing to the disk. The RLL code has criteria including a coding rate of 2/3 which requires a minimum of one 0 and a maximum of seven 0's between adjacent 1's. The improvement comprises means for ensuring that during user write gate being inactive the encoder produces RLL codes that are free from exceptions and valid for training and write pad fields. Further, the minimization of trailing exceptions minimizes the necessary length of the write pad field. Still further, the ability of the encoder to generate suitable data for the training and write pad fields eliminates any need for storage space in the data buffer for the training and write pad fields.

In an embodiment of the present invention, the means includes a two bit pair generating mechanism injecting a two bit pair into the encoder. Preferably, the generating mechanism generates an two bit pattern which results in an 0 1 0 encoded RLL pattern output from the encoder.

In another embodiment of the present invention, the means is connected to the encoder in a parallel relationship with the data presented by the controller. The means interjects information into the encoder independent of the data presented by the controller in a multiplex fashion where selection is dependent upon the user write gate signal state.

The present invention is further an encoder for receiving a user write gate signal and two bit data pairs from the controller. The controller presents defined data in the form of 0 and 1 bits to the encoder during the user write gate signal being active and undefined or random data during the user write gate signal being inactive. The encoder, in response to the controller data and the user write gate signal being active, produces a run length limited (RLL) code in the form of 0 and 1 bits dependent on the successive two bit data pairs from the controller. The encoder, in response to the controller user write gate signal being inactive, produces a run length limited (RLL) code in the form of 0 and 1 bits independent on the data being presented by the controller. The RLL data has criteria including a coding rate of 2/3 which requires a minimum of one 0 and a maximum of seven 0's between adjacent 1's.

Annotation: The following text appears to be repeated erratically from above, that is why it is deleted entirely and not edited.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram illustrating a magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate constructed in accordance with the present invention;

FIG. 2 is a table illustrating the primary encoding table of the magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate constructed in accordance with the present invention;

FIG. 3 is a table illustrating the secondary encoding table of the magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate constructed in accordance with the present invention;

FIG. 4 is representative data, for example, being encoded by both the primary encoding table and the secondary encoding table of the magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate constructed in accordance with the present invention; and

FIG. 5 is a schematic diagram illustrating the duration of the actual write of data to the disk of the magnetic recording encoder system for a (1,7) channel having a 2/3 coding rate constructed in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As illustrated in FIG. 1, the present invention is a system, indicated generally at 10, for encoding a data field 12 on a disk (not shown) during the write gate signal 15 being active. The system 10 has an encoder/decoder 16 (hereinafter referred to as the encoder) and a controller or controlling entity 18 for directing of user data 20 and selection of sub-fields of the written data. The controller 18 directs user data 20, i.e., generally a predetermined number of bytes of data known as non return to zero data (NRZ data), in the form of 0 and 1 bits to the encoder 16. The encoder 16, in response to the NRZ data 20 and the user write gate signal 15 being active, produces a run length limited (RLL) code, also in the form of 0 and 1 bits, dependent on the write gate data 15. As illustrated in FIG. 2, in the present invention, the RLL code preferably has a coding rate of 2/3, where two unconstrained NRZ data bits are mapped into three constrained channel bits, with a primary RLL code criteria requiring a minimum of one 0 and a maximum of seven 0's between adjacent 1's.

An example of the 1,7 constrained 2/3 coding rate as described immediately above, and as illustrated in FIG. 2, will now be discussed. The encoder 16 receives in succession, for example, two bits of information from the controller 18 in the form of 0's and 1's. Each of these pairs are taken in their successive order and translated through a primary look-up table (FIG. 2) 22 from a two bit pair to a three bit word. As discussed above, the constraint of each of the newly formed three bit words is that there can never be two 1's next to each other. These three bit words are then concatenated successively (FIG. 4) to form a binary write data stream. By using three bit words, the possibilities of having two 1's together is greatly lessened (See FIG. 4).

If by chance, by using the two bit pair to three bit word look-up table 22, concatenation causes two 1's together, the encoder 16 produces a secondary coding which violates the (d,k) constraint of the primary RLL code criteria. The encoder 16 detects this and then uses a slightly larger secondary look-up table (FIG. 3) to deal with these exceptions, i.e., four bits to six bits. If the encoder 16 can not meet the primary criteria by translating the two bit pair into a three bit word, then the previous NRZ data bit pair is concatenated with the current NRZ data bit pair producing a four bit word and translated into a six bit word through an secondary look-up table 24. Each of the six bit words generated by the secondary look-up table 24 ends with three 0 bits thus guaranteeing that any subsequent translation and concatenation by the primary look-up table 22 can not generate a violation of the RLL code criteria. Upon the entry of the next two bit NRZ data pair from the controller 18, the encoder 16 begins again with the primary look-up table 22. FIG. 4 illustrates a typical data stream being encoded by both the primary table 22 and the secondary table 24.

For data 12 written on a disk to be accurately read back from the disk the following things, from the point of view of the encoder/decoder 16, must occur;

1) the PLL must adjust to the frequency of the written data 12 and also obtain phase lock with the written data 12; 2) the three bit word boundaries defined during writing the data 12 must be identified and the decoder must synchronize itself with the three bit word boundaries; 3) the start of actual data 12 must be determined; 4) the data 12 must be read in and decoded; 5) ending the read sequence must not generate an error in recovered data. Knowledge of the foregoing requirements allows one to define the requirements of writing data 12 to the disk. In the present embodiment four distinct fields of information are contained within each section of written data. As illustrated in FIG. 5, these are a training field 30, a sync mark field 32, a user data field 34, and a write pad field 36.

The training field 30 is a repeating pattern of 0 1 0 three bit words. The training field 30 must be long enough for the PLL to obtain phase and frequency lock and then continue in length long enough for the encoder/decoder 16 to identify and synchronize to the 0 1 0 three bit word boundaries as opposed to synchronizing to a 0 0 1 or 1 0 0 pattern. By doing this, the reading requirements of 1) and 2) above are satisfied. It should be noted that with the magnetic recording encoder system 10 of the present invention, the training field 30 is constant for all written data.

The sync mark field 32 is also a known pattern other than the repeated 0 1 0 pattern of the training field 30 and can be generated by any non-repeating two bit pairs. The pattern of the sync mark field 32 is searched for and upon recognition signifies that user data follows immediately. The sync mark field 32 as described above satisfies the reading requirement 3) above.

The user data field 34 is a known number of three bit patterns which represent actual user data. The user data field 34 as described satisfies the reading requirement 4) above and the utility of this invention.

The write pad field 36 is extra data written to the disk, in the form of repeating 010 three bit words, which guarantees that the encoder 16 has completed all exception processing and to overwrite extraneous data present on the disk from the last write operation at this location. The write pad field 36 as described satisfies the reading requirement of 5) above.

The training field 30, the sync mark field 32, and the write pad field 36 are recognized as overhead required for proper reading and writing of data. It is preferable to minimize the size of these fields 30, 32, and 36 thereby yielding greater storage efficiency. The training field 30 and the write pad field 36 are two fields in which the encoder/decoder 16 can have an impact. Further, in having the encoder 16 generate the data for the training field 30 and the write pad field 36, the size of the data buffer can be reduced realizing more efficient use and less required buffer ram for the system.

The system of the present application has a mechanism for ensuring that the last predetermined number of data bits in the data field are free from an exception. Basically, the mechanism forces a non-exception word or two-bit pair which never causes an exception even for any extraneous bits at the end of the write data on the disk thereby guaranteeing to never run into a problem.

In operation, the mechanism is attached in parallel with the controller to the encoder. In other words, the mechanism is independent of the controller. When the user write gate data goes inactive, the mechanism disconnects the controller from the encoder. When the user write gate goes inactive, then the encoder recognizes that it needs to change the multiplexer so that it is always receiving a non-violating bit stream pair.

Once the controller has been disconnected by the encoder, the mechanism directs a non-violating two bit pair, i.e., 0 1, to the encoder. For instance, in the current embodiment of 0 1, the 0 1 two bit pair is preferred since from the primary RLL coding table, the 0 1 two bit pair translates into 0 1 0 which can precede or follow any other encoded constrained three bit symbol without forcing an exception. The mechanism forces the 0 1 two bit pair until a new user write gate is directed to the encoder by the controller. The mechanism forces the end of the data field to be exceptionless, i.e., the last three digits can never be an exception.

In practice, the 0 1 two bit pair is derived logically from a signal supplied by the controller to the mechanism within the encoder. The 0 1 two bit pair is merely being sent to the encoder and are not forced onto the disk. The mechanism interjects independent of the state of the controller data lines in a multiplex fashion the 0 1 signals at the end of the write gate.

The disk drive of the present invention preferably includes a carriage assembly which is described in U.S. patent application Ser. No. 08/965,223-(Attorney Docket No. CAL-P003) filed concurrently herewith and incorporated herein by reference. Furthermore, preferably, the disk 14 of the present invention includes servo sector architecture for a high density, removable media-type disk which is described in U.S. patent application Ser. No. 08/965,111 (Attorney Docket No. CAL-P001) filed concurrently herewith and incorporated herein by reference.

In the magnetic recording encoder system 10 of the present invention, FIG. 1 illustrates the appropriate block diagram of the encoder implementation for generating the above described requirements. Further, this is implemented in an Hardware Description Language (HDL) known as AHDL and is illustrated in Appendix A. The corresponding decoder implementation, also written in AHDL, is illustrated in Appendix B.

The foregoing exemplary descriptions and the illustrative preferred embodiments of the present invention have been explained in the drawings and described in detail, with varying modifications and alternative embodiments being taught. While the invention has been so shown, described and illustrated, it should be understood by those skilled in the art that equivalent changes in form and detail may be made therein without departing from the true spirit and scope of the invention, and that the scope of the present invention is to be limited only to the claims except as precluded by the prior art. Moreover, the invention as disclosed herein, may be suitably practiced in the absence of the specific elements which are disclosed herein.

__________________________________________________________________________APPENDIX A__________________________________________________________________________File: encoder.tdf Version: 9 Last modified: 10/06/97, 10:52am by JNv9 JN 10/06/97, 10:52am Jim finally figured out how to update a VCS project|?| v8 JN 10/06/97, 10:21am v7 JN 09/30/97, 02:19pm Added debug pins for endec troubleshooting v6 JN 08/28/97, 11:55am vcs maintenance v5 JN 06/27/97, 12:55pm Check-in to new location. v4 JN 08/20/97, 05:23pm v3 JN 08/20/97, 04:44pm Total Rewrite, Implementation through lookup table v1 LWL 08/13/97, 02:36pm Initial CheckinTITLE "1,7 Encoder";=================FILENAME: encoder.tdfLANGUAGE: ahdlAUTHOR: Jim NoxonLOCATION:DESCRIPTION:This code generates a 1,7 implementation of a channel encoder.Standard mapping of 2 bits to 3 bits is used. The followingtable indicates the general mapping of the input data;NRZ Data In Encoded Data Out__________________________________________________________________________0 0 0 0 10 1 0 1 01 0 1 0 01 1 1 0 1For those states where a violation would occur the outputdata stream is modified according to the following violationtable;NRZ Data In Encoded Data Out__________________________________________________________________________0 0 1 0 0 0 1 0 0 00 0 1 1 0 1 0 0 0 0 *1 1 1 0 1 0 1 0 0 01 1 1 1 1 0 0 0 0 0 **denotes those violations in which the preceeding symbol istranslated differently.Implementation of this encoder assumes that the first twobits of nrz data are presented at the time write gate (wg)goes high and then every third read reference clock (rr.sub.-- clk)thereafter.To minimize the timing problems due to delay from the encoder,a delayed write gate (dly.sub.-- wg) signal is generated that issynchronized with the data at the write data (wd) output.General implementation is to use a 2 bit counter (dbtc�!) heldin an idle state (dbtc�! == B"11") during times when write gateis held low. When write gate goes high, the counter rolls overand works in a divide by three mode counting from 0 to 1 to 2 andback to 0 again. This provides knowledge of where we are interms of serializing the output symbol. Write gate is expectedto go low after the last nrz pair is clocked in. This causes thecounter to count down and underflow into the idle state duringoutput of the last symbol. This methodology allows for simplifiedmapping of the delayed write gate signal to the state of thecounter.Symbol generation is done through a lookup table. The lookup tablehandles all code violations for the current symbol. For those twosymbols that require the modification of the previous symbol, aviolation flag (vflag) is set which then modifies the load procedureof the shift register (sr.sub.-- out�!) such that the previous symbol iscorrected before being shifted out.REVISION HISTORY:Date Person Description__________________________________________________________________________ 11/05/96 ST Initial creation. 03/02/97 dc Change to different 1,7 endec. 08/18/97 JN Complete revision for new 1,7 encoderThis media contains an authorized copy or copies of materia1 owned byCaleb Technology. This ownership notice and any other notices includedin machine readable copies must be reproduced on all authorized copies.This is confidential and unpublished property of Caleb Technology.All rights reserved.=================INCLUDE "GENERICS.INC"; -- support for modes of compilationSUBDESIGN encoder { rr.sub.-- clk : INPUT;read reference clock resetb : INPUT;active low reset signal nrz�1..0! : INPUT;2 bit nrz data wg : INPUT;write gate nwd : OUTPUT;negative serial write data output last bit : OUTPUT;represents state of last bit output dly wg : OUTPUT;delayed write gate synchronized with serial write dataVARIABLE sr out�5..0! : DFF;holds data to be output dbtc�1. .0! : DFF;holds a divide-by-three-counter load shift : SOFT;generates the active high load, active low shift signal vflag : SOFT;generates the violation state requiring change of currentoutput symbol tb out�1..0!�2..0! : SOFT;generates synbols for output from a translation table wgff : DFF;generates the delayed write gate symbol last : DFF;holds state of last data bit transfered out lnrz�1..0! : SOFT;local nrz data inputBEGIN- clock assignments sr out�!.clk = rr.sub.-- clk; dbtc�!.clk = rr.sub.-- clk; wgff.clk = rr.sub.-- clk; last.clk = rr.sub.-- clk;- reset assignments sr out�!.clm = resetb; dbtc�!.pm = resetb; wgff.clm = resetb; last.clm = resetb;- local nrz data implementation IF wg == VCC THEN -- if writing lnrz�! = nrz�!; -- get next data- if not writing- load non violating symbol END IF;- divide by three counter implementation IF wg == VCC THENif writing IF dbtc�! == 2 THENif ready to rollover counter dbtc�!= 0;rollover counter ELSEif counting dbtc�! = dbtc�! + 1;increment counter END IF;ELSEif not writing IF dbtc�! ? = 3 THENif not in idle state dbtc�! = dbtc�! - 1;decrement counter ELSEif in idle state dbtc�! = dbtc�!;hold idle state END IF;END IF;load shift implementationIF dbtc�! == VCC THEN -- if on last count or idle load.sub.-- shift = VCC;should be loadingELSEif not on last count and not idle load.sub.-- shift = GND;should be shiftingEND IF;delayed write gate implementationIF wg == VCC THEN -- if writing IF wgff == GND THEN -- if initiating a write IF dbtc�! == 2 THEN -- if ready for first symbol wgff = VCC;delayed write gate becomes trueELSEif not ready for first symbol wgff = GND;delayed write gate still falseEND IF;ELSEif in the middle of a write wgff = VCC;delayed write gate stays trueEND IF;ELSEif not writingIF wgff == GND THENif in between writes wgff = GND;delayed write gate stays falseELSEif at end of a write IF dbtc�! == 3 THENif in idle state wgff = GND;delayed write gate becomes falseELSEif finishing last symbol. wgff = VCC;delayed write gate still true END IF;END IF;END IF;the encode translation tableTABLElnrz�!, sr.sub.-- out�4..2! => tb.sub.-- out�1!�!, tb.sub.-- out�0!�!, vflag;B"00", B"XXX" => B"XXX", B"001", GND;00 can follow anythingB"01", B"XXX" => B"XXX", B"010", GND;01 can follow anythingB"10", B"000" => B"XXX", B"100", GND;data following violationsalways validB"10", B"001" => B"XXX", B"000", GND;following symbol onlyviolationB"10", B"010" => B"XXX", B"100", GND;10 can follow 01B"10", B"011" => B"XXX", B"XXX", GND;invalid encode, should notoccurB"10", B"100" => B"XXX", B"100", GND;10 can follow 10B"10", B"101" => B"XXX", B"000", GND;following symbol onlyviolationB"10", B"110" => B"XXX", B"XXX", GND;invalid encode, should notoccurB"10", B"111" => B"XXX", B"XXX", GND;invalid encode, should notoccurB"11", B"000" => B"XXX", B"101", GND;data following violationsalways validB"11", B"001" => B"010", B"000", VCC;following and current symbolviolationB"11", B"010" => B"XXX", B"101", GND;11 can follow 01B"11", B"011" => B"XXX", B"XXX", GND; invalid encode, should notB"11", B"100" => B"XXX", B"101", GND;11 can follow 10B"11", B"101" => B"100", B"000", VCC;foliowing and current symbolviolationB"11", B"110" => B"XXX", B"XXX", GND;invaiid encode, should notoccurB"11", B"111" => B"XXX", B"XXX", GND;invalid encode, should notoccurEND TABLE;output shift register implementationIF load.sub.-- shift == VCC THENif loading data sr.sub.-- out�2..0! = tb out�0!�!;load next symbol to outputIF(vflag == VCCY THENif in a violation state sr.sub.-- out�5..3! = tb.sub.-- out�1!�!;load modified symbol in upper registerELSEif not in a violation state sr.sub.-- out�5..3! = sr.sub.-- out�4. .2!;shift a bitEND IF;ELSEif not loading data sr.sub.-- out�5. .1! = sr.sub.-- out�4..0!;shift a bitEND IF;last data bit state implementationIF wgff == VCC THENif writing last = sr.sub.-- out�5!;assign last output bitELSEif not writing last = last;hold iast output bitEND IF;output assignmentsnwd = |sr.sub.-- out�5!;serial write data outputdly.sub.-- wg = wgff;delayed write gate outputlast bit = last;last bit outputEND;File: decoder.tdf Version: 4 Last modified: 10/06/97, 10:52am by JNv4 JN 10/06/97, 10:52am Jim finally figured out how to update a VCS project|?| v3 JN 08/29/97, 02:08pm Added psuedo sync detect signal to pin 7 of project. v2 JN 08/28/97, 11:01am New Decoder Initial Check In v1 JN 08/27/97, 01:00pm Initial checkinTITLE "1,7 Decoder";=============FILENAME: decoder.tdfLANGUAGE: ahdlAUTHOR: Jim NoxonLOCATION:DESCRIPTION:This file implements a 1,7 decoder with internal synchronizationto the tribit boundaries. A signal "locked" is provided to indicatethat the decoder is iocked to the tribit boundaries. The input wordlock.sub.-- len allows for a variable length of valid tribit boundariestobe validated before the locked signal is asserted.Implementation is through the use of a look up table which definesthe decode map used in the encoder. As read data bits are shifted inthey are added to the previous data bits read to generate a look upaddress for the look up table. When a violation code is read in thatrequires modification of the previous symbol for proper decoding, avflag signal is asserted to modify the normal operation of the inputdata shift register pipeline allowing the symbol to be corrected.Synchronization is accomplished through the use of a divide by threecounter and a flip flop indicating lock. The lock flip flop is clearedany time that read gate (rg) is low. Read gate going high enables thelock up logic to take control. While lock is low, the divide by threecounter (dbtc�!) is synchronized to each incomming 1 bit. If thesynchronization has caused an adjustment in the value of the divide bythree counter, the lock counter (lock.sub.-- cntr�!) is reset to 0. Ifthesynchronization is valid, the lock counter is incremented. Once thelock counter increments to the value on the lock ien input wordsynchronization is assumed locked and the lock flip flop is asserted.The lock flip fiop reinains in the locked state until read gate isbrought low.A signal named sym.sub.-- err is generated through the use of the lookuptable. This signal indicates that an invalid symbol combination hasoccured even though this error inay not violate the 1,7 code constraint.One possible example of this is . . . 001 000 000 100 . . .Clearly there is no 1,7 code vioiation here but this sequence can notlegally occur since the symbol stream 000 000 has no corrospondingdecode stream.REVISION HISTORY:Date Person Description__________________________________________________________________________ 08/25/97 JN Initial attempt at a DecoderThis media contains an authorized copy or copies of material owned byCaleb Technology. This ownership notice and any other notices inciudedin machine readable copies must be reproduced on all authorized copies.This is confidentiai and unpublished property of Caleb Technology.All rights reserved.==============INCLUDE "GENERICS.INC"; -- support for modes of compilationSUBDESIGN decoder {rr.sub.-- clk : INPUT; -- read reference clockrd : INPUT; -- read data inresetb : INPUT; -- system resetrg : INPUT; -- read gatelock.sub.-- len�5..0! : INPUT; -- number of vaiid tribit frames to justify lock on sync fieidpatternnrz�1..0! : OUTPUT; -- nrzdata outsym.sub.-- err : OUTPUT; -- symbol in violation of encode schemerd.sub.-- clk : OUTPUT; -- read data clock synchronized with read datalocked : OUTPUT; -- indicates decoder is locked to sync field patternpsync.sub.-- det : OUTPUT; -- psuedo sync detectVARIABLEdbtc�1..0! : DFF; -- divide by three countercur.sub.-- sym�4..0! : DFF; -- holds input data and output nrz datacur.sub.-- nrz�1..0! : DFF; -- holds currently translated nrz dataprev.sub.-- nrz�1..0! : DFF; -- holds output nrz dataerr : DFF; -- holds symbol in error dataiock : DFF; -- identifeds if state counter locked to sync field patterniock.sub.-- cntr�5. .0! : DFF; -- counts vaiid tribit frames during sync field patternprev.sub.-- tbi�1..0! : NODE; -- generates the corrected previous rirz data bit paircur.sub.-- tbi�1. .0! : NODE; -- generates the current nrz data bit pairtbl.sub.-- input�5..0! : NODE; -- generates the numeric input for the look up tablevflag : NODE; -- generates the violation flagtbl.sub.-- err : NODE; -- generates the symbol error status flagIF DEBUG CIRCUITRY |= 0 GENERATEpsync.sub.-- det.sub.-- ff : DFF; -- holds psuedo sync detect statusEND GENERATE;BEGINclock assigrunentsdbtc�!.clk = rr.sub.-- clk;cur.sub.-- sym�!.clk = rr.sub.-- clk;cur.sub.-- nrz�!.clk = rr.sub.-- clk;prev.sub.-- nrz�!.clk = rr.sub.-- clk;err.clk = rr.sub.-- clk;lock.clk = rr clk;lock.sub.-- cntr�!.clk = rr.sub.-- clk;reset assignmentsdbtc� .clrn = resetb;cur.sub.-- sym�!.clrn = resetb;cur.sub.-- nrz�!.clrn = resetb;prev.sub.-- nrz�!.clrn = resetb;err.clrn = resetb;lock.clrn = resetb;lock.sub.-- cntr�!.clrn = resetb;lock to sync pattern implementationIF rg == GND THEN -- if not reading lock = GND;ELSE -- if reading IF lock == GND THEN -- if not yet locked up IF lock.sub.-- cntr�! == lock.sub.-- len�! THEN -- if reached lockcount lock = VCC; -- indicate that we are locked ELSE lock = GND; -- indicate that we are not locked END IF; ELSE -- if already locked up lock = VCC; -- hold lock state END IF;END IF;lock counter implementation- if not readingNlock.sub.-- cntr�! = 0;hold counter in ready stateELSEif reading IF rd == VCC THENif a one bit in the read data IF dbtc�! == 1 THENif it is synchronous with state counter lock.sub.-- cntr�! = lock.sub.-- cntr�!+ 1;increment the counter ELSEif not synchrouous iwth state counter lock.sub.-- cntr�! = 0;reset the counter END IF;ELSEif not a one bit in the read data IF dbtc�! | = 1 THENif it is synchronous with state counter lock.sub.-- cntr�! = lock.sub.-- cntr�!;hold current count value ELSEif it is not synchronous with state counter lock.sub.-- cntr�! = 0;reset the counter END IF; END IF;END IF;divide by three counter implementationIF lock == VCC THENif locked up to sync field IF dbtc�! == 2 THENif counter at maximum dbtc�! = 0;roll over the counter ELSEif counter not at maximum dbtc�! = dbtc�! + 1;increment the counter END IF;ELSEif not locked up to sync field IF rg == VCC THENif reading IF rd == VCC THENif a one bit in the read data dbtc�! = 2;synchronize state counter ELSEif not a one bit IF dbtc�! = 2 THENif counter at maximum dbtc�! = 0;roll over counter ELSEif counter not at maximum dbtc�! = dbtc�! + 1;increment the counter END IF; END IF;ELSEif not reading IF dbtc�! == 2 THENif counter at maximum dbtc�! = 0;roll over the counter ELSEif counter not at maximum dbtc�! = dbtc�! + 1;increment the counter END IF; END IF;END IF;psuedo sync detect implementationIF DEBUG.sub.-- CIRCUITRY |= 0 GENERATE psync.sub.-- det.sub.-- ff.clk = rr.sub.-- clk;clock assignment IF lock == VCC THENif acquired lock IF psync.sub.-- det.sub.-- ff == GND THENif psuedo sync not detected yet IF dbtc�! == 2 THENif on a tribit boundary IF cur.sub.-- sym�2..0! |= B"001" THENif not in training field psync.sub.-- det.sub.-- ff = VCC;assert psuedo sync detect ELSEif in training field psync.sub.-- det.sub.-- ff = GND;maintain sync not found status END IF; END IF; ELSEif psuedo sync detected psync.sub.-- det ff = VCC;maintain sync found status END IF; ELSEif not locked and ready to search for psuedosync psync.sub.-- det.sub.-- ff = GND;prepare for when ready to search END IF; psync det = psync.sub.-- det.sub.-- ff;assign outputELSE GENERATE psync det = GND;set default pin stateEND GENERATE;input shift register implementationcur.sub.-- sym�4..! = cur sym�3..0!;shift up bitcur.sub.-- sym�0! = rd;shift in data bitinput data pipeline implementationIF dbtc�! == 2 THENif on a tribit boundary IF vflag == VCC THENif this is a violation prev.sub.-- nrz�! = prev.sub.-- tbl�!;correct previous nrz data ELSEif this is not a violation prev.sub.-- nrz�! = cur.sub.-- nrz�!;shift up current nrz data END IF; cur.sub.-- nrz�! = cur.sub.-- tbl�! ;get current nrz dataELSEif not on a tribit boundary prev.sub.-- nrz�! = prev.sub.-- nrz�!;hold previous nrz data cur.sub.-- nrz�! = cur.sub.-- nrz�!;hold current nrz dataEND IF;symbol error detection implementationIF dbtc`== 2 THENif only tribit boundary err = tbl err;get symbol error statusELSEif not on a tribit bdundary err = err;maintain current error statusEND IF;translation table for input pipelinetbl.sub.-- input�5..1! = cur.sub.-- sym�!;tbl.sub.-- input�0! = rd;TABLEtbl.sub.-- input�! => prev.sub.-- tbl�!, cur.sub.-- tbl�!, vflag, tbl.sub.-- err;B"000001" => B"XX", B"00", GND, GND;B"000010" => B"XX", B"01", GND, GND;B"000100" => B"XX", B"10", GND, GND;B"000101" => B"XX", B"11", GND, GND;B"001000" => B"XX", B"10", GND, GND;B"001001" => B"XX", B"00", GND, GND;B"001010" => B"XX", B"01", GND, GND;B"010000" => B"00", B"11", VCC, GND;B"010001" => B"XX", B"00", GND, GND;B"010010" => B"XX", B"01", GND, GND;B"010100" => B"XX", B"10", GND, GND;B"010101" => B"XX", B"11", GND, GND;B"100000" => B"11", B"11", VCC, GND;B"100001" => B"XX", B"00", GND, GND;B"100010" => B"XX", B"01", GND, GND;B"100100" => B"XX", B"10", GND, GND;B"100101" => B"XX", B"11", GND, GND;B"101000" => B"XX", B"10", GND, GND;B"101001" => B"XX", B"00", GND, GND;B"101010" => B"XX", B"01", GND, GND;invalid symbol combinationsB"000000" => B"XX", B"XX", GND, VCC;B"XXXX11" => B"XX", B"XX", GND, VCC;B"XXX11X" => B"XX", B"XX", GND, VCC;B"XX11XX" => B"XX", B"XX", GND, VCC;B"X11XXX" => B"XX", B"XX", GND, VCC;B"11XXXX" => B"XX", B"XX", GND, VCC;END TABLE;output assignmentsnrz�! = prev.sub.-- nrz�!;sym.sub.-- err = err;locked = lock;rd.sub.-- clk = dbtc�1!;END;__________________________________________________________________________

Claims

1. An encoder for receiving a write gate code from a data receiving controller, the data receiving controller directing write gate data in the form of 0 and 1 bits to the encoder, the encoder in response to the write gate data producing a run length limited (RLL) code in the form of 0 and 1 bits dependent on the write gate data and directing the RLL code to the disk, the RLL having criteria including a coding rate of 2/3 which requires a minimum of one 0 and a maximum of seven 0's between adjacent 1's, the encoder producing a secondary coding rate as an exception when the write gate data does not result in the RLL code criteria, the encoder comprising:

a multiplexer that, in response to a signal, selects the source of data for encoding from one of the data receiving controller and a second source;

means for converting the data provided by the source selected by the multiplexer into a RLL code.

2. The encoder of claim 1 wherein said second source includes a two bit pair generating mechanism for injecting a two bit pair into said means for converting.

3. The encoder of claim 2 wherein said two bit pair generating mechanism is a 0 1 generator for generating a 0 1 two bit pair.

4. In a system for encoding a data field on a disk with a write gate data, the system having an encoder and a data receiving controller for directing write gate data in the form of 0 and 1 bits to the encoder, the encoder in response to the write gate data producing a run length limited (RLL) code in the form of 0 and 1 bits dependent on the write gate data and directing the RLL code to the disk, the RLL having criteria including a coding rate of 2/3 which requires a minimum of one 0 and a maximum of seven 0's between adjacent 1's, the encoder producing a secondary coding rate as an exception when the write gate data does not result in the RLL code criteria, the improvement comprising:

a multiplexer that, in response to a signal, selects the source of data for encoding from one of the data receiving controller and a second source;

means for converting the data provided by the source selected by the multiplexer into a RLL code.

5. The improvement of claim 4 wherein said second source includes a two bit pair generating mechanism for injecting a two bit pair into said means for converting.

6. The improvement of claim 5 wherein said two bit pair generating mechanism is a 0 1 generator for generating a 01 two bit pair.

7. A method for encoding a data field on a disk with write gate data, the method comprising the steps of:

providing an encoder;

providing a data receiving controller providing write gate data, producing a user write gate signal, and producing a write gate signal;

directing the write gate data in the form of 0 and 1 bits to the encoder when said user write gate signal is in a first state and other data from a source other than the data receiving controller that is in the form of 0 and 1 bits to the encoder when said user write gate signal is in a second state that is different than said first state; and

producing a run length limited (RLL) code in the form of 0 and 1 bits from the encoder in response to the write gate data, the RLL code having criteria including a coding rate of 2/3 which requires a minimum of one 0 and a maximum of seven 0's between adjacent 1's.

8. The method of claim 7 wherein said step of directing includes disconnecting the encoder from the controller in response to and at the end of the user write gate signal.

9. The method of claims 7 wherein said step of directing includes connecting the encoder to a means for providing said other data and ensuring that the last predetermined number of bits in the data field are not an exception.

10. The method of claim 9 wherein the means includes a two bit pair generating mechanism for injecting a two bit pair into the encoder.

11. The method of claim 10 wherein said two bit pair generating mechanism is a 0 1 generator for generating a 0 1 two bit pair.

12. In a system for encoding a data field on a disk with a write gate data, the system having an encoder and a data receiving controller for directing write gate data in the form of 0 and 1 bits to the encoder, the encoder in response to the write gate data producing a primary code in the form of 0 and 1 bits and directing the primary code to the disk, the primary code having certain predetermined criteria, the encoder producing a secondary coding rate as an exception when the write gate data does not result in predetermined criteria, the improvement comprising:

a multiplexer that, in response to a signal, selects the source of data for encoding from one of the data receiving controller and a second source;

means for converting the data provided by the source selected by the multiplexer into a primary code.

13. The improvement of claim 12 wherein said second source includes a two bit pair generating mechanism for injecting a two bit pair into said means for converting.

14. The improvement of claim 13 wherein said two bit pair generating mechanism is a 0 1 generator for generating a 0 1 two bit pair.