Magnetic resonance gyro phase shifter

Abstract

A phase shifter of a signal processor which involves separation of the cell signals from a magnetic resonance gyro (MRG) using phase locked loops that also serve as frequency multipliers, phase shifting one cell output to maintain phase comparisons within the monotonic region of the phase detectors, PDM/Digital conversion of the MRG signals and finally microcomputer processing to obtain gyro angle to the required resolution and update rate.

Description

PRIOR ART

U.S. Pat. No. 3,778,700, Bayley et al., 12/73.

U.S. Pat. No. 3,808,542, Ferriss, 4/74.

This invention is related to the magnetic resonance gyro. More particularly, this invention is a signal processor for converting the gyro output angle to digital form.

BACKGROUND OF THE INVENTION

The atomic nuclei of certain materials possess magnetic moments which arise out of their inherent angular moments or spin properties. These special properties of certain materials form the principle upon which the nuclear gyro operates.

U.S. Pat. No. 3,778,700, assigned to the same assignee as the present invention, discloses an optically pumped nuclear magnetic resonance gyroscope device in the preferred embodiment of which two different isotopes of mercury are utilized in the cells of two interconnected spin generators. As taught therein, each spin generator comprises a mercury absorption cell containing .sup.199 Hg and .sup.201 Hg which is subjected to a DC magnetic field, H.sub.o and to an AC magnetic field, H.sub.1 perpendicular to field H.sub.o. The magnetic fields H.sub.o of the two cells are described as being equal and antiparallel to each other. The mercury absorption cells are optically pumped by a circularly polarized beam of light to increase the magnitude of the net magnetic moment and phase comparison means are provided to derive a readout signal representative of of gyro angular rotation about a given axis by comparing and phase outputs of the two spin generators.

The disadvantages of the prior art early schemes were:

1. Gyro output was in analog forms not readily useable by modern-day navigation computers without conversion.

2. Mechanization required bulky and expensive electro-mechanical devices which are slow in response time.

3. Stability of the phase shift introduced by the resolver scheme is dependent not only on the resolver characteristics, but also on the stability of the resistor and capacitor (the phase shifter works ideally only at a single frequency).

4. Filters prior to the resolver introduce phase instability with time degrading output.

Thus, there is a need to implement a system which will provide digital signals which will satisfy the fast mid-course corrections of present day missiles and other gyro controlled devices.

BRIEF SUMMARY OF THE INVENTION

Briefly, the apparatus of the present invention comprises a magnetic resonance gyro having a digital phase shifter which converts the gyro's inherent analog signals into digital pulse count and a residual PDM signal which is further converted to a digital word. The set of digitized signals are applied to a microprocessor system where the digital gyro output angle is constructed for use by the navigation or guidance computer.

Accordingly, it is an object of this invention to provide a means for converting the analog signals from a magnetic resonance gyro to digital signals for direct measurement of gyro angle by modern-day navigation and guidance computers.

This and other objects, features and advantages of the present invention will become more apparent from the following description taken in conjunction with the accompanying drawings wherein:

FIG. 1 is a simplified block diagram of a conventional magnetic resonance gyro;

FIG. 2 is a block diagram in servo-oriented format of the mechanization of the gyro elaborated upon by this invention;

FIG. 3 is a more detailed block diagram of the phase shifter of FIG. 2;

FIG. 4 shows the signal inputs to the phase shifter of FIG. 3;

FIG. 5 shows the selected monotonic range of the transfer characteristics of the phase detector of FIG. 2;

FIG. 6 shows the pulse duration modulation to digital converter;

FIG. 7 shows the three full periods of the pulse duration modulation input waveforms and the corresponding digital output; and

FIG. 8 shows the microprocessor with the outputs of the PDM/Digital converter and with the .DELTA..phi. pulses inputted to an Up/Down counter.

Referring to FIG. 1, there is shown a simplified block diagram of a magnetic resonance gyro that outputs an analog signal which is subsequently digitized according to the invention. The spin generator cells 10 and 11 comprise absorption cells containing .sup.199 Hg and .sup.201 Hg which is subjected to a DC field H.sub.o. In the spin generator loops, the phase stable amplifiers 12 and 13, receive input signals from photodiodes (not shown) associated with each cell and supply energy to the nuclei of the mercury isotopes to sustain steady-state Larmor oscillations. The composite cell signals are supplied to the signal processor 14 which provides angular output information.

A more detailed diagram in the classical control system format of a magnetic resonance gyro mechanization is shown in FIG. 2. Cells 10 and 11 are shown in dotted outline. The four phase locked loop (PLL) frequency/phase multipliers 29,30,40 and 42 scale output phases by a factor N, prior to phase comparison in phase shifters 31 and 32. Because phase detectors 37 and 39 are monotonic over a range of only .pi. radians some kind of phase shifter is required to prevent sense changes. The need for a phase shifter can be recognized by assuming a fixed input rate considering the angles which would accumulate at the inputs to the phase detector over time. The phase shifter is introduced by G.DELTA..phi. block 36 which feeds back a phase identified as M.DELTA..phi. tending to restrict the magnitude of the output of the phase detector. In earlier mechanizations, this was implemented using a pair of resolvers for the phase shifters with shafts connected together. The G.DELTA..phi. block 36 was a servo amplifier driving a motor to which the resolvers' shafts were connected. Thus the output .DELTA..phi..sub.2 of phase detector 39 is driven to null by the null-seeking servo containing the G.DELTA..phi. block 36. Under that mechanization, the integrated rate, .omega.n/S=.theta..sub.r, is given by: ##EQU1## Thus, the gyro output is proportional to the resolver shaft angle and may be outputted in this manner. Requirements for strapped-down gyros for use in navigation systems in the 1 n.m. per hour class call for an angular resolution of 1 sec. To operate a resolver/synchro output to digitize to that resolution it would require a 20 bit converter to achieve 1.24 sec. resolution: ##EQU2## This resolution requirement surpasses the performance capabilities of fast rate tracking converters.

The essentials of the digital phase shifter of the present invention can be explained by using FIG. 2. Here the output of phase detector 39 is allowed to accumulate an output angle .DELTA..theta..sub.2 by placing a dead-band in block 36 (G.DELTA..phi.). When .DELTA..phi..sub.2 exceeds the dead-band a quantum of phase shift .DELTA..phi. is introduced into phase shifters 31 and 32 within the period of the phase detection, thus shifting .DELTA..theta..sub.2 by an amount -.DELTA..phi.. The number of .DELTA..phi.'s introduced is accumulated in a counter (see reference symbol 82 in FIG. 8) which totalizes .DELTA..phi. pulses thus containing .+-.M.DELTA..phi.. The total output of the gyro is contained by the quantized value M.DELTA..phi. and the residual .DELTA..phi..sub.2. Moreover, block 34 (G.DELTA.H) is operated as a null-seeking servo forcing .DELTA..theta..sub.1 =.DELTA..theta..sub.2. The quantities labelled OUTPUT are:

.DELTA..theta..sub.1 =2N.sub..theta.r +M.DELTA..phi. (3a) .DELTA..theta..sub.2 =-2N.sub..theta.r -M.DELTA..phi. (3b) and .DELTA..phi.

In the PDM to digital converter (FIG. 6) digital conversions of .DELTA..theta..sub.1 and .DELTA..theta..sub.2 are performed at a binary sub-multiple level of .DELTA..phi.. The remaining operations include subtraction of (3b) from (3a), subtraction of M.DELTA..phi. from the result and division by 4N by bit location recognition, thus producing .theta..sub.r, all performed by the microcomputer of FIG. 8.

Having briefly described the overall signal processing scheme, each of the elements will now be considered in more detail.

Turning to FIG. 3, a block diagram of the digital phase shifter 31 is shown. Noting that the block diagram of 32 is identical to block 31, the two input signals, N.theta..sub.2A and N.theta..sub.2B to the phase shifters 31 and 32 are square waves from the phase-locked-loop frequency multipliers which have raised the cell output signals to a frequency N times the original. Input signal N.theta..sub.2A is applied along with clock pulse CL2A to eight stage shift register 53 and input pulse signal N.theta..sub.2B along the clock pulse CL2B is applied to advancer retarder detector 54. The clock pulse inputs are square waves at a frequency eight times the input signals. These signals are generated within the phase-locked-loop frequency multipliers and are frequency and phase-locked with their respective input signals as shown in FIG. 4. The output from the eight stage register 53 is applied to eight channel multiplexer 56. Also applied to block 56 are three bit address lines from three stage up/down counter 57. The advancer retarder detector provides an output signal +.DELTA..phi. and -.DELTA..phi. which are applied to gating circuit 58 and to the angle counter (not shown). Gating circuit 58 has a third input, clock pulse CL2A and outputs to up/down counter 57. The output of the eight channel multiplexer 56 is a signal N.theta..sub.2A -M.DELTA..phi. which is applied as an output signal to the phase detector and to the advancer retarder detector 54.

The fundamental purpose of the digital phase shifter is to maintain the signals N.theta..sub.2A -M.DELTA..phi. and N.theta..sub.2B which go to the phase detector within a selected monotonic range of the transfer characteristic as shown in FIG. 5 for an Exclusive OR gate 59. The output can be in terms of either the logic "1" level output duty cycle or the average value of the output voltage. The point to be made is that the transfer characteristic is periodic having positive and negative slopes. The region to which operation is confined by the action of this digital phase shifter is between .pi./8 and 7.pi./8, shown by the dotted lines. Within the advancer-retarder detector 54 an electronic "window" is effectively generated. Relative phases N.theta..sub.2A -M.DELTA..phi. activation of the phase shifter. As the relative phase equals or exceeds the window limits an output pulse is generated on one of the lines +.DELTA..phi. or -.DELTA..phi.. After synchronization to the CL2A within gating circuit 58, three stage ring counter 57 is incremented or decremented. The counter contents represented by the states of three flip-flops determine a binary number 0 through 7 which represents closure of one of eight input switches of multiplexer 56. The incrementing or decrementing of the ring counter 57 causes the switch previously closed to open and an adjacent switch to close which connects the correspondingly numbered state of shift register 53 to the output line of multiplexer 56. Within shift register 53 at any time are eight images of the input N.theta..sub.2A each shifted in phase by .pi./4 (1/8 of 2.pi.) by the action of the clock CL2A operating at eight times the input frequency. The selection of an adjacent stage of shift register 53 thus is tantamount to shifting the output phase by a quantized increment of .pi./4 radians. The appearance of N.theta..sub.2A -M.DELTA..phi. on the output line, with M now having been incremented or decremented by one, effects the phase shift of .pi./4 causing the phase comparison, previously residing at either .pi./8 or 7.pi./8 on the phase detector transfer characteristic to shift toward the center of the characteristic, to either 3.pi./8 or 5.pi./8 dependent on phase advancement or retardation. The .+-..DELTA..phi. pulse generated is accumulated in the angle counter of FIG. 8 as a measure of total digital phase shift, .+-.M.DELTA..phi..

The completion of the phase shifting sequence is achieved within three clock pulses allowing a maximum phase shifting rate of one quantum per period of input. That is dm/dt is equal to the frequency of the input:

dm/dt=Nf.sub.c (4) where f.sub.c is the frequency of Larmor oscillation associated with .gamma..sub.2.

Differentiating equation (1) with respect to time and substituting equation (4): ##EQU3## For .DELTA..phi.=.pi./4, f.sub.c =1000, .omega..sub.r =12.5.pi. or greater than 6 revolutions per second. This is the only electronics-imposed rate limitation apparent at this time.

Turning to FIG. 6, there is shown a schematic block diagram of the PDM to digital converter. A PDM input from the phase shifter of FIG. 3 is applied to phase detector 60 and gating circuit 61. Phase detector 60 also receives a signal from counter divider 62. The output of phase detector 60 is applied to low pass filter circuit 63 and the output of circuit 63 is applied to voltage control oscillator 66 which converts the dc input into pulse output. The blocks enclosed in the dotted outline are a conventional PLL (phase-lock loop) frequency multiplier. The pulse signals from the voltage control oscillator 66 is applied to the counter divider 62 and gating circuit 61. Gating circuit 61 provides four output signals for application to counter 67. Gating circuit 61 provides serial output signals on line c and counter 67 provides parallel binary word output. The output frequency is P times the input frequency f.sub.in. Or another way of thinking of it, within each period of the input are generated P output pulses. Usually a binary ripple counter is used as the frequency divider such that P is some integral power of 2.

The total gyro angle .theta..sub.r is contained in the pulse count M multiplied by the phase shift weighting of .DELTA..phi. plus the residual angle represented by the index of modulation of the pulse duration modulation outputs of the phase detectors.

When 50% duty-cycle square waves are applied to the exclusive OR gate 59 (FIG. 5) used as a phase detector, the output signal is a PDM wave at a frequency twice that of the input frequency. The range from -100% modulation (duty cycle=0) to +100% modulation (duty cycle=maximum) corresponds to a range of the phase detector transfer characteristic of .pi. (r). From equation (3) that equivalent gyro angle is:

.pi.=2N.theta..sub.p The equivalent gyro angle stored in the PDM wave is: ##EQU4##

By operating the multiplied input frequency and the PDM input signal into AND gate 61 an output pulse train is generated wherein for each period of the input PDM wave the number of output pulses, expressed as a fraction of P is numerically equal to the duty cycle of the input PDM waveform. By use of gating circuit 61 the counter 67, with preset capability and built-in latches, can output in the following manner:

1. During that portion of the PDM input where the input is high or at the logic 1 value the binary output word is that from the previous PDM period.

2. At the point in time where the PDM input goes low the binary output changes to a value representative of the current PDM period.

This is illustrated in FIG. 7 where three full periods of a PDM input wave are shown with the duty cycle varying linearly from 5/8 to 3/8. Assume for example P=2.sup.8 =256. Since the value of the PDM wave preceding the first shown, the output value is unknown except that it would lie between 00000000 and 11111111. At the negative going transition of the first PDM wave K=0.625.times.256=160 pulses would have incremented the counter to read 10100000 and the output would be latched at that time, after unlatching the counter is zeroed to await the positive going input of the next PDM wave. Meanwhile, the latches cause the output to remain displayed until updating at the next negative going transition.

Now, fixing more numbers to this example, assume N=8 for the multipliers associated with .gamma.2 frequency of 1 KHZ. By equation (6) the PDM wave, at 16 KHZ, contains 11.25.degree. of the equivalent input angle. With P=2.sup.8 the least significant bit of the contents of the counter in the PDM to Digital Converter (or the angular value of the serial pulse) is 11.25.degree..div.2.sup.8 =0.044. The frequency of operation of the VCO in the converter is 16 KHZ.times.2.sup.8 =4.096 MHz.

Other options are available using this general scheme. The counter could be preset to -P/2 instead of being zeroed thus removing the offset angle. Also, multiple period averages could be generated by zeroing or presetting and latching after a selected number of PDM periods have taken place. If the number A is chosen as the number of periods over which summation takes place, equations for the quantization level and the time between updates can be developed and are: ##EQU5## The frequency of oscillation of the VCO in the converter is the limiting frequency and can be expressed by:

f.sub.(VCO) =2NPF.sub.c(.gamma.) (9) Assuming a center frequency of 16.384 MHZ as a conservative choice equation (9) produces a value NP=8.192.times.10.sup.3. Imposing a 1.24 sec resolution requirement from equation (2) and solving for A in equation (7) a value of 32 is obtained. Finally from equation (8) a time between updates of 2 ms. is obtained. The combination of 1.24 sec resolution, 2 ms. update rate and the rate handling capability of 2250 degrees per second satisfies not only the most stringent requirements for strapped down navigation systems, but also for all but the high spin rate stabilized tactical guidance applications.

Referring to FIG. 8, the processing of the digital signals is accomplished by use of the microprocessor shown. The outputs of the two PDM/Digital Converters are inputted to a pair of asynchronous interface adapters 30, 81 while the .DELTA..phi. pulses are counted by an up/down counter 82 and paralleled into a peripheral interface adapter 83. Interconnecting the microprocessor unit with I/0 interface and interface I.C.'s (integrated circuits) and memory I.C.'s (integrated circuits) is the parallel data bus 84. The read only memory 86 (ROM) contains the program which operates on equation (3) to yield gyro input angle .theta..sub.r with the appropriate averaging. The random access memory 87 (RAM) stores interim computations, performed by the microprocessor 88, or in an expanded processing version of this microcomputer, stores moving average computations, based on a triangular averaging technique. At the output of the microprocessor through a pair peripheral adapters 89 and 90 is the 20 bit binary word (1.24 sec LSB) representing total MRG gyro input angle .theta..sub.r, updated at the required rate.

While particular embodiments of the invention have been shown and described, modifications may be made, and it is intended in the following claims to cover the embodiments which fall within the true spirit and scope of the invention.

Claims

1. A phase shifter comprising:

a source of input signals,

a shift register containing eight images of said input signal,

an eight channel multiplexer connected to said shift register for maintaining the phase shifted input signals within a selected monotonic range,

an advancer retarder detector connected to the output of said eight channel multiplexer for developing an electronic window for retarding the input signals which fall within said electronic window,

a gating circuit connected to the output of said advancer retarder detector, and

a three stage up/down counter connected to the output of said gating circuit and providing a three bit address to the input of said eight channel multiplexer said gating circuit operative under said advancer retarder detector to alter the contents of said three stage counter whereby flip-flops in said counter determine a binary number 0 through 7 which represents closure of one of eight switches of said eight channel multiplexer, said altering of said counter causing switches in said eight channel multiplexer which were previously closed to open and causing adjacent switches which were previously open to close thereby connecting the correspondingly numbered state of said shift register to the output line of said eight channel multiplexer.

2. The phase shifter of claim 1 wherein said input signals to said shift register comprises:

a source of signals from a magnetic resonance gyro which has been multiplied N times the original, and

a source of clock pulses consisting of square waves at a frequency eight times that of said input gyro signals.

3. The phase shifter of claim 2 comprising:

a second input signal from said gyro which has been multiplied N times the original connected to said advancer retarder whereby the relative phases between said first and second gyro signals which fall within said electronic window of said advancer retarder produce no activation of said shift register.