Patent Application
20070267709
This application is based on Japanese Patent Applications No. 2004-100841 filed on Mar. 30, 2004, No. 2004-124460 filed on Apr. 20, 2004, and No. 2005-5653 filed on Jan. 12, 2005, the disclosures of which are incorporated herein by references.
The present invention relates to a magnetic sensor having a vertical Hall device and a method for manufacturing the same.
In general, a lateral Hall cell detects a magnetic field component perpendicular to a substrate surface (i.e., a chip surface). The lateral Hall cell is disclosed in, for example, “Integrated three-dimensional magnetic sensor” in Journal of Institute of Electrical Engineers of Japan, Vol. 109-C, No. 7, pages 483-490 (1989). However, it is difficult for the lateral Hall device to detect a magnetic field component parallel to the substrate surface.
To detect the magnetic field component parallel to the substrate surface, a vertical Hall device as a vertical type Hall device is provided. The vertical Hall device is disclosed in, for example, Japanese Patent Application Publication No. H01-251763. The vertical Hall cell can detect the magnetic field component in parallel to the chip surface.
However, an epitaxial substrate is necessitated to provide the vertical Hall device. Therefore, the design degree of freedom is limited to use the epitaxial substrate.
In view of the above-described problem, it is an object of the present invention to provide a vertical Hall device having high design degree of freedom. It is another object of the present invention to provide a method for manufacturing the vertical Hall device having high design degree of freedom.
A vertical Hall device includes: a substrate; a semiconductor region having a first conductive type and disposed in the substrate; and a magnetic field detection portion disposed in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate in a case where a current flows through the magnetic field detection portion in a vertical direction of the substrate. The semiconductor region is a diffusion layer including a conductive impurity doped and diffused therein.
In the above device, the semiconductor region is made of a diffusion layer. Therefore, the substrate can be prepared from a single conductive type substrate, an epitaxial substrate, SOI substrate or the like. Thus, the design degree of freedom for selecting the substrate is increased. Thus, the vertical Hall device has high design degree of freedom.
Preferably, the device further includes a separation wall having a second conductive type and disposed in the semiconductor region for separating the magnetic field detection portion electrically. The separation wall provides a current path in such a manner that the separation wall selectively narrows near a bottom of the semiconductor region. More preferably, the separation wall is disposed from the surface of the semiconductor region to a predetermined depth of the semiconductor region so that the current path is formed between a bottom of the separation wall and a bottom of the semiconductor region.
Preferably, the device further includes: a first, a second and a third current supply terminals disposed on the surface of the semiconductor region; and a first and a second voltage output terminals disposed on the surface of the semiconductor region. The first and the second current supply terminals flow the current through the magnetic field detection portion in the vertical direction of the substrate. The first and the third current supply terminals flow the current through the magnetic field detection portion in the vertical direction of the substrate. The first and the second voltage output terminals output a Hall voltage signal corresponding to the magnetic field parallel to the surface of the substrate. The first current supply terminal is disposed between the first and the second voltage output terminals. The second and the third current supply terminals are disposed symmetrically on either side of a line between the voltage output terminals.
Preferably, the surface of the substrate is parallel to a predetermined surface orientation of crystal, which shows a resistance change in accordance with a stress application caused by a Piezo resistance effect, the resistance change of the predetermined surface orientation is smallest among those of other surface orientations.
Further, a method for manufacturing a vertical Hall device includes the steps of: forming a semiconductor region having a first conductive type in a semiconductor substrate in such a manner that an impurity having the first conductive type is doped and diffused in the substrate; and forming a magnetic field detection portion in the semiconductor region. The magnetic field detection portion is capable of detecting a magnetic field parallel to a surface of the substrate in a case where a current flows through the magnetic field detection portion in a vertical direction of the substrate.
The above method provides the vertical Hall device having the substrate. The design degree of freedom for selecting the substrate is increased. Thus, the vertical Hall device has high design degree of freedom.
The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. In the drawings:
The inventor have preliminarily studied about a Hall cell as a comparison of a Hall device according to a first embodiment of the present invention. Firstly,
In
VH=(RHIB/D)cos θ, and
RH=1/(QN).
Here, a Hall coefficient is defined as RH, a charge is defined as Q, and a carrier density in the cell is defined as N.
Therefore, the Hall voltage VH is changed in accordance with the angle θ between the Hall cell and the magnetic field. To use this relationship, the angle θ can be detected by the Hall cell. Thus, the Hall IC provides an angle detection sensor. In general, a lateral Hall cell detects a magnetic field component perpendicular to a substrate surface (i.e., a chip surface). The lateral Hall cell shown in
In the region 22, a diffusion layer 24 as a P type diffusion separation wall is formed so that the diffusion layer 24 separates between the Hall cell and other electric parts. The diffusion layer 24 reaches the semiconductor substrate 21. An active region 22a surrounded by the diffusion region 24 is disposed on the surface of the semiconductor region 22. In the active region 22a, a contact regions 23a-23d as a N+ diffusion region is formed. The contact region 23a-23d has high impurity concentration selectively increased. Each contact region 23a-23d has an electrode, which is connected to the contact region 23a-23d with excellent ohmic contact. Specifically, the contact regions 23a-23d are disposed on corners of the active region 22a so that a line connecting between the contact regions 23a, 23b is perpendicular to another line connecting between the contact regions 23c, 23d. The contact region 23a is electrically connected to a terminal S, the contact region 23b to a terminal G, the contact region 23c to a terminal V1, and the contact region 23d to a terminal V2.
For example, when a driving current flows from the terminal S to the terminal G, the current flows into the contact region 23b in the semiconductor region 22 through the contact region 23a. In this case, the current mainly flows near the surface of the semiconductor region 22 so that the current mainly includes a component flowing in parallel to the surface of the semiconductor region 22, which is defined as a chip surface. At this time, when the magnetic field including a perpendicular component perpendicular to the current, i.e., perpendicular to the chip surface, is applied to the cell, the Hall voltage is generated between the terminals V1, V2 according to Hall effect. Here, an arrow B shown in
Although the above Hall cell is a lateral type Hall device, a vertical Hall device as a vertical type Hall device as a comparison of the Hall device according to the first embodiment is prepared.
In the semiconductor region 32, a diffusion layer 34 having P conductive type as a P conductive type diffusion separation wall is formed to contact the semiconductor substrate 31 so that the diffusion layer 34 separates the Hall cell from other parts. Multiple contact regions 33a-33e are formed in the semiconductor region 32, and the contact regions 33a-33eare surrounded by the diffusion layer 34. Specifically, the contact regions 33a-33e are disposed in a region, i.e., an active region, which is surrounded with the diffusion layer 34. The contact regions 33a-33e are formed by increasing the impurity concentration selectively. The contact regions 33a-33e have the N conductive type. Thus, each contact region 33a-33e is connected to an electrode disposed on the contact region 33a-33e with excellent ohmic con tact. The contact regions 33a-33e are electrically connected to terminals S, G1, G2, V1, V2, respectively, through the electrodes and wirings.
Further, the active region surrounded with the diffusion layer 34 is divided into three regions 32a-32c so that P conductive type diffusion layers 34a, 34b as a P conductive type diffusion separation wall are separated by a PN junction separation wall disposed at an interface between the diffusion layers 34a, 34b and the regions 32a-32c. The diffusion layers 34a, 34b contact the substrate 32 so that the regions 32a-32c are electrically separated each other.
Further, in the regions 32a-32c, the contact regions 33a, 33d, 33e are disposed in the region 32a, the contact region 33b is disposed in the region 32b, and the contact region 33c is disposed in the region 32c. The contact region 33a is sandwiched between the contact regions 33b, 33c and the contact regions 33d, 33e, which are perpendicular to the contact regions 33b, 33c. Thus, the contact region 33a is disposed to face both of the contact regions 33b, 33c through the diffusion layers 34a, 34b.
In the Hall device, a region sandwiched between the contact regions 33d, 33e , provides a magnetic field detection portion HP as a Hall plate. The detection portion HP is electrically separated from other portions in the region 32a. Thus, the Hall cell generates a Hall voltage signal corresponding to the magnetic field applied to the detection portion HP.
Here, for example, a driving current flows from the terminal S to the terminal G1 and from the terminal S to the terminal G2. The driving current has a predetermined constant current. The driving current flows from the contact region 33a disposed on the substrate 31 to the contact regions 33b, 33c through the detection portion HP and the embedded layer BL. In this case, in the magnetic field detection portion HP, the current having a component perpendicular to the chip surface flows through the detection portion HP. Therefore, when the driving current flows through the detection portion HP, the magnetic field including a component parallel to the chip surface is applied to the detection portion HP in the Hall cell. The magnetic field B is shown in
Further, to increase the sensitivity of the Hall cell, another Hall device has been studied. The Hall device is shown in
Thus, the magnetic field component parallel to the chip surface applied to the detection portion HP is detected by the vertical type Hall device shown in
However, the epitaxial substrate is necessitated to provide these vertical type Hall devices. Therefore, the design degree of freedom is limited to use the epitaxial substrate.
In view of the above limitation, a new vertical type Hall device and a method for manufacturing the Hall device according to a first embodiment of the present invention are provided.
The vertical Hall device according to the first embodiment of the present invention is shown in
In general, a (100)-surface orientation in a silicon substrate has the smallest resistance change in accordance with a stress applied to the substrate among other surface orientations. The resistance change is caused by a Piezo electric effect. Therefore, when the Hall cell is formed of the substrate having the (100)-surface orientation, an offset voltage of the Hall device is reduced. The offset voltage is arisen from a stress application in a case where the Hall device is packaged.
Further, the N conductive type semiconductor substrate has large carrier mobility larger than that of the P conductive type semiconductor substrate. Therefore, it is preferred that the semiconductor region 12 in the Hall device is made of the N conductive type semiconductor layer. However, the semiconductor region 12 can be made of the P conductive type semiconductor layer. Specifically, the semiconductor region 12 can be made of the P− conductive type semiconductor layer. Further, as the impurity concentration of the semiconductor region 12 becomes smaller, the carrier mobility in the semiconductor region 12 becomes larger. In this case, the sensitivity of the Hall device as the magnetic field detection device is increased. This is, the output voltage as the detection signal becomes larger. Therefore, it is preferred that the impurity concentration of the semiconductor region 12 is small. On the other hand, as the carrier mobility of the semiconductor region 12 becomes larger, the temperature characteristics of the Hall voltage as the output signal deteriorates. Specifically, the Hall voltage is much changed in accordance with temperature change when the carrier mobility is large. Thus, the impurity concentration of the semiconductor region 12 is determined appropriately in view of the above relationships. The impurity concentration of the semiconductor region 12 is, for example, in a range between 1.0×1014/cm3 and 1.0×1017/cm3.
In the Hall device, a diffusion layer 14 as a P conductive type diffusion separation wall is formed so that the diffusion layer 14 separates the Hall cell from other parts. Multiple contact regions 13a-13e are formed on the surface of the semiconductor region 12. Specifically, the contact regions 13a-13e are disposed in an active region, which is surrounded with the diffusion layer 14. The contact regions 13a-13e are formed by increasing the impurity concentration selectively. The contact regions 13a-13e have the N conductive type. Each contact region 13a-13e is connected to an electrode disposed on the contact region 13a-13e with excellent ohmic contact. Further, each contact region 13a-13e is electrically connected to the terminal S, G1, G2, V1, V2, respectively, through the electrode and a wiring. The contact regions 13a, 13b provide a pair corresponding to a current supply pair, and the contact regions 13a, 13c provide another pair corresponding to another current supply pair. The contact regions 13d, 13e provide a pair corresponding to a voltage output pair.
The active region surrounding with the diffusion layer 14 is divided into three regions 12a-12c with PN junctions provided by an interface between diffusion layers 12, 14a, 14b. Specifically, three regions 12a-12c are separated with the P conductive type diffusion layers 14a, 14b as a P conductive type diffusion separation wall. Here, each diffusion layer 14a, 14b has a shallow diffusion depth shallower than the semiconductor region 12. Specifically, the depth of the diffusion layer 14a, 14b is smaller that that of the semiconductor region 12. The bottom of the semiconductor region 12 becomes narrower selectively so that the current path becomes narrower. The regions 12a-12c are electrically separated each other in the semiconductor region 12.
In the regions 12a-12c, the contact regions 13a, 13d, 13e are disposed on the region 12a, the contact region 13b is disposed on the region 12b, and the contact region 13c is disposed on the region 12c. The contact region 13a is sandwiched between the contact regions 13b, 13c, and is sandwiched between the contact regions 13d, 13e. A line connected between the contact regions 13d, 13e is perpendicular to another line connected between the contact regions 13b, 13c. Thus, the contact region 13a is disposed to face the contact region 13b, 13c through the diffusion layer 14a, 14b.
In the Hall device, the magnetic field detection portion HP as the Hall plate is provided by a region sandwiched between the contact regions 13d, 13e, the region which is disposed in the region 12a and separated from other parts. When the magnetic field is applied to the detection portion HP, the Hall voltage is generated. The Hall voltage as the output voltage corresponds to the magnetic field applied to the detection portion HP. The contact region 13a, which corresponds to one terminal of a pair of current supply terminals, is sandwiched between the contact regions 13a, 13e, which correspond to a pair of voltage output terminals. The contact regions 13b, 13c, which correspond to the other terminal of the current supply terminals, are disposed in line symmetry of the voltage output terminals. Thus, a component of the Hall voltage, which is generated in accordance with the current flowing in a lateral direction of the detection portion HP, i.e., the current flowing in parallel to the chip surface, is cancelled. Thus, the magnetic field component parallel to the chip surface can be detected with high accuracy. Further, the diffusion layers 14a, 14b prevent the current from flowing in the lateral direction, i.e., the direction parallel to the chip surface. Thus, the detection accuracy is much improved.
Here, for example, a driving current flows from the terminal S to the terminal G1 and from the terminal S to the terminal G2. The driving current has a predetermined constant current. The driving current flows from the contact region 13a disposed on the substrate 11 to the contact regions 13b, 13c through the detection portion HP and the bottom of the diffusion layers 14a, 14b. In this case, in the magnetic field detection portion HP, the current having a component perpendicular to the chip surface flows through the detection portion HP. Therefore, when the driving current flows through the detection portion HP, the magnetic field including a component parallel to the chip surface is applied to the detection portion HP in the Hall cell. The magnetic field B is shown in
Thus, in the vertical Hall device, the N conductive type impurity is doped and diffused on the surface of the semiconductor substrate 11 so that the semiconductor region 12 as the diffusion well is formed. Accordingly, the Hall device can be made of the single conductive type substrate. The design degree of freedom for selecting the substrate composing the Hall device is increased. Further, the Hall device has no embedded layer BL shown in
Next, the detailed construction of the Hall device is described with reference to
In general, when an impurity is doped on the surface of a semiconductor substrate and the impurity is diffused in the substrate so that a diffusion layer is formed, a width of the diffusion layer in the substrate becomes narrower as a depth from the surface of the substrate becomes deeper. Therefore, in a vertical Hall device having a magnetic field detection portion divided by the diffusion layer, for example, in the device shown in
In the vertical Hall device shown in
A dimension A shown in
The Hall device can include a signal processing circuit, a compensation circuit and a temperature compensation circuit. The signal processing circuit processes the Hall voltage outputted from the Hall cell on the basis of a predetermined signal processing. The compensation circuit computes and compensates the offset voltage. The temperature compensation circuit computes and compensates the temperature deviation of the Hall voltage.
The periphery circuit portion C10 includes a CMOS (i.e., complementary metal oxide semiconductor) circuit. The circuit portion C10 further includes multiple FETs (i.e., field effect transistor) having channels composed of the semiconductor substrate 11, a N conductive type semiconductor region C12 as a N well, and a P conductive type diffusion layer C13 as a P well. In the FET, a N conductive type diffusion layers C13a-C13d as a N+ diffusion layer provide a source, and a P conductive type diffusion layers C13e, C13f as a P+ diffusion layer provide a drain. To control the current flowing between the source and the drain, gate insulation films I1a-I1c are formed, and gate electrodes G1a-G1c are formed of a poly crystalline silicon. The FETs are separated each other with a field oxide film (i.e., a LOCOS oxide film) CL1 having a LOCOS (i.e., local oxidation of silicon) construction. Further, an insulation film 15 made of PSG (i.e., phosphor silicate glass) is formed on the field oxide film CL1. Each diffusion layer C13a-C13f is connected to a wiring, i.e., an electrode C16a-C16f through a contact hole formed in the insulation film 15. The electrode C16a-C16f is made of aluminum.
Thus, the Hall device includes the CMOS circuit as a periphery circuit. Thus, the following advantages are expected.
The Hall device with the periphery circuit can be integrated with high density, i.e., the dimensions of the Hall device can be minimized. Therefore, when the Hall device includes the compensation circuit, the compensation circuit can compensate the output signal with high accuracy. Further, the Hall device with the periphery circuit portion C10 can include a high-speed circuit. For example, when the Hall device is used for a rotation sensor, the Hall device is required to detect a high-speed rotation with high accuracy. In this case, the CMOS circuit as the periphery circuit provides the high-speed circuit so that the Hall device can detect high speed rotation with high response speed. Thus, the Hall device can detect the rotation with high accuracy.
Further, the Hall device has small energy consumption, since the CMOS is used as the periphery circuit. Specifically, standby power consumption of the CMOS is low so that the Hall device totally consumes small energy. Therefore, when the Hall device is energized from a battery, the battery can supply energy to the Hall device for a long time.
Furthermore, the Hall device and the periphery circuit can be integrated into one chip. Therefore, a manufacturing cost of the Hall device is reduced.
Further, in the vertical Hall device, the contact regions 13d, 13e corresponding to a pair of voltage output terminals output the Hall voltage as a Hall voltage signal in such a manner that the Hall voltage signal is outputted through a wiring having a variable resistance.
Next, as shown in
Firstly, a silicon substrate 11 having the P conductive type is prepared. The substrate 11 has a principal surface of a (100)-surface orientation. Then, a mask (not shown) having a predetermined pattern is formed on the substrate 11 so that the N conductive type impurity such as phosphorous is doped on the surface of the substrate 11. Further, the substrate 11 is annealed if necessary. Thus, the N conductive type semiconductor region 12 and another semiconductor region C12 are formed as a diffusion layer.
As shown in
As shown in
Then, the substrate 11 is thermally oxidized so that the gate insulation films I1a-I1c are formed. The gate insulation films I1a-I1c are made of silicon oxide. The gate electrodes G1a-G1c are formed on the gate insulation films I1a-I1c. The gate electrodes G1a-G1c are made of poly crystalline silicon. Specifically, the poly crystalline silicon film is deposited by a LP-CVD (i.e., low pressure chemical vapor deposition) method. A conductive impurity such as phosphorous is doped in the polycrystalline silicon film by a thermal diffusion method. After that, the poly crystalline silicon film is selectively etched so that the gate electrodes G1a-G1c are formed at a predetermined position.
Next, the N conductive type impurity such as arsenic and the P conductive type impurity such as boron are doped by an ion implantation method at a predetermined position by using a photo mask having a predetermined pattern. Then, the substrate 11 is annealed if necessary. Thus, the contact regions 13a-13e and the diffusion layers C 3a-C13f are formed. Here, the diffusion layers C13a-C13f can be formed by using the LOCOS oxide film Cl1 or the gate electrodes G1a-G1c as a mask of self-alignment. Further, a sidewall and/or a silicide are formed at this time.
Further, the insulation film 15 made of PSG is formed by the thermal CVD method. The insulation film 15 is appropriately patterned so that a contact hole is formed. Then, the wiring is formed to fill the contact hole. The wiring is made of aluminum. The wiring is patterned if necessary. Thus, the wirings 16a-16c, C16a-C16f are formed between the contact regions and the diffusion layers with excellent ohmic contact. Thus, the Hall cell portion 10 and the periphery circuit portion C10 are completed.
In the above method for manufacturing the Hall device, the Hall cell portion 10 is manufactured together with the periphery circuit portion C10, and therefore, the manufacturing process for manufacturing the Hall device is reduced. Specifically, the number of the process is reduced.
Thus, the vertical Hall device according to the first embodiment has the following advantages.
(1) The semiconductor region 12 is provided by the diffusion layer (i.e., the N well), which is formed by doping and diffusing the conductive impurity in the semiconductor substrate. Thus, the Hall device can be formed from the substrate having a single conductive type. Thus, the selecting degree of freedom for selecting the substrate composing the vertical Hall device is increased.
(2) The Hall device is formed from the substrate having the single conductive type. The cost of the substrate having the single conductive type is lower than that of the epitaxial substrate. Therefore, the manufacturing cost of the Hall device is reduced.
(3) The semiconductor region 12 has the maximum impurity concentration near the chip surface. The impurity concentration of the semiconductor region 12 is reduced as the depth from the chip surface becomes deeper. Therefore, the semiconductor region 12 can be formed by a conventional semiconductor process. For example, the semiconductor region 12 is manufactured in such a manner that the conductive impurity is doped on the surface of the chip by the ion implantation method, and the impurity is diffused by the thermal diffusion method.
(4) The N conductive type semiconductor region 12 is surrounded with the P conductive type semiconductor substrate 11. Thus, the PN junction is formed between the semiconductor region 12 and the substrate 11 so that the semiconductor region 12 including the magnetic field detection portion HP is electrically separated from other parts. Thus, the Hall cell is separated from other parts appropriately.
(5) The P conductive type diffusion layers 14a, 14b for providing the current path are formed in the semiconductor region 12 by narrowing the semiconductor region 12 near the bottom. The magnetic field detection portion HP is electrically divided by the diffusion layers 14a, 14b. Thus, the vertical Hall device for detecting the magnetic field parallel to the chip surface has high sensitivity. Further, the diffusion layers 14a, 14b are formed by the conventional semiconductor process such as a CMOS process so that the Hall device can be manufactured easily.
(6) The diffusion layers 14a, 14b are formed in the semiconductor region 12 in such a manner that the depth of the diffusion layer 14a, 14b is shallower than that of the semiconductor region 12. Accordingly, the vertical Hall device has high sensitivity, and the Hall device can be manufactured easily.
(7) The diffusion depth of the diffusion layer 14a, 14b is equal to or deeper than 2 μm. The current flowing through the magnetic field detection portion HP is limited from expanding in the horizontal direction effectively. Thus, the sensitivity of the Hall device is improved. However, the diffusion depth of the diffusion layer 14a, 14b can be another although the depth is preferably equal to or deeper than 2 μm.
(8) The diffusion layer 14a, 14b has the maximum impurity concentration near the chip surface, and the impurity concentration of the semiconductor region 12 is reduced as the depth from the surface becomes deeper. Thus, the current flowing through the magnetic field detection portion HP is limited from expanding in the horizontal direction so that the current component flowing in the vertical direction is relatively increased. Thus, the sensitivity of the Hall device is improved.
(9) The impurity concentrations of the semiconductor region 12 and the diffusion layers 14a, 14b are controlled to prepare the current path near the bottom of the semiconductor region 12 after the depletion layer is formed between the semiconductor region 12 and the diffusion layers 14a, 14b. Thus, the current path near the bottom of the semiconductor region 12 is prepared appropriately. Further, this preparation method can be performed only by controlling the impurity concentration.
(10) The current supply terminals and the voltage output terminals are formed on the surface of the semiconductor region 12. The current is supplied to the magnetic field detection portion HP from one terminal of the current supply terminals. When the current including the component perpendicular to the chip surface flows through the detection portion HP, and the magnetic field parallel to the chip surface is applied to the detection portion HP, the Hall voltage is generated between the voltage output terminals. The Hall voltage corresponds to the magnetic field. The Hall device having a sufficient performance for detecting the magnetic field is manufactured.
(11) The contact region 13a corresponding to one terminal of the current supply terminals is sandwiched and disposed between the contact regions 13a, 13e corresponding to the voltage output terminals. The Hall voltage corresponding to the current flowing through the detection portion HP is appropriately measured through the voltage output terminals.
(12) The contact region 13a is sandwiched between the contact regions 13d, 13e, and the contact regions 13b, 13c corresponding to the other terminal of the current supply terminals is disposed in line symmetry of a line connecting between the voltage output terminals. Thus, the magnetic field as a detection object can be detected with high accuracy.
(13) A pair of the current supply terminal is perpendicular to a pair of the voltage output terminals. This construction provides an excellent device characteristics of the Hall device although the construction is simple.
(14) The contact regions 13a-13e as the current supply terminal and the voltage output terminals are formed on the surface of the semiconductor region 12 by increasing the impurity concentration selectively. Thus, the electrode disposed on the contact region 13a-13e and the contact region 13a-13e are connected with excellent ohmic contact so that the current supply for supplying the contact region 13a-13e and the voltage output for outputting from the contact region 13a-13e are effectively performed.
(15) The Hall voltage signal outputting from the contact regions 13d, 13e corresponding to the voltage output terminals is outputted through the wiring system, which is capable of controlling it's resistance. The wiring system has multiple wirings, which are connected in parallel each other. Further, the wirings having different resistances are connected and disconnected between the voltage output terminals V1, V2 so that the wiring system provides different resistance. Thus, the offset voltage is compensated and reduced.
(16) The current flowing through the detection portion HP flows in a tilt direction slanted from the vertical direction. This current includes the component perpendicular to the chip surface, which flows through the detection portion HP. Thus, the Hall device can detect the magnetic field parallel to the chip surface.
(17) The substrate 11 is made of the silicon substrate having the (100)-surface orientation. Therefore, the offset voltage caused by the stress applied to the substrate when the device is packaged is reduced.
(18) Since the substrate 11 is made of silicon, the Hall device is manufactured with low cost. This is because the silicon substrate is processed in a conventional semiconductor process, and the characteristics of the silicon substrate have been studied sufficiently.
(19) The Hall device has no embedded layer BL. Thus, the offset voltage is reduced. Further, the temperature characteristics of the magnetic field detection sensitivity is improved. Thus, the temperature compensation circuit is simplified and minimized.
(20) The Hall device with the periphery circuit is integrated into one chip. This Hall device can be used for a magnetic sensor such as an angular detection sensor. The Hall device is provide by a Hall IC.
(21) The Hall device includes the CMOS circuit as the periphery circuit. Thus, the Hall device can be manufactured by a conventional CMOS process together with manufacturing the CMOS circuit.
(22) The number of process of the manufacturing method described above is reduced.
(23) The semiconductor region 12 is formed by doping and diffusing the conductive impurity in the semiconductor substrate 11. The substrate 11 can be made of an epitaxial substrate or a SOI (i.e., silicon on insulator) substrate. Therefore, the selecting degree of freedom for selecting the substrate composing the Hall device is increased.
(24) Further, the semiconductor region 12 is formed in such a manner than the N conductive type impurity is doped on the surface of the substrate 11 by the ion implantation method and then the N conductive type impurity is diffused in the substrate 11 by the heat treatment. Thus, the impurity concentration of the semiconductor region 12 has the maximum impurity concentration near the surface, and is decreased as the depth from the surface becomes deeper. The semiconductor region 12 is easily manufactured by the conventional semiconductor process. Since the semiconductor region 12 has a simple construction and is formed with low cost, the Hall device can be manufactured in mass production.
The impurity concentrations of the semiconductor region 12 and the diffusion layers 14a, 14b are controlled to provide the current path near the bottom of the semiconductor region 12 after the depletion layer is formed between the semiconductor region 12 and the diffusion layers 14a, 14b. However, in a case where the diffusion layers 14a, 14b are formed by the ion implantation method, the current path near the bottom of the semiconductor region 12 can be prepared by controlling the implantation energy.
Although the Hall cell portion 10 is manufactured together with the periphery circuit portion C10, the Hall cell portion 10 and the periphery circuit portion C10 can be manufactured individually.
Although the switches SW11-SW14, SW21-SW24 are used for connecting and disconnecting the wirings, a fuse or a thin film resistor can be used for connecting and disconnecting the wirings. The fuse disconnects itself when excess current flows through the fuse. The thin film resistor is capable of disconnecting the wire by trimming. Further, the fuse or the thin film resistor can be formed at least one of the voltage output terminals. Thus, the Hall voltage is outputted from the voltage output terminals, at least one of which is capable of changing the Hall voltage signal. Thus, when a variable resistance device is used for the wirings, the wiring system provides different resistance so that the offset voltage is compensated and reduced.
Although the diffusion layer 14a, 14b has the maximum impurity concentration near the chip surface, the diffusion layer 14a, 14b can have the minimum impurity concentration near the chip surface, and the impurity concentration of the semiconductor region 12 is increased as the depth from the surface becomes deeper. This type Hall device as a modification of the first embodiment is shown in
When the current flows from the contact region 13a to the contact region 13c, the current including the component perpendicular to the chip surface flows through the magnetic field detection portion HP, shown as an arrow in
In this case, the following advantage is obtained.
(25) The component of the current perpendicular to the chip surface flowing through the magnetic field detection portion HP can be increased comparatively. Thus, the sensitivity (i.e., the product sensitivity) of the Hall device is increased.
(26) The diffusion layer 14a, 14b has the minimum impurity concentration near the chip surface, and the impurity concentration of the semiconductor region 12 is increased as the depth from the surface becomes deeper. In this case, the impurity concentration of the semiconductor region 12 can be easily controlled with high design degree of freedom.
The above manufacturing method has the following advantages.
(27) Two high impurity concentration layers having different conductive types composing the diffusion stopper layer ST and the semiconductor region H12 are laminated on the substrate 11. Then, the epitaxial film composing the region L12 is formed on the substrate. These processes can be performed by a conventional semiconductor process easily.
Next, another manufacturing method for manufacturing the semiconductor region 12 is described with reference to
(28) The diffusion stopper layer ST prevents the conductive impurity from diffusing into the substrate 11. Further, the semiconductor region 12 can be formed by a conventional semiconductor process.
The impurity concentration of the semiconductor region 12 can have the maximum impurity concentration at a predetermined depth from the chip surface, as shown in
When the current flows from the contact region 13a to the contact region 13c, the current flows through a portion having low resistance, the portion which has the high impurity concentration. Specifically, the current firstly flows from the contact region 13a in the vertical direction. Then, the current flows through the semiconductor region 12 having the maximum impurity concentration. Then, the current flows to the contact region 13c. Thus, the current having the component perpendicular to the chip surface flows through the magnetic field detection portion HP. This Hall device has the following advantages.
(29) In the Hall device, the current having the component perpendicular to the chip surface is comparatively increased so that the sensitivity of the Hall device is increased.
The Hall device shown in
The above method has the following advantage.
(30) The ion implantation of the N conductive type impurity into the inside of the substrate 11 is performed by a conventional semiconductor method, which is suitably used for the SOI substrate manufacturing method.
Next, another manufacturing method is shown in
(31) This method can be performed by a conventional semiconductor process.
A vertical Hall device having a Hall cell portion 10 and a periphery circuit portion C10 according to a second embodiment of the present invention is shown in
A vertical Hall device according to a third embodiment of the present invention is shown in
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(32) The construction of the Hall device is simplified. Further, the dimensions of the Hall device are reduced.
A vertical Hall device according to a fourth embodiment of the present invention is shown in
The manufacturing method of the Hall device is described as follows.
The insulation separation wall is formed by the STI method. Specifically, a silicon oxide film as a pad oxide film and a silicon nitride film are deposited on the substrate 11. Then, the substrate 11 is selectively etched by using the photo-lithography method so that the trenches T1, T2a, T2b are formed on the substrate 11 at a predetermined position. Next, the insulation films IL1, IL2a, IL2b are embedded in the trenches T1, T2a, T2b by the CVD method or the like. At this time, the insulation film outside of the trenches T1, T2a, T2b are removed by, for example, CMP (i.e., chemical mechanical polishing) method. Then, the pad oxide film and the silicon nitride film are removed from the substrate. Thus, the insulation separation wall is formed.
Here, the STI method is used in the conventional CMOS process such as a part separation wall. Therefore, the insulation separation wall can be formed by the conventional semiconductor process. Further, the insulation separation wall having the shallow depth shallower than the semiconductor region 12 is easily formed by the STI method since the STI method is suitably used for forming the part separation wall.
The insulation separation wall having the STI construction includes a trench, and therefore, the insulation separation wall is easily formed on the surface of the substrate 11 vertically. Thus, the current flowing through the detection portion HP is limited from broadening so that the component of the current flowing in the vertical direction is increased comparatively. Accordingly, the sensitivity of the Hall device is improved.
Further, the deviation of the temperature characteristics of the magnetic field detection sensitivity is reduced. Accordingly, the temperature compensation circuit is minimized.
Furthermore, as shown in
A vertical Hall device according to a fifth embodiment of the present invention is shown in
When the trench T1, T2a, T2b is formed in the substrate 11, the inner wall of the trench T1, T2a, T2b is damaged. Therefore, a carrier is recombined at a damaged layer ion the inner wall of the trench T1, T2a, T2b. However, when the impurity layer D1 is formed on the inner wall of the trench T1, T2a, T2b, the impurity layer D1 prevents the carrier from recombining. Accordingly, the carrier mobility in the semiconductor region 12 is improved so that the mobility is not reduced. Further, a depletion layer at a PN junction between the impurity layer D1 and the semiconductor region 12 can penetrate into the device deeply. Accordingly, the thickness D of the detection portion HP is substantially narrowed. Thus, the sensitivity of the Hall device is improved.
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(33) The sensitivity of the Hall device is increased.
Further, as shown in
A vertical Hall device according to a fifth embodiment of the present invention is shown in
In general, an interlayer insulation film such as the insulation film 15 formed on a chip surface of a Hall device includes a movable ion such as sodium ion. Therefore, the movable ion is displaced in accordance with energizing the Hall device or temperature change, so that an electric potential near an voltage output terminal disposed on the chip surface may become unstable. Accordingly, the Hall voltage signal outputted from the Hall device is fluctuated. This fluctuation is a drift of the Hall voltage signal or a fluctuation with time, which generates a detection error of the magnetic field. When the Hall device is used for an angular detection sensor, the sensor characteristics are deteriorated by the drift.
However, the field oxide film HL1 covers the Hall device, i.e., the semiconductor region 12, the movable ion is prevented from generating the drift. Thus, the detection accuracy of the Hall device is improved. Further, the field oxide film HL1 can be formed together with the field oxide film CL1. The field oxide film HL1 protects the Hall device from damage caused in an ion implantation process, a plasma process or the like. Specifically, after the Hall cell portion 10 is formed in the device, the ion implantation process or the plasma process is performed to form the periphery circuit portion C10. In this case, the field oxide film HL1 protects the Hall cell portion 10. Therefore, the field oxide film HL1 is used for manufacturing the Hall device to integrate into one chip.
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(34) The influence of the movable ion for reducing the detection accuracy is limited in the Hall device. Further, the damage in the manufacturing process is reduced by the field oxide film HL1.
Although the field oxide film HL1 covers whole surface of the device except for the contact regions 13a-13e, the field oxide film HL1 can only cover the semiconductor region 12. In this case, the above advantage of (34) is also obtained.
A vertical Hall device according to a seventh embodiment of the present invention is shown in
When a reverse bias is applied between the impurity layer D2 and the semiconductor region 12, the reverse bias provides the depletion layer near a PN junction between the impurity layer D2 and the semiconductor region 12. This depletion layer protects the surface of the device from the movable ion. Thus, the influence of the movable ion is reduced so that the detection accuracy of the Hall device is improved.
A vertical Hall device according to an eighth embodiment of the present invention is shown in
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(35) The ground plate GP improves the detection accuracy of the Hall device and the noise resistance of the device.
Although the ground plate GP is fixed to the ground potential, the ground plate GP can be fixed to another potential such as a power source potential.
Although the diffusion layers 14, 14a, 14b are also fixed to the ground potential to increase the fixation of the potential, The diffusion layers 14, 14a, 14b can not be always fixed to the ground potential.
Although the ground plate GP covers the chip surface, the ground plate GP can be formed on a part of the chip surface or the ground plate GP can be divided into multiple parts. In this case, the ground plate GP is applied with a predetermined voltage so that the resistance distribution of the detection portion HP is variable. In this case, the ground plate GP is disposed appropriately so that the resistance distribution of the detection portion HP at a predetermined position is variable. Thus, the potential distribution in the device is changed so that the offset voltage of the Hall device is reduced. Specifically, imbalance of the potential distribution in the device is compensated by changing the potential distribution. Thus, the offset voltage is reduced without a compensation circuit or with a simple compensation circuit. Thus, the dimensions of the compensation circuit are reduced.
A vertical Hall device according to a ninth embodiment of the present invention is shown in
In general, the Hall voltage detected by the Hall device is small. The magnetic field is detected by measuring the small Hall voltage change with high accuracy. Therefore, the noise, which comes from the outside of the device, or a charge-up according to the driving current of the Hall device may affect the potential of the Hall device. In this case, the detection accuracy of the Hall device is reduced.
However, the ground plate GP covering the semiconductor region 12 electrically connects to the diffusion layers 14, 14a, 14b disposed in the semiconductor region 12. Thus, the electric potential of the Hall device is stabilized so that the detection accuracy of the device is improved.
Further, as shown in
A Hall device according to a tenth embodiment of the present invention is shown in
In this device, the output voltage Vx from the cell 102 is a sine curve, and the output voltage Vy from the cell 101 is a cosine curve. Even when the output voltages are changed in accordance with temperature change so that the output voltages become Vx′ and Vy′, the changes of the output voltages can be cancelled as follows. For example, when the changes of the output voltages are defined as V, the output voltages Vx′, Vy′ are shown as:
Vx=V sin θ; and
Vy=V cos θ.
In this case, the changes of the output voltages can be cancelled to computing a ratio of the output voltages Vx′, Vy′ as follows:
Vx/Vy=sin θ/cos θ=tan θ.
Thus, the changes of the output voltages are cancelled.
Accordingly, the Hall cells 101, 102 can detect the magnetic component parallel to the substrate 11 with high accuracy by computing the Hall voltage signals outputted from the Hall cells. Thus, the Hall device detects the magnetic field around 360°. Further, the Hall cell 70 detects the magnetic component perpendicular to the substrate 11. Thus, the Hall device can detect the magnetic field three-dimensionally. Specifically, the Hall device can independently detect three magnetic components in the X, Y, and Z directions. Accordingly, the Hall device works as a three-dimensional magnetic sensor.
A vertical Hall device according to an eleventh embodiment of the present invention is shown in
Specifically, the Hall cell 101 includes two terminals G1, G2, and the adjacent Hall cell 102 includes a terminal S, which is connected to the terminals G1, G2 in parallel. Then, the Hall cell 103 next to the Hall cell 102 includes a terminal S, which is connected to two terminals G1, G2 of the Hall cell 102 in parallel. Thus, the Hall cell 10n is connected to the Hall cell 101 in series. The terminal S of the Hall cell 101 is connected to a terminal S0, and the terminals G1, G2 of the Hall cell 10n are connected to a terminal G0. Each Hall cell 101-10n is energized through the terminals S0, G0.
Since the Hall cells are connected in series, the Hall voltage signal outputted from the Hall device becomes larger. Thus, the detection sensitivity of the device is improved.
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(36) The magnetic field detection sensitivity, i.e., the product sensitivity of the device is increased.
A vertical Hall device according to a twelfth embodiment of the present invention is shown in
Specifically, two terminals G1, G2 of each Hall cell 101-10n are connected to the terminal G0 in parallel, and the terminal S of each Hall cell 101-10n is connected to the terminal S0 in parallel. Thus, the Hall cells 101-10n are connected in parallel. Each Hall cell 101-10n is energized through the terminals S0, G0.
In general, when multiple Hall cells are manufactured in mass production, or when multiple Hall cells are integrated into one chip, the Hall cells have deviations of the output voltages and/or the offset voltages. However, since the Hall device according to the twelfth embodiment includes multiple Hall cells connected each other in parallel, the Hall voltage signal outputted from the device and the offset voltage of the device are normalized so that the detection accuracy of the device is improved.
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(37) The magnetic field detection accuracy of the device is increased.
A Hall device according to a thirteenth embodiment of the present invention is shown in
The Hall cells 101, 102 can detect the magnetic component parallel to the substrate 11 with high accuracy by computing the Hall voltage signals outputted from the Hall cells. Thus, the Hall device detects the magnetic field around 360°.
Here, it is considered that the sensor characteristics of two Hall cells 101, 102 may be varied in the manufacturing process. Therefore, to reduce the variation between the Hall cells 101, 102, it is preferred that a distance between the Hall cells 101, 102 is equal to or smaller than 100 μm. Thus, the variation between the Hall cells 101, 102 caused in the manufacturing process is reduced so that the sensor characteristics between the cells 101, 102 are uniformed. Further, another variation between the cells 101, 102 caused by, for example, temperature change is also reduced.
In this case, the Hall device has the advantages described above, which are described in advantages of (1) to (24). In addition, the Hall device has the following advantage.
(38) The Hall device can detect the magnetic field around 360° with high accuracy.
Although the cells 101, 102 are perpendicularly disposed, an angle between the cells 101, 102 can be another angle. For example, the angle between the cells 101, 102 can be a sharp angle.
A Hall device according to a fourteenth embodiment of the present invention is shown in
As shown in
A Hall device according to a fifteenth embodiment of the present invention is shown in
In general, the output voltage of the Hall cell is in proportion to the carrier mobility in the magnetic field detection portion HP. The carrier mobility depends on the crystal structure, i.e., atomic arrangement. Here, the Piezo resistance in accordance with the mechanical stress applied to the substrate 11 also depends on the crystal structure. Therefore, it is important for the Hall cell to arrange the cell parallel to a predetermined crystal axis. Specifically, when multiple Hall cells are integrated into one chip, it is important to arrange the cells to be parallel to the predetermined crystal axis. In the above Hall device, the deviation between the cells 101, 102 is reduced since the crystal axis parallel to the cell 101, 102 is determined appropriately. Specifically, the deviation of each Hall voltage outputted from the cell 101, 102 is reduced. Further, the deviation of each resistance change in accordance with the stress applied to the substrate 11 caused from the Piezo resistance effect is reduced. Thus, the detection accuracy of the device is improved.
Although the Hall cell is parallel to the <001> direction or the <010> direction, the Hall cell can be parallel to another direction. Here, the single silicon crystal has a diamond type crystal structure, and therefore, the <001>, the <010>, the <00-1>, the <0-10> directions are equivalent. Therefore, the Hall cell can be parallel to a <011> direction (or a <0-1-1> direction) and a <0-11> direction (or a <01-1> direction), as shown in
Although the Hall device includes two cells 101, 102, the Hall device can have multiple cells such as three cells 101, 102, 103.
As shown in
A Hall device according to a sixteenth embodiment of the present invention is shown in
Although the Hall cell 101, 102 is parallel to the <001> direction or the <010> direction, the Hall cell can be parallel to another direction. As shown in
Although the Hall device includes two cells 101, 102, the Hall device can have multiple cells such as three cells.
A Hall device according to a seventeenth embodiment of the present invention is shown in
Although the Hall device shown in
Although the current supply terminals S, G1, G2 are disposed perpendicularly to the voltage output terminals V1, V2, the current supply terminals S, G1, G2 and the voltage output terminals V1, V2 can be disposed in line. In this case, the Hall device can have no diffusion layer 14, 14a, 14b. Even when the Hall device has no diffusion layer 14, 14a, 14b, the current including the component perpendicular to the substrate 11 can flow through the magnetic field detection portion HP. Further, one of the current supply terminals S, G1, G2 can be disposed on the bottom of the substrate 11 so that the other one of the current supply terminals S, G1, G2 faces the one of the current supply terminals S, G1, G2 in the vertical direction of the substrate 11. In this case, even when the Hall device has no diffusion layer 14, 14a, 14b, the current including the component perpendicular to the substrate 11 can flow through the magnetic field detection portion HP.
Although the current supply terminals S, G1, G2 and the voltage output terminals V1, V2 are disposed on the contact regions 13a-13e, the impurity concentration of each of which is selectively increased, the current supply terminals S, G1, G2 and the voltage output terminals V1, V2 can be disposed on the semiconductor region 12 directly.
Although the periphery circuit C10 is formed of the CMOS circuit, the periphery circuit C10 can be formed of another circuit such as a bipolar circuit.
Although the Hall device shown in
In the Hall device, the P conductive type can be exchange to the N conductive type. For example, although the semiconductor region 12 has the P conductive type, the semiconductor region 12 can have the N conductive type.
Although the substrate 11 is made of silicon, the substrate 11 can be made of another material such as GaAs, InSb, InAs, SiC, or Ge. Specifically, when the substrate is made of GaAs or InAs, the Hall device can have high sensitivity since the material such as GaAs and InAs has excellent temperature characteristics. In this case, the Hall cell is disposed in parallel to a certain direction, which has small resistance change in accordance with the stress applied to the substrate 11 caused by the Piezo resistance effect.
Although the substrate 11 is made of a single conductive type substrate, the substrate 11 can be made of an epitaxial substrate, a SOI (i.e., silicon on insulator) substrate, or a maltilayer substrate having different conductive type layers (e.g., the substrate has a P—N—P—N—P, or a N—P—N—P—N construction).
Such changes and modifications are to be understood as being within the scope of the present invention as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-100841 | Mar 2004 | JP | national |
| 2005-124460 | Apr 2004 | JP | national |
| 2005-5653 | Jan 2005 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11082023 | Mar 2005 | US |
| Child | 11819544 | Jun 2007 | US |
